Assignment - 4, Solutions
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Ali AbrarAssignment - 4, Solutions
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Ali AbrarP.1. For the following C statement, write the corresponding RISC-V assembly code.
Assume that
the C variables f, g, and h, have already been placed in registers x5, x6, and x7 respectively. Use
a minimal number of RISC-V assembly instructions (12 marks).
f = g + (h − 5);
Answer:
addi x5, x7,-5
add x5, x5, x6
[addi f,h,-5 (note, no subi) add f,f,g]
P.2. For the following C statement, write the corresponding RISC-V assembly code. Assume that
the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively.
Assume that the base address of the arrays A and B are in registers x10 and x11, respectively.
B[8] = A[i−j] (20 marks);
Answer:
sub x30, x28, x29 // compute i-j
slli x30, x30, 3 // multiply (i-j) by 8 to convert to double-word size
add x30, x10, x30 // compute address of A[i-j] by adding offset x30 to based address x10
ld x31, 0(x30) / load A[i-j]
sd x31, 64(x11) //// store in B[8]
P.3. Write a single C statement that corresponds to the two RISC-V assembly instructions below
(8 marks).
add f, g, h
add f, i, f
Answer: f = g+h+i
P.4, For the RISC-V assembly instructions below, what is the corresponding C statement?
Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29,
respectively. Assume that the base address of the arrays A and B are in registers x10 and x11,
respectively (10 marks).
slli x30, x5, 3 // x30 = f*8
add x30, x10, x30 // x30 = &A[f]
slli x31, x6, 3 // x31 = g*8
add x31, x11, x31 // x31 = &B[g]
1
ld x5, 0(x30) // f = A[f]
addi x12, x30, 8 // x12=&A[f+1]
ld x30, 0(x12) // x30=A[f+1]
add x30, x30, x5 //x30=A[f]+x[f+1]
sd x30, 0(x31) //B[g]=x30=A[f]+A[f+1]
Answer:
B[g]= A[f] + A[f+1]
P.5. Provide the instruction type, assembly language instruction, and binary representation of
instruction described by the following RISC-V fields (20 marks):
opcode=0x3, funct3=0x3, rs1=27, rd=3, imm=0x4
Answer:
Type: I-type
Assembly language instruction: ld x3, 4(x27)
Binary representation: 0000 0000 0100 1101 1011 0001 1000 0011)
P.6. Assume that we would like to expand the RISC-V register file to 128 registers and expand
the instruction set to contain four times as many instructions (30 marks).
a) How would this affect the size of each of the bit fields in the R-type instructions?
b) How would this affect the size of each of the bit fields in the I-type instructions?
c) How could each of the two proposed changes decrease the size of a RISC-V assembly
program? On the other hand, how could the proposed change increase the size of an RISC-V
assembly program?
Answer:
a) The opcode would expand from 7 bits to 9.
The rs1, rs2, and rd fields would increase from 5 bits to 7 bits.
b) The opcode would expand from 7 bits to 9.
2
The rs1 and rd fields would increase from 5 bits to 7 bits. This change does not affect the
imm field per se, but it might force the ISA designer to consider shortening the immediate
field to avoid an increase in overall instruction size.
c) Increasing the size of each bit field potentially makes each instruction longer, potentially
increasing the code size overall.
However, increasing the number of registers could lead to less register spillage, which
would reduce the total number of instructions, possibly reducing the code size overall.
