Sample Questions 1
Uploaded by
Ali AbrarSample Questions 1
Uploaded by
Ali AbrarENGI9865
Advanced Digital Systems
Sample Questions 1
Prepared by Dr. Andrew House.
1 Logic Minimization
(a) Use Karnaugh maps to minimize the output logic for the 4-input (A, B, C, D), 2-output
(X, Y) function described by the truth table below.
A B C D X Y
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 1
0 0 1 1 0 0
0 1 0 0 1 1
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 1 0 0
1 0 1 0 1 x
1 0 1 1 0 x
1 1 0 0 1 x
1 1 0 1 1 x
1 1 1 0 1 x
1 1 1 1 1 x
(b) Use K-maps to minimize the following three 3-input logic functions:
X = AB ′ C ′ + ABC + ABC ′ + A′ B ′ C ′
Y = ABC + A′ B ′ C ′ + A′ BC
Z = A′ BC + AB ′ C + ABC ′ + A′ B ′ C + AB ′ C ′
ENGI9865 Sample Questions 1 1
2 Multiplexers
(a) Recall that a 2-to-1 multiplexer has 2 data inputs and 1 select line input. If the select
line is 0, then the data on input 0 is passed to the output; if the select line is 1, then
the data on input 1 is passed to the output. Write the truth table to represent this
functionality, then derive a Boolean circuit to implement it.
(b) Use VHDL to describe the circuit you designed in part (a). You will create an entity
called mux2 to 1 and use concurrent assignment statements to implement it in the
corresponding architecture.
(c) Write a VHDL testbench to simulate your multiplexer.
(d) A 4-to-1 multiplexer can be implemented by composing 3 2-to-1 muxes. Similarly, an
8-to-1 mux can be implemented from two 4-to-1 muxes and a 2-to-1 mux. Draw circuit
diagrams representing each of these cases.
(e) Write structural VHDL to describe a 4-to-1 mux (called mux4 to 1) composed out of
mux2 to 1 components.
(f) Write structural VHDL to describe an 8-to-1 mux (called mux8 to 1) composed out of
mux4 to 1 and mux2 to 1 components.
3 Sequence Detector Design
In this question you must design a Moore machine to detect the sequence “10101”. When
the sequence is detected, the system will output a ‘1’ for 1 cycle.
(a) Draw a block diagram to represent the top-level, black-box view of this system.
(b) Draw the state transition diagram for a state machine that implements the desired
functionality.
(b-2) Draw the ASM chart for a state machine that implements the desired functionality.
(c) Write out the state transition table and output expressions.
(d) Determine an encoding for the states that uses the fewest number of D-type flip-flops
possible.
(e) Rewrite the state transition table and output expressions using the state encodings
chosen in part (d).
(f) Derive expressions for next-state inputs and minimize if possible.
(g) Draw the complete circuit diagram for your final design.
ENGI9865 Sample Questions 1 2
(h) Write a VHDL description of this circuit, then write a testbench to test it functions
correctly.
(i) Is your design self-starting, or is it possible for the state registers to hold an invalid
state? If the latter, how would have to modify your design to ensure predictable
operation?
(j) Devise an alternate design using D flip-flops and basic gates that doesn’t require going
through the process of state diagrams, transition tables, encoding, etc.
