Metal Oxide Semiconductor

Capacitor
Şenol Mutlu
Invention of the Field-Effect
Transistor. The first patent for
the field-effect transistor
principle was filed in Canada
by Austrian-Hungarian
physicist Julius Edgar
Lilienfeld on October 22,
1925. In 1934 German
physicist Dr. Oskar Heil
patented another field-effect
transistor. A working MOSFET
was not demonstrated until
1955. It started to dominate
integrated circuits after 1970s.

Semiconductors and Electronic Devices 1

 Outline
• MOS Capacitor Structure
• MOS Capacitor Band Diagram
• Voltage Drops in the MOS System
• Biasing Conditions
• Threshold Voltage
• MOS capacitance
• Capacitance Voltage Graphs
• Oxide Charges
• Interface Traps

Semiconductors and Electronic Devices 2

 MOS Capacitor Structure
• Typical MOS capacitors and
transistors in ICs today employ
MOS capacitor – heavily doped polycrystalline Si
(cross-sectional view) (“poly-Si”) film as the gate-
electrode material
• n+-type, for “n-channel” transistors
(NMOS)
GATE • p+-type, for “p-channel” transistors
xo (PMOS)

VG + – SiO2 as the gate dielectric

_
• band gap = 9 eV,
Si • χ = 0.95 eV, electron affinity
• εr,SiO2 = 3.9
– Si as the semiconductor material
• p-type, for “n-channel” transistors
(NMOS)
• n-type, for “p-channel” transistors
EE130, UC Berkeley (PMOS)
Semiconductors and Electronic Devices 3
 Definitions
• EO= Vacuum Energy Level. The minimum energy an electron must
have to free itself from the material.
• ΦM = “Work function” of the metal. Energy difference from the fermi
energy (average energy) of an electron in the metal to the vacuum
energy level.
• χ = Electron Affinity of the semiconductor. This is the energy
difference from the conduction band minimum in the semiconductor
to the vacuum energy level. Note that this energy does NOT depend
on doping.
• ΦS = “Work function” of the semiconductor. Energy difference from
the fermi energy of an electron in the semiconductor to the vacuum
energy level. Note that this energy depends on doping since EF
depends on doping.
• Metal is an equipotential region.
• The semiconductor is thick enough to have a quasi-neutral region
(where electric field is zero and all energy bands are flat).

Semiconductors and Electronic Devices 4

 Special Case: Equal Work Functions FM = FS

• The insulator is simply a very wide bandgap, intrinsically doped semiconductor

characterized by an electron affinity, χ𝑖 .
• Since the insulator prevents any current from flowing, when we bring the materials
together, the fermi-energy must be flat.
• Likewise, if no charges are stored on the “plates” (metal and semiconductor
regions near the insulator) of the capacitor, the bands are not bent in the insulator
nor semiconductor. Note the assumption of an equipotential surface in the metal
simply states that a perfect conductor can not support an electric field
(electrostatics).

Semiconductors and Electronic Devices 5

 General Case: Different Work Functions
E0
E0 E0

E0

The semiconductor can

(EC - EF)FB = q(ΦS – χ) in the quasi-neutral have an electric field near
region where the bands are not bent or are the insulator that forces
in “flat band” the energy bands to bend
near the insulator-
semiconductor interface.

Semiconductors and Electronic Devices 6

 Guidelines for Drawing MOS Band
Diagrams
• Fermi level EF is flat (constant with distance x) in the Si
– Since no current flows in the x direction, we can assume that
equilibrium conditions prevail
• Oxide is a perfect insulator with zero current flow. Band
bending is linear in the oxide.
d𝚬
– No charge in the oxide => 𝑑𝑥 = 0 so 𝚬 is constant
𝚬=
1 d𝐸𝐶
=> dEc/dx is constant 𝑞 𝑑𝑥

• Neither oxide nor oxide-semiconductor interface have

charge centers. From Gauss’ Law, we know that the
electric field strength in the Si at the surface, 𝚬Si , is related
to the electric field strength in the oxide, 𝚬oxi :
ε𝑆𝑖 𝑑𝐸𝑐 𝑑𝐸𝑐
𝚬𝑜𝑥 = 𝚬 ≅ 3𝚬𝑠𝑖 𝑠𝑜 ቤ =3× ቤ
ε𝑜𝑥 𝑠𝑖 𝑑𝑥 𝑜𝑥𝑖𝑑𝑒 𝑑𝑥 𝑆𝑖 (𝑎𝑡 𝑡ℎ𝑒 𝑠𝑢𝑟𝑓𝑎𝑐𝑒)
Semiconductors and Electronic Devices 7
 MOS Band-Diagram Guidelines (cont.)

• The barrier height for conduction-band electron flow

from the Si into SiO2 is 3.1 eV
– This is equal to the electron-affinity difference (cSi and cSiO2)
• The barrier height for valence-band hole flow from the Si
into SiO2 is 4.8 eV
• The vertical distance between the Fermi level in the
metal, EFM, and the Fermi level in the Si, EFS, is equal to
the applied gate voltage:
qVG = E FS − E FM
If the semiconductor is grounded:
• metal side Fermi level moves downward if VG > 0
• metal side Fermi level moves upward if VG < 0
Semiconductors and Electronic Devices 8
 MOS Equilibrium Energy-Band Diagram
metal oxide semiconductor
ℰ𝑜𝑥
EC

W, depletion region
n+ poly-Si 3.1 eV
VG SiO EC
2
+ EG
_ qfF E
Ei
EC=EFM FS
EV
p-type Si
EV
VG = 0

4.8 eV

EV
Semiconductors and Electronic Devices 9
 Flat-Band Condition
EC

EC=EFM
n+ poly-Si EC
VG SiO 𝑞 𝑉𝐹𝐵 0.56 eV
2 qfF EEi
FS
+ EV EV
_
p-type Si
VG = VFB ≈ -(0.56 + ϕF) V

VFB : flatband voltage

EV

Semiconductors and Electronic Devices 10

 Bulk Semiconductor Potential, fF

𝑞 f𝐹 ≡ 𝐸𝑖 (𝑏𝑢𝑙𝑘) − 𝐸𝐹
• p-type Si:
Ec
𝑘𝑇
f𝐹 = ln( 𝑁𝐴 /𝑛𝑖 ) > 0 qfF
Ei
𝑞 EF
Ev

Ec
• n-type Si: EF
𝑘𝑇 |qfF|
f𝐹 = − ln( 𝑁𝐷 /𝑛𝑖 ) < 0 Ei
𝑞 Ev

Semiconductors and Electronic Devices 11

 Voltage Drops in the MOS System
• In general,
𝑉𝐺 = 𝑉𝐹𝐵 + 𝑉𝑜𝑥 + f𝑠
where
qVFB = qFMS = q(FM – FS)
Vox is the voltage dropped across the oxide
(Vox = total amount of band bending in the oxide)

fs is the voltage dropped in the silicon

(total amount of band bending in the silicon)
𝑞 f𝑆 = 𝐸𝑖 (𝑏𝑢𝑙𝑘) − 𝐸𝑖 (𝑠𝑢𝑟𝑓𝑎𝑐𝑒)
For example: When VG = VFB, Vox = fs = 0
i.e. there is no band bending

Semiconductors and Electronic Devices 12

 MOS Band Diagrams (n-type Si)
Decrease VG (toward more negative values)
-> move the gate energy-bands up, relative to the Si
decrease VG decrease VG

• Accumulation • Depletion • Inversion

– VG > VFB – VG < VFB – VG < VT
– Electrons – Electrons – Surface
accumulate at repelled becomes
surface from surface p-type

Semiconductors and Electronic Devices 13

 Biasing Conditions for p-type Si
increase VG increase VG

VG = VFB VG < VFB VT > VG > VFB VG > VT

Semiconductors and Electronic Devices 14

 Accumulation (n+ poly-Si gate, p-type Si)
M O S
VG < VFB
3.1 eV | qVox
|
Ec= EFM

GATE Ev
|qVG |
|qfS| is small,  0
- - - - - -
+ + + + + +

VG + Ec
_
p-type Si 4.8 eV EFS
Ev

𝑉𝐺 ≅ 𝑉𝐹𝐵 + 𝑉𝑜𝑥
Mobile carriers (holes) accumulate at Si surface

EE130, UC Berkeley
Semiconductors and Electronic Devices 15
 Accumulation Layer Charge Density

VG < VFB 𝑉𝑜𝑥 ≅ 𝑉𝐺 − 𝑉𝐹𝐵

From Gauss’ Law:

GATE
- - - - - -
Ε𝑜𝑥 = −𝑄𝑎𝑐𝑐 /ε𝑆𝑖𝑂2
xo
+ + + + + + 𝑉𝑜𝑥 = Ε𝑜𝑥 𝑥𝑜 = −𝑄𝑎𝑐𝑐 /𝐶𝑜𝑥
VG +
_ Qacc (C/cm2) where 𝐶𝑜𝑥 ≡ ε𝑆𝑖𝑂2 /𝑥𝑜
p-type Si F/cm2 (units: F/cm2)

⇒ 𝑄𝑎𝑐𝑐 = −𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝐹𝐵 ) > 0

C/cm2
Semiconductors and Electronic Devices 16
 Depletion (n+ poly-Si gate, p-type Si)
M O S
VT > VG > VFB
qVox
W
Ec
GATE EFS
+ + + + + +
3.1 eV qfS Ev
- - - - - - qVG
VG +
_ Ec= EFM
p-type Si
Ev 4.8 eV

Si surface is depleted of mobile carriers (holes)

=> Surface charge is due to ionized dopants
(acceptors) EE130, UC Berkeley
Semiconductors and Electronic Devices 17
 Depletion Width W (p-type Si)
• Depletion Approximation:
The surface of the Si is depleted of mobile carriers to a depth W.

• The charge density within the depletion region is

𝜌 ≅ −𝑞𝑁𝐴 (0 ≤ 𝑥 ≤ 𝑊)
𝑑Ε ρ 𝑞𝑁𝐴
• Poisson’s equation: = ≅− (0 ≤ 𝑥 ≤ 𝑊)
𝑑𝑥 ε𝑆𝑖 ε𝑆𝑖
• Integrate twice, to obtain fS:

𝑞𝑁𝐴 2 2𝜀𝑆𝑖 f𝑆 To find fs for a given VG,

f𝑆 = 𝑊 ⇒𝑊= we need to consider the
2𝜀𝑆𝑖 𝑞𝑁𝐴 voltage drops in the MOS
system…
Semiconductors and Electronic Devices 18
 Voltage Drops in Depletion (p-type Si)

From Gauss’ Law:

GATE Ε𝑜𝑥 = −𝑄𝑑𝑒𝑝 /ε𝑆𝑖𝑂2
+ + + + + +
- - - - - - 𝑉𝑜𝑥 = Ε𝑜𝑥 𝑥𝑜 = −𝑄𝑑𝑒𝑝 /𝐶𝑜𝑥
VG +
_
Qdep (C/cm2)
Qdep is the integrated
p-type Si charge density in the Si:
𝑄𝑑𝑒𝑝 = −𝑞𝑁𝐴 𝑊 = − 2𝑞𝑁𝐴 𝜀𝑆𝑖 f𝑆

2𝑞𝑁𝐴 𝜀𝑠𝑖 f𝑆
𝑉𝐺 = 𝑉𝐹𝐵 + f𝑆 + 𝑉𝑜𝑥 = 𝑉𝐹𝐵 + f𝑆 +
𝐶𝑜𝑥

Semiconductors and Electronic Devices 19

 Surface Potential in Depletion (p-type Si)

2𝑞𝑁𝐴 𝜀𝑠𝑖 f𝑆
𝑉𝐺 = 𝑉𝐹𝐵 + f𝑆 +
𝐶𝑜𝑥

• Solving for fS, we have

𝑞𝑁𝐴 𝜀𝑠𝑖 2𝐶𝑜𝑥 2 (𝑉𝐺 − 𝑉𝐹𝐵 )

f𝑆 = 1+ −1
2𝐶𝑜𝑥 𝑞𝑁𝐴 𝜀𝑠𝑖

2
𝑞𝑁𝐴 𝜀𝑠𝑖 2𝐶𝑜𝑥 2 (𝑉𝐺 − 𝑉𝐹𝐵 )
f𝑆 = 1+ −1
2𝐶𝑜𝑥 2 𝑞𝑁𝐴 𝜀𝑠𝑖

Semiconductors and Electronic Devices 20

 Threshold Condition (VG = VT)

• When VG is increased to the point where fs reaches

2fF, the surface is said to be strongly inverted.
(The surface is n-type to the same degree as the bulk is p-type.)
This is the threshold condition.
VG = VT

⇒ f𝑆 = 2f𝐹
𝐸𝑖 (𝑏𝑢𝑙𝑘) − 𝐸𝑖 (𝑠𝑢𝑟𝑓𝑎𝑐𝑒) = 2 𝐸𝑖 (𝑏𝑢𝑙𝑘) − 𝐸𝐹
𝐸𝑖 (𝑠𝑢𝑟𝑓𝑎𝑐𝑒) − 𝐸𝐹 = − 𝐸𝑖 (𝑏𝑢𝑙𝑘) − 𝐸𝐹
⇒ 𝑛𝑠𝑢𝑟𝑓𝑎𝑐𝑒 = 𝑁𝐴

Semiconductors and Electronic Devices 21

 MOS Band Diagram at Threshold (p-type Si)
M O S
𝑘𝑇 𝑁𝐴
f𝑆 = 2f𝐹 = 2 ln
𝑞 𝑛𝑖 qVox WT
qfF
Ec

qfF EFS
2𝜀𝑆𝑖 (2f𝐹 ) qfs Ev
qVG
𝑊 = 𝑊𝑇 =
𝑞𝑁𝐴 Ec= EFM
Ev

EE130, UC Berkeley
Semiconductors and Electronic Devices 22
 Threshold Voltage

• For p-type Si:

2𝑞𝑁𝐴 𝜀𝑠𝑖 f𝑆
𝑉𝐺 = 𝑉𝐹𝐵 + f𝑆 + 𝑉𝑜𝑥 = 𝑉𝐹𝐵 + f𝑆 +
𝐶𝑜𝑥
2𝑞𝑁𝐴 𝜀𝑆𝑖 (2f𝐹 )
𝑉𝑇 = 𝑉𝐹𝐵 + 2f𝐹 +
𝐶𝑜𝑥

• For n-type Si:

2𝑞𝑁𝐷 𝜀𝑆𝑖 2f𝐹
𝑉𝑇 = 𝑉𝐹𝐵 + 2f𝐹 −
𝐶𝑜𝑥

Semiconductors and Electronic Devices 23

 Threshold Voltage
n+ poly-si gate NMOS

p+ poly-si gate PMOS

EE130, UC Berkeley
f𝑭 < 𝟎 𝒇𝒐𝒓 𝒏 − 𝒕𝒚𝒑𝒆 𝑺𝒊
Semiconductors and Electronic Devices 24
 Strong Inversion (p-type Si)
As VG is increased above VT, the negative charge in the Si is increased
by adding mobile electrons (rather than by depleting the Si more deeply),
so the depletion width remains ~constant at W= WT

WT r(x)
GATE M O S
+ + + + + +
- - - - - -

VG + x
_
p-type Si

f𝑆 ≅ 2f𝐹
Significant density of mobile electrons at
surface 2𝜀𝑠𝑖 (2f𝐹 )
(surface is n-type)
𝑊 ≅ 𝑊T =
𝑞𝑁𝐴
Semiconductors and Electronic Devices 25
 Inversion Layer Charge Density (p-type Si)

𝑉𝐺 = 𝑉𝐹𝐵 + f𝑆 + 𝑉𝑜𝑥
(𝑄𝑑𝑒𝑝 + 𝑄𝑖𝑛𝑣 )
= 𝑉𝐹𝐵 + 2f𝐹 −
𝐶𝑜𝑥
2𝑞𝑁𝐴 𝜀𝑠 (2f𝐹 ) 𝑄𝑖𝑛𝑣
= 𝑉𝐹𝐵 + 2f𝐹 + −
𝐶𝑜𝑥 𝐶𝑜𝑥
𝑄𝑖𝑛𝑣
= 𝑉𝑇 −
𝐶𝑜𝑥

∴ 𝑄𝑖𝑛𝑣 = −𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑇 )

Semiconductors and Electronic Devices 26

 fS and W vs. VG (p-type Si)

2fF
f S: 𝑞𝑁𝐴 𝜀𝑠𝑖 2
2𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝐹𝐵 )
2

f𝑠 = 1+ −1 (for 𝑉𝐹𝐵 < 𝑉𝐺 < 𝑉𝑇 )

2𝐶𝑜𝑥 2 𝑞𝑁𝐴 𝜀𝑠𝑖
0 VG
accumulation depletion inversion
VFB VT

2εSi (2fF )
WT =
qNA
W: 2𝜀𝑆𝑖 f𝑆 𝜀𝑆𝑖 2𝐶𝑜𝑥 2 (𝑉𝐺 − 𝑉𝐹𝐵 )
𝑊= = 1+ −1 (for 𝑉𝐹𝐵 < 𝑉𝐺 < 𝑉𝑇 )
𝑞𝑁𝐴 𝐶𝑜𝑥 𝑞𝑁𝐴 𝜀𝑠𝑖

0 VG
accumulation depletion inversion
VFB VT
EE130, UC Berkeley
Semiconductors and Electronic Devices 27
 Total Charge Density in Si, Qs
Q acc = −𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝐹𝐵 )

depletion inversion
0
accumulation
VG 𝑄𝑠 = 𝑄𝑎𝑐𝑐 + 𝑄𝑑𝑒𝑝 + 𝑄𝑖𝑛𝑣
VFB VT

accumulation depletion inversion

0 VG accumulation depletion inversion

VFB VT

Q dep = −𝑞𝑁𝐴 𝑊 VG
0 VFB VT
accumulation depletion inversion
0 VG
Qinv
VFB VT
slope = -Cox

Q inv = −𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑇 )

EE130, UC Berkeley
Semiconductors and Electronic Devices 28
 MOS Capacitance Measurement
• VG is scanned slowly
• Capacitive current due
to vac is measured
iac
GATE
𝑑𝑣𝑎𝑐
𝑖𝑎𝑐 =𝐶
𝑑𝑡
vac
𝑑𝑄𝐺𝐴𝑇𝐸 𝑑𝑄𝑠
Si 𝐶= =
𝑑𝑉𝐺 𝑑𝑉𝐺

C-V Meter MOS Capacitor

Semiconductors and Electronic Devices 29

 MOS C-V Characteristics (p-type Si)
accumulation depletion inversion

VG
𝑑𝑄𝑠
𝐶=
VFB VT 𝑑𝑉𝐺
Qinv C
slope = -Cox
Cox

Ideal C-V curve:

VG
VFB VT
accumulation depletion inversion

Semiconductors and Electronic Devices 30

 Capacitance in Accumulation (p-type Si)

• As the gate voltage is varied, incremental charge is

added/subtracted to/from the gate and substrate.
• The incremental charges are separated by the gate oxide.
M O S
+DQ

+Q
𝑑𝑄𝑎𝑐𝑐
𝐶= = 𝐶𝑜𝑥
-Q 𝑑𝑉𝐺
−DQ

Cox

Semiconductors and Electronic Devices 31

 Flat-Band Capacitance
• At the flat-band condition, variations in VG give rise to
the addition/subtraction of incremental charge in the
substrate, at a depth LD

• LD is the “extrinsic Debye Length”

– characteristic shielding distance, or the distance where the
electric field emanating from a perturbing charge falls off by
a factor of 1/e
𝜀𝑆𝑖 𝑘𝑇
𝐿𝐷 ≡
𝑞2 𝑁𝐴
1 1 𝐿𝐷
= +
𝐶𝐹𝐵 𝐶𝑜𝑥 𝜀𝑆𝑖
Cox CDebye

Semiconductors and Electronic Devices 32

 Capacitance in Depletion (p-type Si)

• As the gate voltage is varied, the width of the depletion

region varies.
→ Incremental charge is effectively added/subtracted at a
depth W in the substrate.
M O S
+DQ 𝑑𝑄𝑑𝑒𝑝 1 2(𝑉𝐺 − 𝑉𝐹𝐵 )
𝐶= = 2+
+Q W 𝑑𝑉𝐺 𝐶𝑜𝑥 𝑞𝑁𝐴 𝜀𝑆𝑖
−DQ
-Q
1 1 1 1 𝑊
= + = +
𝐶 𝐶𝑜𝑥 𝐶𝑑𝑒𝑝 𝐶𝑜𝑥 𝜀𝑆𝑖
Cox Cdep

Semiconductors and Electronic Devices 33

 Capacitance in Inversion (p-type Si)
CASE 1: Inversion-layer charge can be supplied/removed
quickly enough to respond to changes in the gate voltage.
→ Incremental charge is effectively added/subtracted at the
surface of the substrate.
+DQ
Time required to build
M O S inversion-layer
WT charge = 2NAto/ni , where
to = minority-carrier lifetime at
surface
−DQ
𝑑𝑄𝑖𝑛𝑣
𝐶= = 𝐶𝑜𝑥
𝑑𝑉𝐺
Cox

Semiconductors and Electronic Devices 34

 Capacitance in Inversion (p-type Si)

CASE 2: Inversion-layer charge cannot be supplied/removed

quickly enough to respond to changes in the gate voltage.
→ Incremental charge is effectively added/subtracted at a
depth WT in the substrate.
+DQ 1 1 1
= +
M O S C Cox Cdep
WT
1 WT
−DQ = +
Cox  Si
1 2(2fF ) 1
= + 
Cox Cdep= 𝜀𝑠𝑖 Cox qN A Si C min
𝑊𝑇

Semiconductors and Electronic Devices 35

 Supply of Substrate Charge (p-type Si)
gate gate
Accumulation: Cox Depletion: Cox

+ + + + + + Cdep W

p-type Si p-type Si

Case 1 Case 2
Inversion: gate gate

Cox Cox
N+ - - - - - - DC - - - - - -
Cdep,min
-
AC
DC and AC WT WT

p-type Si p-type Si

Semiconductors and Electronic Devices 36

 Capacitor vs. Transistor C-V
(or LF vs. HF C-V)
p-type Si:
C MOS transistor at any f,
MOS capacitor at low f, or
Cmax=Cox quasi-static C-V
CFB

MOS capacitor at high f

Cmin
VG
accumulation depletion inversion
VFB VT

Semiconductors and Electronic Devices 37

 Quasi-Static C-V Measurement

p-type Si: C
Cmax=Cox
CFB

Cmin
VG
accumulation depletion inversion
VFB VT
The quasi-static C-V characteristic is obtained by slowly ramping the
gate voltage (< 0.1 V/s), while measuring the gate current IG with a
very sensitive DC ammeter. C is calculated from IG = C·(dVG/dt)

Semiconductors and Electronic Devices 38

 Deep Depletion

• If VG is scanned quickly, Qinv cannot respond to the

change in VG. The increase in substrate charge
density Qs must then come from an increase in
depletion charge density Qdep
 depletion depth W increases as VG increases
 C decreases as VG increases
C
Cox

Cmin
VG
VFB VT

Semiconductors and Electronic Devices 39

 Example: Effect of Doping
C/Cox
1

VG
VFB VT

• How would C-V characteristic change if substrate

doping NA were increased?
– VFB VFB = (FM – FS)/q decreases since FS increases
– VT increases
– Cmin increases because Cdep increases because WT increases

Semiconductors and Electronic Devices 40

 Example: Effect of Oxide Thickness
C/Cox
1

VG
VFB VT

• How would C-V characteristic change if oxide

thickness xo were decreased?
– VFB : does not change
– VT : decreases
– Cmin : decreases

Semiconductors and Electronic Devices 41

 Oxide Charges

In real MOS devices, there is • In the oxide:

always some charge in the oxide – Trapped charge Qot
and at the Si/oxide interface. • High-energy electrons
and/or holes injected into
oxide
– Mobile charge QM
• Alkali-metal ions, which
have sufficient mobility to
drift in oxide under an
applied electric field

• At the interface:
– Fixed charge QF
• Excess Si (?)
– Trapped charge QIT
• Dangling bonds

Semiconductors and Electronic Devices 42

 Effect of Oxide Charges

• In general, charges in the oxide cause a shift

in the gate voltage required to reach the
threshold condition: 𝑥
𝑜
1
Δ𝑉𝑇 = − න 𝑥𝜌𝑜𝑥 (𝑥)𝑑𝑥
𝜀𝑆𝑖𝑂2
0
(x defined to be 0 at metal-oxide interface)
• In addition, they may alter the field-effect
mobility of mobile carriers (in a MOSFET)
due to Coulombic scattering

Semiconductors and Electronic Devices 43

 Fixed Oxide Charge QF

M O S
qQF / Cox
3.1 eV

Ec= EFM
|qVFB | QF
VFB = f MS
Ev Ec
EFS
−
Ev
Cox
4.8 eV

Semiconductors and Electronic Devices 44

 Parameter Extraction from C-V

From a single C-V measurement, we can extract much

information about the MOS device.
• Suppose we know that the gate-electrode material is
heavily doped n-type poly-Si (FM=4.05eV), and that the
gate dielectric is SiO2 (r=3.9):
– From Cmax = Cox we determine the oxide thickness xo
– From Cmin and Cox we determine substrate doping (by iteration)
– From substrate doping and Cox we calculate the flat-band
capacitance CFB
– From the C-V curve, we can find VFB = VG C =C
FB

– From FM, FS, Cox, and VFB we can determine Qf

Semiconductors and Electronic Devices 45

 Determination of FM and QF
Measure C-V characteristics of capacitors with different
oxide thicknesses. Plot VFB as a function of xo:
VFB
10nm 20nm 30nm
0
xo

𝑥𝑜
–0.15V
𝑉𝐹𝐵 = f𝑀𝑆 − 𝑄𝐹
𝜀𝑆𝑖𝑂2


–0.3V 

EE130, UC Berkeley
Semiconductors and Electronic Devices 46
 Mobile Ions
• Odd shifts in C-V characteristics were once a mystery:

QM
DVFB =−
Cox

• Source of problem: Mobile charge moving to/away from

interface, changing charge centroid

Semiconductors and Electronic Devices 47

 Interface Traps

Traps cause “sloppy” C-V and

also greatly degrade mobility in
channel 𝑄 (f ) 𝐼𝑇 𝑆
Δ𝑉𝐺 = −
𝐶𝑜𝑥
Semiconductors and Electronic Devices 48