EC8311

TAGORE INSTITUTE OF ENGINEERING AND
TECHNOLOGY
Deviyakurichi-636112, Attur (TK), Salem (DT). Website: www.tagoreiet.ac.in
(Approved by AICTE, New Delhi and Affiliated to Anna University, Chennai)
Accredited by NAAC
Department of Electrical and Electronics Engineering

II Year- III Semester - Electrical and Electronics Engineering
EC8311 – ELECTRONICS LABORATORY
LAB MANUAL
Academic Year 2020-2021
(2017 Regulation)
DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING
III SEM
EC8311 – ELECTRONICS LABORATORY
S.NO NAME OF EXPERIMENTS
1. Characteristics of semiconductor diode and zener diode.
Characteristics of a NPN Transistor under common emitter , common collector

2. and common base configurations.
Characteristics of JFET(Draw the equivalent circuit)

3.
Characteristics of UJT and generation of saw tooth waveforms.

4.
Design and Frequency response characteristics of a Common Emitter
5. Amplifier.
Characteristics of photo diode & photo transistor, Study of light activated relay
6. Circuit.
Design and testing of RC phase shift, LC oscillators.

7.
Single Phase half-wave and full wave rectifiers with inductive and capacitive
8. Filters.
Differential amplifiers using FET.

9.
10. Frequency and phase measurement using CRO
11. Astable and Monostablemultivibrators
Realization of passive filters

12.
Page 2 of 104
EXP.NO:1A CHARACTERISTICS OF SEMICONDUCTOR DIODE
DATE:
AIM
i) To plot the forward and reverse V-I characteristics of given PN - junctiondiode.

ii) To find the dynamic forward resistance offered by the PN-diode.
APPARATUS REQUIRED
Sl. No Components / Equipments Specifications Quantity

1 Diode- PN IN4007 1
2 Resistors 1kΩ 1
3 Dual Regulated Power Supply (0-30)V 1
4 Voltmeters MC (0-1)V, (0-15)V Each One
MC (0-500)µA, (0-20)
5 Ammeters Each One
mA
6 Bread Board 1
7 Connecting Wires Few
THEORY
The V-I characteristics is a graph drawn between the voltage applied across the terminals of a device and the
current that flows through it. The characteristics of PN junction diode for Forward Bias and Reverse Bias are
determined.
FORWARD BIAS
In forward bias, the positive of the battery is connected with P side (anode) of the diode and the negative of the
battery is connected with the N side (cathode) of the diode. When a diode is connected in the forward bias, the
electrons of the N material and holes of the P Material are repelled by the negative and positive of the battery
respectively towards the junction. Some of the electrons and holes enter the depletion region and they
recombine with each other. This reduces the width as well as height of the potential barriers. As a result of
this, more majority carriers diffuse across the junction. Therefore it causes a large current to flow through the
PN junction. The forward voltage at which the diode starts to conduct the current through it is called knee
voltage or threshold voltage. Normally the knee voltage for silicon diode is 0.7V and for germanium diode it is
0.3V. So the diode conducts the signal only in forward bias. In other words, the diode is ON in forward bias.
Page 3 of 104
REVERSE BIAS
The negative of the battery is connected with P side of the diode and the positive of the battery is connected
with the N side of the diode is called reverse bias. When a diode is connected in reverse bias, the electrons of
the N material and the holes of the P materials are attracted by the positive of the battery and the negative of
the battery respectively. With increase in reverse voltage, the width of depletion region and the height of the
potential barrier is increased. Therefore there is no current flow through the junction. Beyond a reverse voltage
the diode starts to conduct the current rapidly. That voltage is called breakdown voltage. The diode won’t
conduct the signal in its reverse bias. In other words the diode is OFF in reverse bias.
PROCEDURE
PN-JUNCTION DIODE FORWARD BIAS
1. The connections are given as per the circuit diagram.

2. The supply voltage from RPS is increased in steps. The voltmeter readings and the
corresponding current are noted from Ammeter and tabulated.
3. The graph between forward voltage VF and forward current IF is plotted.
4. From the graph the Forward dynamic Resistance Rf is calculated using the formula.
FORMULA
Rf = ∆Vf/ ∆If
Where
Rf = forward diode resistance
∆Vf= change in voltage
∆If = change in current
PN-JUNCTION DIODE REVERSE BIAS

2. The supply voltage from RPS is varied in steps. Voltmeter and ammeter readings are noted. The
graph between reverse voltage Vr and reverse current Ir is drawn.
3. In reverse bias, only a very small current flows through the diode.
Page 4 of 104
CIRCUIT DIAGAM - PN JUNCTION DIODE
FORWARD BIAS
REVERSE BIAS
SYMBOL
Page 5 of 104
TABULATION: FORWARD BIAS
S.No FORWARD VOLTAGE VF (V) FORWARD CURRENT IF (mA)
TABULATION: REVERSE BIAS
S.No REVERSE VOLTAGE IR (V) REVERSECURRENT IR (µA)
Page 6 of 104
MODEL GRAPH
V-I CHARACTERISTICS OF PN JUNCTION DIODE
Page 7 of 104
RESULT
Thus the characteristics of PN diode were drawn and the necessary parameters are
calculated from the graph.
Page 8 of 104
EXP.NO: 1B CHARACTERISTICS OF ZENER DIODE
DATE:
AIM
To plot the forward and reverse characteristics of given Zener diode and find the breakdown voltage.
APPARATUS REQUIRED

1 Diode- Zener FZ3.2 1
2 Resistors 1kΩ 1
5 Ammeters MC (0-20)mA 1
6 Bread Board 1
THEORY
A Zener diode is a properly doped crystal diode which has a sharp breakdown voltage. It is
always reverse biased. When the reverse bias on a crystal diode is increased, a critical voltage called
breakdown voltage is reached where the reverse current increases sharply to a high value. When the doping is
heavy, the reverse breakdown voltage is low. The electric field at barrier will be so strong that the electrons in
the covalent bonds break away from the bonds. This effect is called Zener effect.
Zener diode is available with breakdown voltages of 4.7v, 6.2v, 8.2v, 12v.
Breakdown occurs due to the avalanche multiplication between the thermally generated ions as a chain
of collisions is called Avalanche breakdown. The zener diode with breakdown voltages of < 6v operate
predominantly due to zener breakdown. Those with breakdown voltages > 6v operate predominantly due to
avalanche breakdown.
Page 9 of 104
PROCEDURE
ZENER DIODE FORWARD BIASED

2. The supply voltage from RPS is varied in steps. The corresponding voltmeter and ammeter reading are
noted down.
3. A graph between forward voltage VF and forward current IF is plotted.
4. From the graph the Forward Resistance is calculated using the formula,
∆Vf
Rf =
∆If
ZENER DIODE REVERSE BIASED

2. The supply voltage from RPS is varied in steps and the corresponding voltmeter and ammeter
readings are noted.
3. A graph between reverse voltages VR and reverse current IR is plotted.
4. From the graph the breakdown voltage and the dynamic resistance
∆𝑉𝑟
𝑅𝑟 = are found.
∆𝐼𝑟
Page 10 of 104
TABULATION FOR FORWARD BIAS
FORWARD VOLTAGE FORWARD CURRENT
S.NO
VF (v) IF (mA)
TABULATION FOR REVERSE BIAS

REVERSE VOLTAGE VR REVERSECURRENT IR
S.NO
(V) (A)
MODEL GRAPH:
Page 11 of 104
CIRCUIT DIAGRAM - ZENER DIODE
FORWARD BIAS
2.2KΩ D (0-10)mA
+ -
A
+
MC
RPS + -
- (0-30)V V
(0-1)V
MC
REVERSE BIAS
2.2KΩ D (0-1)mA
+ -
A
+
RPS - MC
+
(0-30)V v
_
(0-1)V
MC
SYMBOL
Page 12 of 104
RESULT
Thus the characteristics of ZENER diode were drawn for both forward and reverse bias.
The Breakdown voltage was found to be_______________
Page 13 of 104
EXP.NO: 2A CHARACTERISTICS OF BJT IN CE CONFIGURATION
DATE:
AIM
To plot the input and output characteristics of BJT in CE configuration.
APPARATUS REQUIRED
Transistor BC107 Max Rating : 50V 1A, 1

1
3W
2 Resistors 1kΩ, (or) 470Ω 2
Ammeters MC (0-25)mA, Each One

5
(0-100)µA
6 Bread Board 1
THEORY
A transistor consists of two PN junctions. They are formed by sandwiching P type or N type
semiconductor layer with a pair of PN junction. It has three layers called Emitter, Base and Collector labeled as
E,B,C respectively. There are two types of transistors called NPN and PNP. When transistor is connected in a
circuit one terminal is considered to be common both for input and output. According to the common terminal
the transistor is configured as Common emitter, Common Base or Common Collector. The configuration in
which emitter is common to the input and output is known as common emitter configuration. For all the
configurations the curves of input parameters and output parameters are drawn.
Input Characteristics gives the relation between input current and input voltage at constant output
voltage. In CE configuration the curve is drawn between base current and base emitter voltage at constant
collector emitter voltage.When V BE increases IB increases. When VCE increases the width of base region
decreases and increases the base current. The phenomenon is known as Early effect. The relation between
Collector current and collector-emitter voltage at constant base current is called output characteristics. The
output characteristics are divided as (i) active region, (ii) cutoff region and (iii) saturation region. When I b= 0,
the collector current is nearly zero. It is known as cutoff region. It is obtained when both the PN junctions are
reverse biased. The saturation region characteristic is obtained when both the junctions are forward biased.
Page 14 of 104
The collector current in saturation region is dependent on base current. At a constant Ib, collector
current increases with VCE up to a certain point and then becomes constant. Now the transistor enters the active
region. In the active region base emitter junction is forward biased and base collector junction is reverse biased.
In the active region collector current depends on I b only. It is independent of collector emitter voltage.
PROCEDURE

INPUT CHARACTERISTICS
1. VCE voltage is kept at a fixed value. VBE increased gradually and the corresponding IB are noted down
and tabulated.
2. The above Procedure is repeated for various VCE values.
3. The graphs VBEvsIb for constant VCE are drawn.
OUTPUT CHARACTERISTICS
1. For output characteristics IB is kept at a fixed value. VCE increased gradually and the corresponding I C are
noted down and tabulated.
2. Procedure is repeated for various VCE values.
3. The Graphs VCEVs IC for constant Ib are drawn.
Page 15 of 104
TABULATION FOR INPUT
CHARACTERISTICS OF BJT
S.NO VcE = 1 V VcE = 2 V

VBE IB (A) VBE IB (A)
(V) (V)
TABULATION FOR OUTPUT CHARACTERISTICS

OF BJT
IB = 20 (A) IB = 30 (A)
S.NO VCE
IC (A) VCE (V) IC (A)
(V)
Page 16 of 104
CIRCUIT DIAGRAM – CE CONFIGURATION
SYMBOL CONSTRUCTION
COLLECTOR
RRR
E N P N
C
BASE
B
C
EMITTER P N P
E
B
PIN DIAGRAM OF BC107
Page 17 of 104
RESULT
Thus the CE transistor input and output characteristics were plotted.
Page 18 of 104
EXP.NO: 2B CHARACTERISTICS OF BJT IN CB CONFIGURATION
DATE:
AIM
To plot the input and output characteristics of BJT in CB configuration.
APPARATUS REQUIRED

1 Transistor BC107 Max Rating : 50V 1A, 3W 1
5 Ammeters MC (0-25)mA 2
6 Bread Board 1
THEORY
The configuration in which base is common to the input and output is known as common base
configuration
Input Characteristics gives the relation between input current (I E) and input voltage (VBE) at constant
output voltage (VCB). When IB increases VBE increase.When VCB increases value of IE decrease for a particular
VBE.Output characteristics give the relation between Collector current and collector base voltage at constant
emitter current. The output characteristics are divided as active region, cutoff region and saturation region. The
characteristic obtained when the collector current is nearly zero and both the junctions are reverse biased is
known as cutoff region. It is obtained when both the PN junctions are reverse biased. The saturation region
characteristic is obtained when both the junctions are forward biased. The collector current in this region is
independent of base current. In the active region the collector current increases linearly with the increase in
collector emitter voltage.
Page 19 of 104
PROCEDURE

2. VCB voltage is kept at a fixed value. VBE increased gradually and the changes in IE are noted down and
tabulated.
3. Process is repeated for various VCB values
4. IE is kept at a fixed value. VCB increased gradually and the changes in IC are noted down and tabulated.
5. Process is repeated for various IE values.
6. Graphs are drawn.
Page 20 of 104
TABULATION FOR INPUT CHARACTERISTICS OF BJT
VcB = 4 V VcB = 8 V
S.NO VEB IE
VEB (V) IE (mA)
(V) (mA)
TABULATION FOR OUTPUT CHARACTERISTICS OF BJT
IE = 1 mA IE = 3 mA
S.NO VCB
VCB (V) IC (mA) IC (mA)
(V)
Page 21 of 104
CIRCUIT DIAGRAM – CB CONFIGURATION
SYMBOL
MODEL GRAPH
Page 22 of 104
RESULT
Thus the CB transistor input and output characteristics were plotted.
Page 23 of 104
EXP.NO: 2C CHARACTERISTICS OF BJT IN CC CONFIGURATION
DATE:
AIM:
To obtain the input and output characteristics of the given BJT in common collector configuration
APPARATUS REQUIRED:

1 Transistor BC107 Max Rating : 50V 1A, 3W 1
4 Voltmeters MC (0-10)V 2
5 Ammeters MC (0-100)µA, (0-25)mA Each One
6 Bread Board 1
THEORY:
A BJT is a three terminal two junction semiconductor device in which the conduction is due to
both the charge carrier. Hence it is a bipolar device and it amplifies the sine waveform. BJT is classified
into two types– NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is
sandwiched.
The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heavily doped with a moderate cross sectional area. The collector collects the
charge carries and hence it has moderate doping and large cross sectional area. The base region acts a path
for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the
base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with
the EB junction forward biased. In transistor, the current is same in both junctions, which indicates that
there is a transfer of resistance between the two junctions which is known as transfer resistance of
transistor
Page 24 of 104
CIRCUIT DIAGRAM:
MODEL GRAPH:
Page 25 of 104
PRECAUTIONS:
1. While doing the experiment do not exceed the ratings of the transistor. This may damage the
transistor.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as per the
circuit diagram.
4. Make sure while selecting the emitter, base and collector terminals of the transistor.
PROCEDURE:
Input characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set VCE, vary VBE in regular interval of steps and note down the corresponding IB
reading. Repeat the above procedure for different values of VCE.
3. Plot the graph: VBC vs. IB for a constant VCE.
Output characteristics:
2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC
reading. Repeat the above procedure for different values of IB.
3. Plot the graph: VCE vs. IC for a constant IB.
Page 26 of 104
OBSERVATION:
Input characteristics:
Output characteristics:
Page 27 of 104
RESULT:
The transistor characteristics of a Common Collector (CC) configuration were plotted.
Page 28 of 104
EXP.NO: 3 CHARACTERISTICS OF JFET
DATE:
AIM
i) To plot the drain and transfer characteristics of JFET.

ii) To determine the Drain resistance and Transconductance.
APPARATUS REQUIRED
FET BFW10 or 11 1
1
Idss> 8 mA, Vp<8V
Voltmeters MC (0-10)V, MC (0- Each One

3
20)V
4 Ammeters MC (0-50) mA 1
5 Bread Board 1
THEORY
Field effect transistor is one type of transistor having three terminals namely gate, source and drain. The
current conduction in this device is only due to majority carriers. In the normal operation of FET, gate-source
junction is always reverse biased. Drain characteristic is the curve between drain current and drain-source
voltage, at constant gate source voltage. The drain current increases linearly with drain-source voltage and
remains constant at its maximum value. When the voltage is further increased, it rapidly leads to the breakdown
of the device. This characteristic is used to find drain resistance of FET.
Transfer characteristics are the curves between drain current and gate-source voltage at constant drain-
source voltage. When gate source voltage is zero, the depletion regions are small and the drain current will be
maximum. When the gate-source voltage is increased, the depletion region increases and reduces the drain
current. This gate- source voltage is called pinch - off voltage. From this characteristic, we can find the
transconductance of FET.
DC DRAIN RESISTANCE
It is also called the static or ohmic resistance of the channel and is given by the ratio ofdrain-source voltage
to drain current.
Page 29 of 104
AC DRAIN RESISTANCE
It is also called dynamic drain resistance (or) the ac resistance between the drain and source terminals,
when the JFET is operating in the pinch – off voltage of saturation region. It is given by the ratio of small
change in drain to source voltage to the corresponding change in drain current for a constant gate to source
voltage
It is the resistance from drain to source terminals. It is also the output resistance of JFET. Its
reciprocal is the output admittance.
PROCEDURE
 The connections are given as per the circuit diagram.
Transfer Characteristics:
 The power supply is Switch ON and VDS is set at a constant value VGS is varied in steps of 0.5V.
 The ammeter and voltmeter readings are tabulated and the transfer characteristics are plotted.
DrainCharacteristics:
 For Drain characteristics VGS is set to a constant value VDS is varied in steps of 0.5V
Output Characteristics:
 The ammeter and voltmeter readings are tabulated and the drain characteristics are plotted.
 The drain resistance = Change in VDS / Change in I D at constant VGS
 Transconductance = Change in ID/ Change in VGS at constant VDS
Page 30 of 104
CIRCUIT DIAGRAM – JFET
SYMBOL PIN DIAGRAM
MODEL GRAPH
Page 31 of 104
TABULATION FOR DRAIN
CHARACTERISTICS OF JFET
VGS = -4V VGS = -6V

VGS = -2V
S.NO VDS ID VDS ID VDS
ID (mA)
(V) (mA) (V) (mA) (V)
TABULATION FOR TRANSFER

CHARACTERISTICS OF JFET
VDS = 10V
VDS = 5V
S.NO VGS VGS
ID (mA) ID (mA)
(V) (V)
Page 32 of 104
RESULT
Thus the drain and transfer characteristics of JFET are plotted.

Drain resistance: ____________
Transconductance: _____________________
Page 33 of 104
EXP.NO: 4 CHARACTERISTICS OF UJT
DATE:
AIM
i) To plot the Emitter characteristics of UJT.
ii) To determine the intrinsic standoff ratio.
APPARATUS REQUIRED

1 UJT 2N2646 1
2 Resistors 330 , 3.3k Each One
4 Voltmeters MC (0-10)V 1
5 Ammeters MC (0-25) mA 1
6 Bread Board 1
THEORY
The UJT consists of a bar of lightly doped N type silicon material with a block of P-type material on
one side. The end terminals B1& B2 of the bar are named as base1and base 2. The P type block is named as
emitter. The resistance of the n type silicon bar is represented as two resistors R1& R2 .The sum of these two
resistances is known as the base-to- base resistance of UJT (RBB). The P type emitter forms a PN junction with
the N type silicon bar. This junction can be considered as a diode in the equivalent circuit. The voltage applied
to the bases B1 and B2 of UJT is divided by voltage division rule between its terminals, B 1 and B2.
When the emitter terminal is grounded, the PN junction is reverse biased and a small emitter reverse
current flows. When the emitter voltage is increased from zero the PN junction becomes forward biased and
causes a forward current to flow from the P type emitter into N type silicon bar. Then the charge carriers are
injected into the B1region.The resistance of the semiconductor material is dependent on doping. So the
additional charge carriers cause the resistance of the region to decrease rapidly.
This decrease in resistance decreases the voltage drop and PN junction is more heavily forward biased.
This results in a greater emitter current and more charge carriers which further reduces the resistance of the
region. So the input voltage is pulled down and the emitter current is increased to a limit determined by the
source resistance. The device remains in on condition until the emitter input is open circuited.
Applications: UJT Relaxation oscillator, overvoltage detector.
Page 34 of 104
PROCEDURE
1. The Connections are given as per the circuit diagram.
2. The power supply is Switch ON. By varying the emitter voltage the corresponding
emitter base voltage and emitter current are noted down.
3. The graph for VBB Vs IE is plotted
4. The intrinsic standoff ratio is determined for different values of V BB
Intrinsic standoff ratio = VP/VBB (OR) RB1/(R B1+ RB2)
= VP – VD/ VBB
VP- Peak point voltage
VBB –Inter base voltage
VD – 0.7V
Page 35 of 104
CIRCUIT DIAGRAM – UNIJUNCTION TRANSISTOR
SYMBOL PIN DIAGRAM
Page 36 of 104
TABULATION
S.NO VBB = 5V VBB = 10V VBB =15V
VE (V) IE (mA) VE (V) IE (mA) VE (V) IE (mA)
MODEL GRAPH
Page 37 of 104
RESULT
Thus the Emitter characteristic of UJT was determined and plotted.
The intrinsic standoff ratio was found to be: _____________.
Page 38 of 104
EXP.NO: 5 DESIGN AND FREQUENCY RESPONSE OF A COMMON
EMITTER AMPLIFIER
DATE:
AIM
To design a common emitter amplifier circuit and to plot frequency response characteristic curve
APPARATUS REQUIRED

Max Rating : 50V 1A,
1 Transistor BC107 1
3W
56kΩ,12kΩ,2.2kΩ,
2 Resistors Each One
10kΩ,560Ω
3 Capacitor 0.1μF, 22μF 2,1
5 CRO (0-30 )MHz 1
6 Function Generator (0 – 1 )MHz 1
7 Bread Board 1
9 BNC CRO Probe 2
THEORY
Amplifier is an electronic circuit that is used to raise the strength of a weak signal. The
process of raising the strength of a weak signal is known as amplification. One importance
requirement during amplification is that only the magnitude of the signal should increase and there
should be no change in signal shape. The transistor is used for amplification. From the voltage
waveforms for the CE circuit shown below, it is seen that there is a 180o phase shift between the
input and output waveforms. This can be understood by considering the effect of a positive going
input signal. When VS increases in a positive direction, it increases the transistor VBE. The increase
in VBE raises the level of IC, thereby increasing the drop across Rc, and thus reducing the level of
the VC. The changing level of VC is capacitor-coupled to the circuit output to produce the ac output
voltage, VO. As VS increases in a positive direction, VO goes in a negative direction. Similarly,
When VS changes in a negative direction, the resultant decrease in VBE reduces the IC level,
thereby reducing VRC, and producing a positive goingoutput.
Page 39 of 104
CE amplifier circuit elements and their functions:
` Biasing circuit: The resistances R1, R2 and RE form the biasing and stabilization circuit. The biasing
circuit must establish a proper operating point, otherwise a part of the negative half-cycle of the signal may be
cut-off in the output.
Input capacitor, C1: An electrolyte capacitor C1 is used to couple the signal to the base of the transistor.
If it is not used, the signal source resistance, Rs will come across R2 and thus change the bias. C1 allows only
ac signal to flow but isolates the signal source fromR2.
Emitter bypass capacitor, CE: An emitter bypass capacitor, CE is used parallel with RE to provide
low reactance path to the amplified ac signal. If it is not used, then ac amplified ac signal following through
RE will cause a voltage drop across it, thereby reducing the output voltage.
Coupling capacitor, C2: The coupling capacitor, C2 couples one stage of amplification to the next
stage. If it is not used, the bias conditions of the next stage will be drastically changed due to the shunting
effect of RC. This is because RC will come in parallel with the upper resistance R1 of the biasing network of
the next stage, thereby altering the biasing conditions of the latter. In short, the coupling capacitor C2 isolates
the dc of one stage from the next stage, but allows the passage of ac signal.
The circuit has input impedance (Zi) and output impedance (ZO). These can cause voltage
division of the circuit input and output voltages.The circuit voltage amplification (AV), or voltage gain,
depends on the transistor parameters and on resistor RC andRL.
Page 40 of 104
CIRCUIT DIAGRAM: (CE amplifier circuit with design values of components)
Page 41 of 104
PROCEDURE
PRECAUTIONS:
1. While performing the experiment do not exceed the ratings of the transistor. This may lead to damage the
transistor.
2. Connect voltmeter and ammeter in correct polarities as shown in the circuitdiagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as per the
circuitdiagram.
4. Make sure while selecting the emitter, base and collector terminals of thetransistor.
PROCEDURE:
Frequency response curve measurements:
1. Connections are made as per the circuitdiagram.
2. In the above assembled circuit, keep the magnitude of the source same, ie. 100 mV and decrease the
frequency from 1 KHz and measure voltage gain of the amplifier at each frequency.
3. Now increase the frequency from 1 KHz to 1 MHz and measure the voltage gain of the amplifier at each
frequency.
4. Take at least 5 readings on either side of the 1 KHz frequency. Tabulate the reading in thetable.
5. Plot on a semi-log graph sheet the frequency response (voltage gain vs. frequency) curve using the
abovemeasurements.
6. From the plot, determine the values of (a) Mid band voltage gain,AV(mid),
(b) Lower cut-off frequency, (c) Upper cut-off frequency and (d) Bandwidth.
Page 42 of 104
OBSERVATION: Frequency response curve measurements
Set Input Voltage,VS= mV
Signal Frequency Output Voltage Voltage Gain, dB

(Hz) Vo Voltage Gain (Vo /
Fs (volts) Vs) 20 log10 (Vo / Vs)
MODEL GRAPH: Frequency response of CE amplifier
Page 43 of 104
RESULT:
Thus the CE amplifier is designed and frequency response curve is plotted.
Page 44 of 104
EXP.NO: 6A CHARACTERISTICS OF PHOTO DIODE.
DATE:
AIM
To plot the VI Characteristics of Photo diode.
APPARATUS REQUIRED

1 Photodiode - 1
2 Resistors 1kΩ 1
3 Regulated Power Supply (0-30)V 1
4 Ammeter (0-25)mA 1
5 Voltmeter (0-30) V 1
6 Incandescent Lamp - 1
7 Bread Board 1
THEORY:
Photo diode is connected in reverse biased condition. The depletion region width is large under
normal condition. It carries small reverse current. When light is incident through glass window on PN
junction, photons in the light bombards with the PN junction and some energy is imparted to the
valence electron. Due to this valence electrons are dislodged from the covalent bonds and become a free
electron. Thus total number of minority carriers’ increases thereby increasing the reverse current.
Page 45 of 104
CIRCUIT DIAGRAM:
Page 46 of 104
PROCEDURE
2. Switch ON the lamp and power supply.
3. Place the bulb in a certain distance and focus to the photodiode and phototransistor.
4. Vary the voltage of power supply step by step from zero volts.
5. Note its corresponding Voltmeter and Ammeter reading.
6. Draw the graph between voltage and current.
7. Switch OFF the lamp and power supply.
8. Disconnect the components.
Page 47 of 104
TABULATION (PHOTO DIODE)
D=10cm D=20cm
S.No.
V(Volts) I(mA) V(Volts) I(mA)
MODEL GRAPH OF PHOTO DIODE
Page 47 of 104
RESULT
Thus the VI characteristic of a Photo diode was plotted in the presence and absence of illumination
Page 48 of 104
EXP.NO: 6B CHARACTERISTICS OF PHOTO TRANSISTOR.
DATE:
AIM
To plot the VI Characteristics of Photo Transistor
APPARATUS REQUIRED:

1 Photo Transistor - 1
2 Resistors 1kΩ 1
4 Ammeter (0-25)mA 1
5 Voltmeter (0-10) V 1
7 Bread Board 1
THEORY:
Phototransistor helps us to achieve photo multiplication or photo current enhancement. In

phototransistor, pairs are generated on the base region by illumination and some majority carriers
diffuse into the emitter, resulting in an injection current which is large. The base load can even be left open
but still majority current will cause injection in this structure.
Page 49 of 104
PROCEDURE:
1. Switch on the power supply.

2. Photodiode is subjected to darkness and illumination and the following steps are followed each
time.
3. By varying the supply voltage in steps of 1V, note down the voltage(VCE) and corresponding
current (Ic)
4. Plot the graph between voltage and current.
Page 50 of 104
TABULATION:
MODEL GRAPH:
Page 51 of 104
RESULT:
Thus the VI characteristic of a Photo Transistor was plotted in the presence and absence of illumination
Page 52 of 104
EXP.NO: 6C STUDY OF LIGHT ACTIVATED RELAY CIRCUIT
DATE:
AIM:
To study the working principle of Light activated Relay circuit.
APPARATUS REQUIRED:

2 Photo diode - 1
3 PN Diode 1N4007 1
4 Resistors 100Ω 1
6 Decade Resistance Box - 1
7 Relay 12 V SPST 1
8 LED Red Color 1
10 Bread Board 1
THEORY:
A photo relay or light activated relay is a circuit which opens and closes the relay contacts according to the
light. Here a photo diode is used to sense the light. The photo diode offers a high resistance when there is
no light falling on it. Here the photo diode is connected in reverse biased condition. The only current flowing
through it will be due to the minority carriers. When light falls on it, the current due to the minority carriers
increase and the diode offers a low resistance. As a result the voltage across the diode will not be sufficient to
make the transistor Q1 forward biased and the relay will OFF. When there is darkness the photo diode
resistance increases and the voltage across it will become enough to forward bias the transistor Q1 making the
relay ON. The diode D2 is used as a freewheeling diode to protect the transistor from transients produced
to the switching of relay. By this way the load connected through the relay contacts can be switched ON and
OFF according to the light falling on the photo diode.
Page 53 of 104
CIRCUIT DIAGRAM:
Page 54 of 104
PROCEDURE:
1. Assemble the circuit on a Bread board.

2. The circuit can be powered from 12V DC.
3. The preset R1 can be used to adjust the sensitivity of the circuit.
4. The Diode D1 can be any general purpose photo diode.
Page 55 of 104
RESULT:
Thus the working of Light activated Relay circuit was studied.
Page 56 of 104
EXP.NO: 7A DESIGN AND TESTING OF RC PHASE SHIFT
OSCILLATOR.
DATE:
AIM
To design and construct a RC phase shift oscillator for the given frequency (f0).
APPARATUS REQUIRED

2 Resistors 1.2kΩ, 47kΩ, 10kΩ, 3, 1, 1
2.2kΩ, 620Ω 1, 1
3 Capacitor 0.01 µF, 10µF, 3, 1
15µF 47µF, 1, 1
4 CRO (0 – 30) MHz 1
5 Regulated Power Supply (0 – 30)V 1
6 Function Generator (0-1 )MHz 1
7 Decade Resistance Box - 1
8 Bread Board 1
THEORY:
In the RC phase shift oscillator the required phase shift of 180˚ in the feedback loop from the output to input is
obtained by using R and C components, instead of tank circuit. Here a common emitter amplifier is used in
forward path followed by three sections of RC phase network in the reverse path with the output of the last
section being returned to the input of theamplifier. The phase shift Ф is given by each RC section Ф=tanˉ1
(1/ωRC). In practice R- value is adjusted such that Ф becomes 60˚. If the value of R and C are chosen such that
the given frequency for the phase shift of each RC section is 60˚. Therefore at a specific frequency the total
phase shift from base to transistor’s around circuit and back to base is exactly 360˚ or 0˚. Thus the Barkhausen
criterion for oscillation issatisfied.
DESIGN:
Vcc=12v, Ic=1mA, β=100,RE = 560 Ω
Vce=Vcc/2=6V, Vre=0.1Vcc=1.2V
Vb=Vre+0.7=1.9V,
Page 57 of 104
R1=Vcc/10Ib –R2=12/ (10*20μA) –10K=47 KΩ
R2=Vb/10Ib = .9/(10*20μA)=9.5K Ω=10 K Ω
Rc=Vcc-Vce-(IeRe/Ic)=2.4K Ω =2.2KΩ
CIRCUIT DIAGRAM:
Page 58 of 104
PRECAUTIONS:
1. All the connections should becorrect.

2. Parallax error should be avoided while taking readings from analogmeters.
PROCEDURE:
1. Connect as per circuitdiagram.
2. Connect CRO output terminals and observe thewaveform.
3. Calculate practically the frequency of oscillations by using the expression f = 1 / T where ( T=
Time period of thewaveform)
4. Repeat the above steps 2, 3 for different values of L, and note down the practical values of
oscillations of the RC-phase shiftoscillator. Compare the values of oscillations both theoretically
andpractically.
Page 59 of 104
OBSERVATION:
Frequency (Hz)
f =1/2 πRC√ (6+4RC/R)
MODEL GRAPH:
Page 60 of 104
RESULT:
Thus a RC phase shift oscillator was designed and tested successfully
Page 61 of 104
EXP.NO: 7B DESIGN AND TESTING OF LC OSCILLATOR.
DATE:
AIM :
To design and construct a Hartley and Colpitts oscillator.
APPARATUS REQUIRED

2 Resistors 100kΩ, 2.7kΩ, 12kΩ, Each 1
800Ω
3 Capacitor 0.1μF, 0.2μF, 22μF 2, 2, 1
4 CRO (0-30 )MHz 2
5 Decade Inductance box - 1
6 Regulated Power Supply (0 – 30)V 1
7 Bread Board 1
THEORY
If gain A of the amplifier is just sufficient to overcome the attenuator β of the β - network. We get
sinusoidal oscillations. Mathematically If Aβ is for greater than 1 square wave results in however, if Aβ is less than
1 no oscillations will occur. The Colpitts and Hartley Oscillator is a LC oscillator. Generally, LC oscillators are
designed to operate in the radio – frequency range above 1MHz however, they can also be designed to produce
oscillations in the low audio – frequency range. But for low frequency operation, the size of the inductors to be
used become larger and larger as the frequency becomes smaller and smaller and this puts a limit on the low
frequency range of oscillators employing LC – coupling network.
DESIGN:
Frequency (Hz)
f =1/2 πRC√ (LCeq)
Where, Ceq = (C1C2)/(C1+C2)

Page 62 of 104
Let C1 = 0.2µF , C2 = 0.2µF and L = 10mH
Then , η= 5kHz
DESIGN:
Vcc =10V, IC =1.2mA, RB =15k Ω

VE = Vcc /10 =10V /10 =1V IE ≈ Ic =1.2mA
VE = IERE
RE = VE /IE =1V / 1.2mA RE = 833.33Ω
Choose, RE =800 Ω
Vcc = IcRC +VCE + VE
Rc = ( Vcc – VCE – VE) /Ic = (10 – 5 – 1) / 1.2mA Rc =3.3kΩ
Choose , Rc = 3.9kΩ
VBE = VB – VE
VB = VBE + VE = 0.7 +1 =1.7 V V B = (Vcc *R2)/ (R1+R2) =15kΩ
R2/(R1+R2) = 1.7 /10 = 0.17
R1 = 15kΩ / 0.17 = 88.24kΩ
Choose, R1 = 100kΩ
R2/(R1+R2) = 0.17 R2 =18kΩ
Choose, R2 =12kΩ
Let C1 =C2 = 0.1μF
PROCEDURE:

2. For the Colpitts oscillator adjust the capacitance in the tank circuit to get a sinusoidal signal of
desired frequency
3. Plot the output obtained in the linear graph.
Page 63 of 104
RESULT:
Thus Colpitts oscillator is designed and constructed, and the output sine wave form is observed and
compared with theoretical oscillation frequency.
Page 64 of 104
EXP.NO: 8A HALF WAVE RECTIFIER WITH INDUCTIVE
&CAPACITIVE FILTERS
DATE:
AIM
To determine the ripple factor, Efficiency of the Half – wave rectifier with inductive and capacitive filters.
Sl.
Description Range Quantity APPARATUS
No.
1 Diode IN4001 1 REQUIRED:
2 Capacitor 100μF 1
3 Resistor 1KΩ 1
4 Transformer (0-12)V 1
5 CRO ---- 1
6 Bread board ---- 1
7 Connecting Wire --- as
required
THEORY:
During positive half-cycle of the input voltage, the diode D1 is in forward bias and conducts through the load
resistor R1. Hence the current produces an output voltage across the load resistor R1, which has the same
shape as the positive half cycle of the input voltage.
During the negative half cycle of the input voltage, the diode is reverse biased and there is no current through
the circuit. i.e, the voltage across R1 is zero. The net result is that only the positive half cycle of the input
voltage appears across the load. The average value of the half wave rectified output voltage is the value
measured on DC voltmeter. For practical circuits, transformer coupling is usually provided for tworeasons.
1. The voltage can be stepped-up or stepped-down, asneeded.
2. The AC source is electrically isolated from the rectifier. Thus, preventing shock hazards in the
secondarycircuit.
Page 65 of 104
CIRCUIT DIAGRAM WITH OUT FILTER
HALF WAVE RECTIFIER WITH INDUCTIVE FILTER
Page 66 of 104
HALF WAVE RECTIFIER WITH CAPACITIVE FILTER
OBSERVATION:
Without Filter
USING Vac(v) Vdc(v) r= Vac/ Vdc

DMM
With Filter
USING Vac(v) Vdc(v) r= Vac/ Vdc

DMM
MODEL GRAPH:
Page 67 of 104
PRECAUTION:
PROCEDURE:
2. Connect the primary side of the transformer to ac mains and the secondary side to the
rectifierinput.
3. Using multimeter, measure the AC input voltage of the rectifier and DC voltage at the output
of therectifier.
4. Find the theoretical of dc voltage by using theformula,
Page 68 of 104
FORMULA
Average or Dc Value of Current
RMS Value Current & Voltage
Im
2
Vm
Vrms 
2
Ripple Factor =
Rectification Efficiency
REGULATION CHARACTERISTICS:
2. By increasing the value of the rheostat, the voltage across the load and current flowing
through the load aremeasured.
3. The reading istabulated
4. Draw a graph between load voltage (VL and load current ( IL) taking VL on X-axis and IL on y-
axis.
Page 69 of 104
5. From the value of no-load voltages, the percentage regulation can be calculated using the
formula.
Page 70 of 104
RESULT:
1. The Ripple factor for the Half-Wave Rectifier with and without filters wasmeasured.
2. The % regulation of the Half-Wave rectifier wascalculated.
EXP.NO: 8B FULLWAVE RECTIFIER WITH INDUCTIVE

&CAPACITIVE FILTERS
DATE:
AIM:
To construct a full wave rectifier using diode with capacitive filter and to draw its output waveform
APPARATUS REQUIRED:

1 Transformer 230V/(12-0-12) V 1
2 Diode 1N4007 2
1000µF,16V/
3 Capacitors 1
470µF,25V
Page 71 of 104
Decade Resistance Box/
4 - / 10kΩ 1
Resistor
5 Dual Trace CRO 20MHz 1
6 Multimeter - 1
7 Bread Board 1
THEORY:
The conversion of AC into DC is called Rectification. Electronic Devices can convert AC power into DC
power with high efficiency. The full-wave rectifier consists of a center-tap transformer, which results in
equal voltages above and below the center-tap. During the positive half cycle, a positive voltage appears
at the anode of D1 while a negative voltage appears at the anode of D2. Due to this diode D1 is forward
biased it results in a current ID1 through the load R.
During the negative half cycle, a positive voltage appears at the anode of D2 and hence it is forward
biased, resulting in a current ID2 through the load at the same instant a negative voltage appears at the
anode of D1 thus reverse biasing it and hence it doesn‟tconduct.
Ripple Factor:
Ripple factor is defined as the ratio of the effective value of AC components to the average DC value. It
is denoted by the symbol „r‟.
Rectification Factor:
The ratio of output DC power to input Ac power is defined as efficiency.
efficincy = (Vdc)2/ (Vac)2

η=81%(if R >>Rf, then Rf can be neglected)
Percentage of Regulation:
It is a measure of the variation of AC output voltage as a function of DC output voltage.
Percentage of regulation = {( VNL – VFL ) / VFL}* 100%
Page 72 of 104
where, VNL = Voltage across load resistance, when minimum current flows through it.
VFL= Voltage across load resistance, when maximum current flows through.
For an ideal Full-wave rectifier, the percentage regulation is 0 percent. The percentage of regulation
is very small for a practical full wave rectifier.
Peak Inverse Voltage (PIV):
It is the maximum voltage that has to be withstood by a diode when it is reverse biased.
PIV = 2Vm
CIRCUIT DIAGRAM FOR FULLWAVE RECTIFIER WITHOUT FILTER:
Page 73 of 104
CIRCUIT DIAGRAM FOR FULL WAVE RECTIFIER WITH FILTER:
MODEL GRAPH:
PRECAUTION:
Page 74 of 104
PROCEDURE:
1. Connect the circuit as shown in the circuitdiagram.

2. Connect the primary side of the transformer to AC mains and the secondary side to rectifierinput.
3. Using a CRO, measure the AC input voltage of the rectifier, AC and DC voltage at the output of the
rectifier.
4. Observe the waveforms at the secondary windings of transformer and across loadresistance.
Observation:
Sl. No. Input Voltage (V) Output Voltage (V)
Calculations:
1. Ripple Factor: R = Vac /Vdc
2. Efficiency: Ƞ = 1 /(2√3fCR)
3. Percentage Regulation: {( VNL – VFL ) / VFL} * 100%
Page 75 of 104
RESULT:
1. The Ripple factor for the Half-Wave Rectifier with and without filters wasmeasured.
2. The % regulation of the Half-Wave rectifier wascalculated.
EXP.NO: 9 DIFFERENTIAL AMPLIFIER USING FET

Page 76 of 104
DATE:
AIM:
To design a differential amplifier using JFET and also, determine the CMRR of the amplifier
APPARATUS REQUIRED:

1 FET BFW10 2
2 Resistor 1kΩ 3
3 Dual Trace CRO 20MHz 1
5 Bread Board 1
THEORY:
1. A differential amplifier is a voltage amplifier that amplifies the difference between the two
inputsignals.
2. It is widely used in analog integrated circuits, because of its good bias stability, high
voltage gain and high inputimpedance.
3. The basic characteristic of differential amplifier is that, it is DC-coupled and avoids the use
of large bypasscapacitors.
4. FET differential amplifier has higher input impedance than BJT differentialamplifier.
5. The differential amplifier is said to operate in common-mode configuration when same
voltage is applied to both the inputterminals.
6. The ability of differential amplifier to reject a common-mode signal defined by its common-
mode Rejection Ratio (CMRR).
7. CMRR is expressed as the ration of differential gain to the common-modegain.
Page 77 of 104
CIRCUIT DIAGRAM:
Differential Mode Gain
Common Mode Gain
PRECAUTION:
Page 78 of 104
2. Do not switch on the power supply unless you have checked the circuit connections as per the
circuitdiagram.
PROCEDURE:
4. The input sine wave signal with appropriate amplitude from the function generator is fed to the
circuit.
5. The output is viewed in the CRO and the corresponding differential gain iscalculated.
6. The frequency of the input signal is varied and the output signal gain is tabulated for different
frequencies.
7. A frequency Vs Gain (dB) plot using semilog sheet is plotted and the bandwidth of the given
amplifier is calculated from theplot.
8. Connect the circuit as shown infig.2.
9. Apply input signal and observe the output usingCRO.
10. Calculate the common-modegain.
11. Calculate CMRR of theamplifier.
OBSERVATION:
Page 79 of 104
Differential Mode Gain
Input voltage,Vs= mV
Ad= 20 log (Gain)

Input Output Gain = Vo dB
frequency voltage,
(Hz) Vo Vs
Common Mode Gain
Input voltage, Vs =mV
Input Output voltage, Gain = Vo

frequency Vo Ac = 20 log (Gain) dB
Vs
(Hz) (volts)
Calculation:
Page 80 of 104
RESULT:
Thus the differential amplifier using JFET was designed and also CMRR of the amplifier was
determined. The CMRR value of the amplifieris .
Page 81 of 104
EXP.NO: 10 STUDY OF CRO
DATE:
AIM
To study the operation and applications of Cathode Ray Oscilloscope.
APPARATUS REQUIRED
Sl. No. Apparatus Range Typ Quantit
e y
100Kpf
1 Capacitor - 1
-
1 K Ohm
2 Resistor - 2
3 Voltmeter (0-2V)MC 30MHZ 1

(0-1MHz)
4 Function Generator 0-30 V 1
(0-20MHz
5 CRO 1 KΩ 1, 2
6 Connecting Wire - - 1
THEORY
An oscilloscope is a measuring device used commonly for measurement of voltage, current, frequency, phase
difference and time intervals. The heart of the oscilloscope is the cathode ray tube, which generates the electron
beam, accelerates the beam to high velocity, deflects the beam to create the image, and contains the phosphor
screen where the electron beam eventually becomes visible. To accomplish these tasks, various electrical
signals and voltages are required. The power supply block provides the voltages required by the cathode ray
tube to generate and accelerate the electron beam, as well as to supply the required operating voltages for the
other circuits of the oscilloscope. Relatively high voltages are required by the cathode tubes, on the order of a
few thousand volts, for acceleration, as well as a low voltage for the heater of the electron gun, which emits the
electrons. Supply voltages for the other circuits are various values usually not more than few hundred volts.The
oscilloscope has a time base, which generates the correct voltage to supply the cathode ray tube to deflect this
part at a constant time dependent rate. The signal to be view is fed to you vertical amplifier, which increases
the potential of the input signal to a level that will provide a usable deflection of the electron beam. To
synchronize the horizontal deflection the vertical input, such that the horizontal deflection starts at the same
point of the input vertical signal each time it sweeps, a synchronizing or triggering circuit is used. This circuit
is the link between the vertical input and the horizontal time base.
Page 82 of 104
Page 83 of 104
PROCEDURE:
Voltage and Time period Measurement:
1. Select the sine output of the signal generator, set at 1KHz.
2. Feed the signal to the vertical input of CRO.
3. Adjust level and time base to get one or two cycles of the sine signal on the
oscilloscope, andcalculate the vertical scale.
4. Count the number of vertical divisions NV on the scope and find peak-peak level.
Vpp = NV X (Volts/Division)
Calculate Vrms as Vpp / 2√2
5. Measure the signal with an AC milli voltmeter as well. It gives the rms value of the
signal.
6. Measure the Time period ‘T’ of the signal by counting the number of horizontal
divisions NH covering the span of one cycle.
T = NH X (Time/Division)
7. Calculate the frequency as f = 1/T.
8. Apply DC voltage from the regulated power supply and measure the DC level on the
scope.
CURRENT MEASUREMENT BY A TEST RESISTOR

1. Connect a 1KΩ Resistor of enough wattage.
2. Measure the voltage across this resistor on the scope
Calculate current as I = V/R.
Page 84 of 104
PHASE MEASUREMENT USING LISSAJOUS PATTERNS (X-Y MODE)
1. To Measure the phase difference of two sine waves their frequencies must be equal.
2. Connect a 1Volt peak-peak, 1KHz sine wave signal from the function generator to the horizontal input of the
CRO.
3. Connect the output of phase shift network to the vertical input as shown in figure.
Calculate the phase angle as

Sine φ = A/B
A: Distance between the points where the ellipse crosses the y-axis and the origin.
B: Distance between the origin and the y – co-ordinate of the maxima of the ellipse.
Calculate theoretical phase difference as
θ = tan-1 (f1/f2)
Where f2 = 1/2ΠRC f1 = input signal frequency.
Page 85 of 104
OBSERVATIONS
AC VOLTAGE & FREQUENCY MEASUREMENT
S.no Input signal CRO Reading Vrms = Vpp/ 2ϒ2 Frequency

frequency Y=1/T (KHz)
Peak to peak amplitude Time period –
Vpp (v) T(msec)
DC VOLTAGE & DC CURRENT MEASUREMENT
s.no DC Input voltage CRO Reading DC voltage-Vdc (v) DC current

(v) Idc = Vdc / R (A)
PHASE MEASUREMENT USING LISSAJOUS PATTERN
s.no Lissajous pattern Practical phase difference (Ф) Theoretical phase

difference (Ф)
Page 86 of 104
RESULT
The operation and applications of Cathode ray oscilloscope have been studied.
Page 87 of 104
EXP.NO: 11 A ASTABLE MULTIVIBRATORS
DATE:
AIM:
To construct and study the operation of astablemultivibrator using 555 timer
APPARATUS REQUIRED:
Sl.
Description Range Quantity
No.
1 IC 555 1
2 Resistor 10kΩ. 1
3 Capacitor 0.1µF,0.01µF 1
4 Bread board - 1
5 Connecting wires - as required
6 Cathode ray oscilloscope (20 MHZ) 1
THEORY:
The 555 timer can be used with supply voltage in the range of + 5 V to + 18 V and can drive up to 200 mA. It
is compatible with both TTL and CMOS logic circuits because of the wide range of supply voltage the 555
timer is versatile and easy to use in the astablemultivibrator. The timer is oscillated between two threshold
levels 1/3 Vcc and 2/3 Vcc in order to generate a square wave form. No external signal source is required for
such generation and hence this is called as a free running multivibrator.
Page 88 of 104
CIRCUIT DIAGRAM :
Page 89 of 104
PRECAUTION:
2. IC pin connections should be checkedproperly.
PROCEDURE:
2. Pins 4 and 8 are shorted and connected to power supply Vcc (+5V)
3. Between pins 8 and 7 resistor R1 of 10 kΩ is connected and between 7 and 6 resistor R2 of 4.7 kΩ is
connected. Pins 2 and 6 are shortcircuited.
4. In between pins 1 and 5 a Capacitor of 0.01µF isconnected.
5. The output is connected across the pin 3 andGND.
6. In between pins 6 and GND, a Capacitor of 0.1µF isconnected.
7. Theoretically, charging time Tc is given byTc=0.69(R1+R2) C1, Discharging time Td is given by
Td= 0.69R2C1. The frequency f is given by f= 1.45/(R1+2R2)C1 . The percentage of duty cycle is
(Tc/(Tc+Td))*100.
8. Practically Td and Tc are measured and wave forms are noted and theoretical values are verified
with practicalvalues.
9. Connect diode between pins 7 and2.
10. Theoretically with diode connected charging time is given by Tc=0.69R1C1. Discharging time
is given byTd=0.69R2C1.
11.Practically Td and Tc are noted and verified with theoreticalvalues.
Page 90 of 104
OBSERVATION:
Sl. No. Charging Time (Tc) Discharging Time (Td)
Theoritical Practical Theoritical Practical
CALCULATION:
1. tON=0.69(R1+R2)C
2. tOFF = 0.69R2C
3. T = tON+tOFF
4. % Dutycycle = tON / (tON+tOFF) *100
MODEL GRAPH:
Page 91 of 104
RESULT:
The obtained value of dutycycle= % Output waveforms of astablemultivibrator was

observed and the duty cycle was calculated and the practical value was found to be equal to the theoretical
value.
Page 92 of 104
EXP.NO: 11 B MONOSTABLE MULTIVIBRATORS
DATE:
AIM:
To construct and study the operation of monostablemultivibrator using 555 timer
APPARATUS REQUIRED:
Sl. Description Range Quantity

No.
1 IC 555 1
2 Resistor 10 kΩ 1
3 Capacitor 0.1µF,0.01µF 1
4 Bread board ----- 1
5 Connecting wires ----- as
required
6 Cathode ray (0-20)MHz 1
oscilloscope
THEORY:
Monostablemultivibrator is also known as triangular wave generator. It has one stable and one quasi
stable state. The circuit is useful for generating single output pulse of time duration in response to a
triggering signal. The width of the output pulse depends only on external components connected to the
op-amp. The diode gives a negative triggering pulse. When the output is +Vsat, a diode clamps the
capacitor voltage to 0.7 V. Then, a negative going triggering impulse magnitude Vi passes through R, C
and the negative triggering pulse is applied to the positive terminal.
Let us assume that the circuit is in stable state. The output V0 is at +Vsat. The diode D1 conducts and
Vc the voltage across the capacitor„C‟ gets clamped to 0.7 V. The voltage at the positive input terminal
through R1R2 potentiometer divider is +ßVsat. Now, if a negative trigger of magnitude Vi is applied to
the positive terminal so that the effective signal is less than 0.7 V. The output of the Op-Amp will switch
from +Vsat to –Vsat. The diode will now get reverse biased and the capacitor starts charging
exponentially to –Vsat. When the capacitor charge Vc becomes slightly more negative than –ßVsat, the
output of the op-amp switches back to +Vsat.
The capacitor „C‟ now starts charging to +Vsat through R until Vc is 0.7V.
V0= Vf+(Vi - Vf) е-t/RC
ß = R2 / (R1+R2)
Page 93 of 104
If Vsat>>Vp, R1=R2 and ß = 0.5, then, T = 0.69 RC
CIRCUIT DIAGRAM :
Page 94 of 104
PRECAUTION:
2. Do not switch on the power supply unless you have checked the circuit connections as per
the circuitdiagram.
PROCEDURE:
2. Negative triggering is applied at the terminal2.
3. The output voltage is measured by connecting the channel-1 atpin3.
4. The output voltage across capacitor is measured by connecting the channel-2 at the pin3.
5. Theoretically the time period is calculated by T= 1.1R1C1, where R1= 10 kΩC1=0.1µF.
6.Practically the charging and discharging timers aremeasured.
Page 95 of 104
OBSERVATION:
Sl. No. Charging Time (Tc) Discharging Time (Td)
Theoritical Practical Theoritical Practical
MODEL GRAPH:
Page 96 of 104
RESULT:
The obtained value of timeconstant= ms
The output Waveforms of monostablemultivibratorwere observed and time constantwas calculated and the
practical value was found to be equal to the theoretical value.
Page 97 of 104
EXP.NO: 12 REALIZATIONS OF PASSIVEFILTERS
DATE:
AIM:
To determine experimentally the frequency response of low pass and high pass filters and note down the cut
off frequency.
APPARATUS REQUIREMENT:
Sl. Name of the Range Quantity

No. Apparatus
1. Function Generator - 1
2. CRO - 1
3. Resistor 1
4. Capacitor 1
5. Inductor 1
6. Breadboard - 1
7. Connecting wires - As
required
THEORY:
High pass filter:
This filter allows only high frequency of AC voltage and rejects the low frequency components at the output.
We know that Xc< 1/f (Reactance is inversely proportional to the frequency). At low frequency, reactance is
very high so it does not allow any signal at the output. At high frequency, reactance is very low so it does not
allow the entire signal at theoutput.
Low pass filter:
This filter allows only low frequency of AC voltage and rejects the high frequency components at the output.
We know that Xc< f (Reactance is directly proportional to the frequency). At low frequency, reactance is very
low so it does not allow the entire signal at the output. At high frequency, reactance is very high so it does not
allow any signal at the output.
Page 98 of 104
CIRCUIT DIAGRAM :
High Pass Filter
Low Pass Filter
Page 99 of 104
PRECAUTION:

2. Do not switch on the power supply unless you have checked the circuit connections as per the
circuitdiagram.
PROCEDURE:
1. The circuit connections are made as per circuitdiagram.
2. Switch on the power supply and increase the input frequency in steps of 100 Hz and note down the
corresponding output voltage in thevoltmeter.
3. Calculate the gainvalue.
4. Draw the graph between frequency Vsgain.
Page 100 of 104

OBSERVATION:
High PassFilter
S.No Input Voltage Frequency Output Voltage Gain = 20log(V0/Vin)
Low PassFilter
S.No Input Voltage Frequency Output Voltage Gain =

20log(V0/Vin)
HighPassfilter Low Passfilter
Page 101 of 104

RESULT:
Thus the low pass and high pass filter was designed successfully.
Page 102 of 104

Page 103 of 104

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EC8311

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TAGORE INSTITUTE OF ENGINEERING AND

Department of Electrical and Electronics Engineering

EC8311 – ELECTRONICS LABORATORY

Academic Year 2020-2021

1. Characteristics of semiconductor diode and zener diode.

Characteristics of a NPN Transistor under common emitter , common collector

Characteristics of JFET(Draw the equivalent circuit)

Characteristics of UJT and generation of saw tooth waveforms.

Design and testing of RC phase shift, LC oscillators.

Differential amplifiers using FET.

10. Frequency and phase measurement using CRO

11. Astable and Monostablemultivibrators

Realization of passive filters

i) To plot the forward and reverse V-I characteristics of given PN - junctiondiode.

Sl. No Components / Equipments Specifications Quantity

PN-JUNCTION DIODE FORWARD BIAS

1. The connections are given as per the circuit diagram.

PN-JUNCTION DIODE REVERSE BIAS

1. The connections are given as per the circuit diagram.

S.No FORWARD VOLTAGE VF (V) FORWARD CURRENT IF (mA)

TABULATION: REVERSE BIAS

S.No REVERSE VOLTAGE IR (V) REVERSECURRENT IR (µA)

V-I CHARACTERISTICS OF PN JUNCTION DIODE

Sl. No Components / Equipments Specifications Quantity

ZENER DIODE FORWARD BIASED

1. The connections are given as per the circuit diagram.

ZENER DIODE REVERSE BIASED

TABULATION FOR REVERSE BIAS

The Breakdown voltage was found to be_______________

Sl. No Components / Equipments Specifications Quantity

Transistor BC107 Max Rating : 50V 1A, 1

Ammeters MC (0-25)mA, Each One

1. The connections are given as per the circuit diagram.

S.NO VcE = 1 V VcE = 2 V

TABULATION FOR OUTPUT CHARACTERISTICS

PIN DIAGRAM OF BC107

Thus the CE transistor input and output characteristics were plotted.

Sl. No Components / Equipments Specifications Quantity

1. The connections are given as per the circuit diagram.

TABULATION FOR OUTPUT CHARACTERISTICS OF BJT

Thus the CB transistor input and output characteristics were plotted.

Sl. No Components / Equipments Specifications Quantity

i) To plot the drain and transfer characteristics of JFET.

Sl. No Components / Equipments Specifications Quantity

Voltmeters MC (0-10)V, MC (0- Each One

SYMBOL PIN DIAGRAM

VGS = -4V VGS = -6V

TABULATION FOR TRANSFER

Thus the drain and transfer characteristics of JFET are plotted.

Sl. No Components / Equipments Specifications Quantity

SYMBOL PIN DIAGRAM

S.NO VBB = 5V VBB = 10V VBB =15V

VE (V) IE (mA) VE (V) IE (mA) VE (V) IE (mA)

Sl. No Components / Equipments Specifications Quantity

Signal Frequency Output Voltage Voltage Gain, dB

MODEL GRAPH: Frequency response of CE amplifier

Sl. No Components / Equipments Specifications Quantity

2. Switch ON the lamp and power supply.

5. Note its corresponding Voltmeter and Ammeter reading.

6. Draw the graph between voltage and current.