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FAT Model Paper

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23 views2 pages

FAT Model Paper

Uploaded by

MadG Log
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The questions are model questions only. Do not rely upon only these questions.

Those
who plan for minimum pass 50-60 % can study first.

1. Minimize the logic function Y(A,B,C,D) = ∑m(0 1, 2, 3, 8, 9, 11,14) + ∑d (7,12) using


Karnaugh map. Draw logic circuit for the simplified function using only NAND gates.

2. Write a Verilog code for given logic Diagram by using structural model

3. Design a 4 x 1 mul plexer using a 2 x 1 mul plexer and implement the following the Boolean
expression F(x,y,z) = Ʃ(1,2,6,7)
4. Implement the binary equivalent mul plica on of two-signed numbers (+6 ×-2) with the
necessary steps. Iden fy the suitable method and explain the step-by-step procedure to
implement it.

5. Design a synchronous counter for the given sequence using JK – FF

1.  4  7  2 6 30….

6. Design a sequence detector using Mealy state machine to detect the input sequence
1010 with overlapping that produces an output 1 if the sequence is detected else 0
otherwise. Implement the circuit using D flip flop.
7. Design a BCD-to-Excess-3 code converter using (a) PLA, and (b) PAL.

8. Convert the following expression in canonical SOP form and implement it using
AND, OR and NAND logic gates. Don’t use any other gates.

F(A, B, C ) = A + A BC
9. Write the Verilog HDL for an 1x8 demux using behavioural model along with test bench

10. Design a four-input priority encoder with input D1 having the highest priority, D0 having the
next lower priority, D2 has the next lower priority and input D3 the lowest priority. Write the
corresponding Verilog HDL code.
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11. Iden fy a suitable algorithm to mul ply two n-bit signed binary numbers. Discuss the step-
by-step process involved in mul plying the binary equivalent of 5 × 5 using this algorithm.

12. Design a synchronous counter for the given sequence using D – FF

0  5  3  2 1  70….

13. Design a sequence detector using Mealy state machine to detect the input sequence
1011 that produces an output 1 if the sequence is detected else 0 otherwise.
Implement the circuit using D flip flop.

14. Design an Excess-3-to-BCD code converter using (a) PLA, and (b) PAL.

15. Simplify the following Boolean expression using K- Map and write the truth table
with the circuit diagram using only NOR gates.

F = B̄C̄ + A B̄ + A BC̄ + A B̄C D̄ + Ā B̄C̄D + A B̄CD

16. Write behavioral Verilog code for J-K ip op along with test bench

17. Implement the following following Boolean func on using a mul plexer.
F(A,B,C,D) = ∑(0,1,5,6,9,11,12,13,14)

18. Discuss the step-by-step process of two 4-bit numbers (1100 and 0110) being added and
subtracted using an adder-subtractor circuit. Draw the logic diagram of the circuit and
explain the importance of over ow detec on.

19. Design an asynchronous MOD 13 counter using T – FF.

20. Write a Verilog HDL in behavioural model for a sequence detector with non-
overlapping to detect a sequence of 1011 using Moore state machine.

21. Implement the following functions using PAL


F1 (A,B,C) = ( 1,2,4,5,7)
F2 (A,B,C) = ( 0,1,3,5,7)
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