United Institute of Management, Naini, Allahabad

Department
Master of Computer Application

Subject
Computer Organization

MCA 215
Session: January , 2015-May ,2015

Author
Dr.Manmohan Mishra
Asst. Professor

Unit 1 Index
1.1 Register transfer
1.2 Bus and Memory Transfers
1.2.1 Tree-state bus buffers
1.2.2 Memory transfer
1.2.3 Bus Architecture
1.3 Micro-Operations
1.3.1 Register transfer Micro-Operations
1.3.2 Arithmetic Micro-Operations
1.3.3 Logic Micro-Operations
1.3.4 Shift Micro-Operations
1.4 Booth multiplication

SUGGESTED READINGS:

Text Book
1. Computer System Architecture, M. Mano(PHI)

Reference Books
1. Computer Organization, Vravice, Zaky & Hamacher (TMH Publication)
2. Structured Computer Organization, Tannenbaum(PHI)
3. Computer Organization, Stallings(PHI)
4. Computer Organization, John P.Hayes (McGraw Hill)

1.1 Introduction Register transfer

A micro operations is an elementary operation performed on the information stored in one or
more registers. The result of the operation may replace the previous binary information of a
register or may by transferred to another register.
The symbolic notation used to describe the micro operation transfer among registers is called a
register transfer language. The term “register transfer” implies the availability of hardware logic
circuits that can perform stated micro operation and transfer the results to the operation to the
same or another register.
Register Transfer
We designate computer registers by capital letters to denote the function of the register. For
example, the register that holds an address for the memory unit is usually called a memory
address register, represented by MAR. Other examples are PC (for program counter), IR (for
instruction register) and R1 (for processor register). We show the individual flip-flops in an n-bit
register by giving numbers them in sequence from 0 through n - 1, starting from 0 in the right
most position and increasing the numbers toward the left.
A 16-bit register is divided into two halves. Low byte (Bits 0 through 7) is assigned the symbol L
and high byte (Bits 8 through 15) is assigned the symbol H. The name of a 16- bit register is PC.
The symbol PC(L) represents the low order byte and PC(H) designates the high order byte. The
statement R2 V R1 refers the transfer of the content of register R1 into register R2. It should be
noted that the content of the source register R1 does not change after the transfer. In real
applications, the transfer occurs only under a predetermined control condition. This can be
shown by means of an “if-then” statement:
If P=1 then R2 VV R1
where P is a control signal generated in the control section of the system. For convenience we
separate the control variables from the register transfer operation by specifying a control
function. A control function is a Boolean variable that is equal to 1 or 0. The control function is
written as follows: P: R2 VVV R1
Bus
Since a computer has many registers, paths must be provided to transfer information from one
register to another. If separate lines are used between each register and all other registers,
number of wires will be excessive in the system. A more efficient scheme for transferring
information between registers in a multiple-register configuration is a common bus system. A
bus structure consists of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time. Control signals determine which register is
selected by the bus during each particular register transfer.
A common bus system can be constructed using multiplexers. These multiplexers select the
source register whose binary information is then placed on the bus. A bus system will multiplex
registers of a bit each to produce an n-line common bus. The number of multiplexers required to
construct the bus is equal to n, where n is the number of bits in each register. The size of each
multiplexer must be k × 1 since it multiplexes k data lines. A bus system can be constructed with
‘three-state gates’ instead of multiplexers.
A three-state gate is a digital circuit that shows three states. Two of the states are equivalent to
logic 1 and 0. The third state is a high impedance state. The high impedance state behaves like an
open circuit, which means that the output is disconnected and does not have a logic significance.
The one most commonly used in the design of a bus system is the buffer gate.
The graphic symbol of a three state buffer gate is shown in the figure given below. The
control input determines the output.

The construction of a bus system for four registers is shown in the figure in on the next
page.
1.2.1 Three state table buffers
Three state table buffers: A bus system can be constructed with three state gates instead of
multiplexers. A three states gate is digital circuit that exhibits three states. Two of the states are
signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance
state. The high-impedance state behaves like an open circuit, which means that the output is
disconnected and does not have logic, such as AND or NAND. However the one most
commonly used in the design of a bus system is the buffer gate.
The construction of a bus system with three state table buffers is shown in the following figure:

1.2 Bus and Memory Transfer

A read operation implies transfer of information to the outside environment from a memory
word, whereas storage of information into the memory is defined as write operation.
Symbolizing a memory word by the letter M, it is selected by the memory address during the
transfer which is a specification for transfer operations. The address is specified by enclosing it
in square brackets following the letter M. For example, the read operation for the transfer of a
memory unit M from an address register AR to another data register DR can be illustrated as:
Read: DR ←M[AR]
The write operation transfer the contents of a data register to a memory word M selected by the
address. Assume that the input data are in register R1 and the address in the AR. The write
operation can be stated symbolic as follows: Write: M [AR] ← R1 This cause a transfer on
information from R1 into the memory word M selected by the address in AR.
1.2.2 Bus Architecture
A shared communication path consisting of one or more connection lines is known as bus and
the transfer of data through this bus is known as a bus transfer.”
AND
When a data is read from the memory or is stored in memory is referred to as memory transfer

Transfer Among Three Register

R1 R2 R3

22
The basic computer has eight registers, a memory unit, and a control unit. Paths must be
provided to transfer information from one register to another and between memory and registers.
The number of wires will be excessive if connections are made between the outputs of each
register and the inputs of the other registers. A more efficient scheme for transferring
information in a system with many registers is to use a common bus. It is known that how to
construct a bus system using multiplexers or three-state buffer gates
The outputs of seven registers and memory are connected to the common bus. The specific
output that is selected for the bus lines at any given time is determined from the binary value of
the selection variables S2,S1, and S0. The lines from the common bus are connected to the inputs
of each register and the data input of each register and the data inputs of the memory. The
particular register whose LD (load) input is enabled receives the data from the bus during the
next clock pulse transition. The memory receives the contents of the bus when its write input is
activated.
Four registers, DR, AC, IR, and TR, have 16-bits each.
Two registers, AR and PC, have 12 bits each since they hold a memory address.
When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to 0’s.
When AR or PC receives information from the bus, only the 12 least significant bits are
transferred into the register
The input register INPR and the output register OUTR have 8 bits each and communicate with
the eight least significant bits (LSB) in the bus. INPR is connected to provide information to the
bus but OUTR can only receive information from the bus.
This is because INPR receives a character from an input device which is then transferred to
AC. OUTR receives a character from AC and delivers it to an output device.
There is no transfer from OUTR to any of the other registers.
The 16 lines of the common bus receive information from sex registers and the memory unit.
The bus lines are connected to the inputs of six registers and the memory. Five registers have
three control inputs: LD (load), INR (increment) and CLR (clear).
This type of register is equivalent to a binary counter with parallel load and synchronous clear.
The increment operation is achieved by enabling the count input of the counter. Two registers
have only a LD input.
The input data and output data of the memory are connected to the common bus, but the memory
address is connected to AR.
Therefore, AR must always be used to specify a memory address. By using a single register for
the address, we eliminate the need for an address bus that would have been needed otherwise.
The content of any register can be specified for the memory data input during a write operation.
Similarly, any register can receive the data from memory after a read operation except AC.
The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of inputs.
One set of 16-bit inputs come from the outputs of AC.
They are used to implement register micro-operations such as complement AC and shift AC.
Another set of 16-bit inputs come from the data register DR.
The inputs from DR and AC are used for arithmetic and logic micro-operations, such as add DR
to AC or and DR to AC.
The result of an addition is transferred to AC and the end carry-out of the addition is transferred
to flip-flop E (extended AC bit).
A third set of 8-bit inputs come from the input register INPR.
Note that the content of any register can be applied onto the bus and an operation can be
performed in the adder and logic circuit during the same clock cycle. The clock transition at the
end of the cycle transfers the content of the bus into the designated destination register and the
output of the adder and logic circuit into AC.
For example, the two micro-operations:
DR ← AC and AC ← DR
Function Table

S2 S1 S0 Register
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

Multiple BUS Organization

 Multiple BUS Organization
BUS A
Special
Purpose
Register G1
R0
General R1 PC Special
Purpose … ALU
R2 Purpose
Register .
R3 Register G2
.
R4
MBR
R5 Buffer
Register

BUS B
Two Bus Organization of the data path

33

All General Purpose register connected with both Bus A and Bus B from Two Bus
Organization. Two operand required by the ALU are routed in One Clock cycle , hence
Instruction execution become faster since ALU does not wait for the second operand as with
Single Bus Organization. The information passed on to the Bus are may be from general purpose
register or from special purpose register. Also Special purpose register are divided in two group ,
one group lift of ALU and are connected to Bus A and Other group is at right of the ALU.
The data form two special purpose register belong to the same group can not be transferred to the
ALU at Same time. The output of the ALU may be routed to either general purpose register or
special purpose register. The ALU does not have any input buffer register and hence both buses
will be busy in carrying the operands during binary operations. Therefore the output of the ALU
is first stored into the out put register and transfer of required operand and loading of the ALU
output buffer register takes in one clock cycle. The content of ALU output register is routed to
the destination with the help of either bus A and Bus B in the second clock cycle.

Multiple BUS Organization

 Multiple BUS Organization
BUS A

BUS B
Special
Purpose
Register G1
R0
General R1 PC Special
Purpose … ALU
R2 Purpose
Register .
R3 Register G2
.
R4
MBR
.
R5 Buffer
….
Register

BUS C
Three Bus Organization of the data path

37

The performance of two bus organization can be further improved by adding a third bus C at the
output of ALU. The addition of third bus allows the system to perform the operation, in one
clock cycle as there are three separated in the system.
Example : R3 R1 + R2
Bus System for Four Register
A common bus system can be constructed with the help of multiplexer and decoders where
decoder select the destination register for the bus transfer.
Multiplexer select the source register whose binary information is placed on the bus and decoder
select one destination register to transfer the information from the bus.
Function Table for bus

S1 S0 Register

0 0 A

0 1 B

1 0 C

1 1 D
Function Table

S1 S2 Register Selected
 0 0 A

0 1 B

1 0 C

1 1 D

Bus system for Four Register

A common bus system can be constructed with the help of multiplexer and decoder where the
decoder select the destination register for the bus transfer.
The multiplexer select the source register whose binary information is then placed on the bus
and decoder select the destination register to transfer the information from the bus.
Two multiplexer are shown in the figure one for low order significant bit and one for high order
significant bit.
if the register is of n bits , n multiplexer is required to produce n bus line. These n line in the bus
are connected to the n inputs of all register. S1 And S2 are selection lines connected to selection
input of all n multiplexer. The selection line choose n bit of one register and transfer those n bit
in to n line common bus.
When S1S0= 00 the 0 data in put of all n multiplexer are selected and causes the n bits from
register A to transfer in to the n- line common bus since out put of this register are connected to 0
data input of each multiplxer.
1.3 Micro-Operations
A micro-operation is an elementary operation which is performed on the data stored in
registers. We can classify the micro-operations into four categories:
1. Register transfer: transfer binary information from one register to another.
2. Arithmetic: perform arithmetic operations on numeric data stored in registers.
3. Logic: perform bit manipulation operation on non-numeric data stored in registers.

4. Shift: perform shift operations on data stored in registers.

1.3.1 Arithmetic Micro-operations

These micro-operations perform some basic arithmetic operations on the numeric data stored in
the registers. These basic operations may be addition, subtraction, incrementing a number,
decrementing a number and arithmetic shift operation. An ‘add’ micro-operation can be specified
as: R3 V R1 + R2
It implies: add the contents of registers R1 and R2 and store the sum in register R3. The add
operation mentioned above requires three registers along with the addition circuit in the ALU.
Subtraction, is implemented through complement and addition operation as:
R3 V R1 – R2 is implemented as
R3 V R1 + (2’s complement of R2)
R3 V R1 + (1’s complement of R2 + 1)
R3 V R1 + R2 + 1

An increment operation can be symbolized as:

R1 V R1 + 1
while a decrement operation can be symbolized as:
R1 V R1 – 1
We can implement increment and decrement operations by using a combinational circuit or
binary up/down counters. In most of the computers multiplication and division are implemented
using add/subtract and shift micro-operations. If a digital system has implemented division and
multiplication by means of combinational circuits then we can call these as the micro-operations
for that system. An arithmetic circuit is normally implemented using parallel adder circuits. Each
of the multiplexers (MUX) of the given circuit has two select inputs. This 4-bit circuit takes
input of two 4-bit data values and a carry-in-bit and outputs the four resultant data bits and a
carry-out-bit. With the different input values we can obtain various micro-operations. Equivalent
micro-operation Micro- operation name
R V R1 + R2 Add
R V R1 + R2 +1 Add with carry
R V R1 + R2 Subtract with borrow
R V R1 + 2’s Subtract
R V R1 Transfer
R VR1 + 1 Increment
R V R1 – 1 Decrement
1.3.2 Logic Micro-operations
These operations are performed on the binary data stored in the register. For a logic micro-
operation each bit of a register is treated as a separate variable. For example, if R1 and R2 are 8
bits registers and
 R1 contains 10010011 and
R2 contains 01010101
R1 AND R2 00010001
Some of the common logic micro-operations are AND, OR, NOT or complements.
Exclusive OR, NOR, NAND.
We can have four possible combinations of input of two variables. These are 00, 01, 10
and 11. Now, for all these 4 input combination we can have 24 = 16 output combinations of a
function. This implies that for two variables we can have 16 logical operations.
Logic Micro Operations
SELECTIVE SET
The selective-set operation sets to 1 the bits in register A where there are corresponding 1’s in
register B. it does not affect bit positions that have 0’s in B. the following numerical example
clarifies this operation:-
1010 A before
1100 B (logic operand)
1110 A after
SELECTIVE COMPLEMENT
The selective-complement operation complements bits in register A where there are
corresponding 1’s in register B. it does not affect bit positions that have 0’s in B. the following
numerical example clarifies this operation:-
1010 A before
1100 B (logic operand)
0110 A after
SELECTIVE CLEAR
The selective-clear operation clears to 0 the bits in register A only where there are
corresponding 1’s in register B. For example:-
1010 A before
1100 B (logic operand)
0010 A after
MASK OPERATION
The mask operation is similar to the selective-clear operation except that thebits of A are cleared

only where there are corresponding 0’s in B. the mask operation is an AND micro operation, for

example:-
1010 A before
 1100 B (logic operand)
1000 A after masking
INSERT OPERATION
The insert operation inserts a new value into a group of bits. This is done by first masking the
bits and then Oring them with the required value. For example, suppose that an A register
contains eight bits, 0110 1010. to replace the four leftmost bits by the value 1001 we first the
four unwanted bits:-
0110 1010 A before
0000 1111 B (mask)
0000 1010 A after masking
and then insert the new value:-
0000 1010 A before
1001 0000 B (insert)
1001 1010 A after insertion
The mask operation is an AND microoperation and the insert operation is an OR microoperation.
CLEAR OPERATION

The clear operation compares the words in A and B and produces an all 0’s result if the two

numbers are equal. This operation is achieved by an exclusive-OR microoperation as has own by
the following example:
1010 A
1010 B
0000 A A ++ B
When A and B are equal, the two corresponding bits are either both 0 or both 1. In either case the

exclusive-OR operation produces a 0. the all-0’s result is then checked to determine if the tow

numbers were equal.

1.3.4 Shift Microoperations
Shift microoperation can be used for serial transfer of data. They are used generally with the
arithmetic, logic, and other data-processing operations. The contents of a register can be shifted
to the left or the right. During a shift-right operation the serial input transfers a bit into the
leftmost position. The serial input transfers a bit into the rightmost position during a shift-left
operation. There are three types of shifts, logical, circular and arithmetic.
Logical shift
A logical shift operation transfers 0 through the serial input. We use the symbols shl and shr for
logical shift left and shift right microoperations, e.g.
R1 ← shl R1
 R2 ← shr R2
are the two micro operations that specify a 1-bit shift left of the content of register R1 and a 1-
bit shift right of the content of register R2.

Circular shift
The circular shift is also known as rotate operation. It circulates the bits of the register around the
two ends and there is no loss of information. This is accomplished by connecting the serial
output of the shift register to its serial input. We use the symbols cil and cir for the circular shift
left and circular shift right. E.g. suppose Q1 register contains 01101101 then after cir operation,
it Vcontains 0110110 and after cil operation it will contain 11011010.
Arithmetic Shift
An arithmetic shift micro operation shifts a signed binary number to the left or right. The effect
of an arithmetic shift left operation is to multiply the binary number by 2. Similarly an arithmetic
shift right divides the number by 2. Because the sign of the number must remain the same
arithmetic shift-right must leave the sign bit unchanged, when it is multiplied or divided by 2.
The left most bit in a register holds the sign bit, and the remaining bits hold the number. The sign

bit is 0 for positive and 1 for negative. Negative numbers are in 2’s complement form. Following

figure shows a typical register of n bits.

Bit Rn-1 in the left most position holds the sign bit. Rn-2 is the most significant bit of the
number and R0 is the least significant bit. The arithmetic shift-right leaves the sign bit
unchanged and shifts the number (including the sign bits) to the right. Thus Rn-1 remains the
same, Rn-2 receives the bit from Rn-1, and so on for other bits in the register.

1.4 Floating point numbers-IEEE 754 standard

IEEE specifies two format for representing floating point number.
Once – 32 bits (Known as Single precision)
Second – 64 bits (known as Double Precision)
Floating point number performing Arithmetic operation with floating points numbers.
most CPU’s these days have floating point that confirm to the IEEE floating point standards.
Both single and double precision format use radix 2 for fraction and excess notation for
exponents .
In decimal number system a floating point number may be represented as
+- A1. A2 A3A4 A5 A6 A7 X 10 +-B1B2
Where Ai and Bi are decimal digits and A i’s from the mantissa part and Bi’s from the exponents
part
 Three pieces:
– sign
– exponent
– significand
1bit 8bit 23bit Single Precision

 Format:
1bit 11bit 52bit Double Precision

Single precision (32-bit) format

Both format works the same differing only by the number of bits used to present each components.

+ 1.Fx2(E-127) Single Precision

+ 1.Fx2(E-1023) Double Precision

IEEE 754 Format

Parameter Single Precision Double Precision

Bits in Sign 1 1
Bits in exponents 8 11

Bits in mantissa 23 52

Total Bits 32 64

Exponents System Excesss127 Excesss1023

Exponent Range -126 to + 127 -1022 to + 1023

Smallest normalized number 2-126 2-1022

Largest normalized number Approx 2 128 Approx 21023

Example
Convert the 32bit single precision IEEE 754 numbers below in binary.

1101011010110110101100000000000

Sign exponent mantissa

Booth Multiplication Algorithm

If the numbers are represented in signed 2’s complement then we can multiply them by using
Booth algorithm. In fact the strings of 0's in the multiplier need no addition but just shifting, and
a string of l's in the multiplier from bit weight 2k to weight 2m can be treated as 2k+1 - 2m. For
example, the binary number 001111 (+15) has a string of 1's from 23 to 20(k = 3, m = 0).

Final product in AQ = 0110110101

The number can be represented as 2k+1 – 2m = 24- 20= 16 - 1 = 15. Therefore, the
multiplication M x 14, where M is the multiplicand and 14 the multiplier may be computed as M
x 24 - M x 21. That is, the product can be obtained by shifting the binary multiplicand M four
times to the left and subtracting M shifted left once. Booth algorithm needs examination of the
multiplier bits and shifting of the partial product. Prior to the shifting, the multiplicand added to
the partial product, subtracted from the partial product, or left unchanged by the following rules:
1. The multiplicand is subtracted from the partial product when we get the first least
significant 1 in a string of 1's in the multiplier.
2. The multiplicand is added to the partial product when we get the first Q (provided
that there was a previous 1) in a string of 0's in the multiplier.
3. The partial product does not change when the multiplier bit is the same as the
previous multiplier bit

Hardware Implementation
SUGGESTED READINGS:

Text Book
1. Computer System Architecture, M. Mano(PHI)
Reference Books
1. Computer Organization, Vravice, Zaky & Hamacher (TMH
Publication)
2. Structured Computer Organization, Tannenbaum(PHI)
3. Computer Organization, Stallings(PHI)
4. Computer Organization, John P.Hayes (McGraw Hill)