International Journal of Engineering & Technology, 7 (2.

4) (2018) 105-108

International Journal of Engineering & Technology

Website: www.sciencepubco.com/index.php/IJET

Research Paper

Design of High-Speed Multiplier Architecture Based

on Vedic Mathematics
Chaitanya CVS1*, Sundaresan C2, P R Venkateswaran3, Keerthana Prasad4, V Siva Ramakrishna5
1245 School of Information Sciences, Manipal Academy of Higher Education, Manipal, Karnataka
3 Bharat Heavy Electricals Limited, Tiruchurapalli, Tamil Nadu

*Email: [email protected]

Abstract

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for
cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some
algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an
increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area.
Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A
novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in
this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design
is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is
compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

Keywords: Binary Multiplication, Multiplier Architecture, Vedic Multiplier.

are main arithmetic components used for processing scientific data,
the excessive power consumption and delay attracts attention from
1. Introduction the research community. The current trends in architectures have
been shifting towards multiple arithmetic cores working in parallel
One of the most important classes of integrated circuits is so that they can process large amounts of data with relatively low
processors. Over the years, the density of integration has grown power and delay. Unfortunately, traditional arithmetic units
tremendously and hence, today, it is possible to have large number dissipate large amounts of power [5].Thus there is a need to look at
of functionalities packed in an IC. As the number of functions special multiplier architectures to be designed and implemented in
increases, the need for computation also grows. Also, with the appropriate circuit design styles[6-10] to achieve computation at
advent of new process technologies, shrinking of feature size low power, besides providing high performance. As the complexity
coupled with the availability of modern CAD tools we could of arithmetic core increases, the need for low power multipliers
develop complex integrated circuits for various applications such with adequate performance also grows.
as digital signal processing, mobile computations and In order to address the low power computation along with high
communications, multimedia applications and processing required performance, a new approach to multiplier design based on ancient
for scientific computing and applications. One of the main Vedic Mathematics has been explored. The mathematical
functional blocks in such circuits is arithmetic unit - the most operations using Vedic mathematics are very fast and require less
important part of the processors- whose speed and efficiency are hardware. This aspect of Vedic mathematics can be utilised to
very crucial for meeting the requirements of the applications they increase the computational speed of multipliers. This paper
have to support [1]. describes the design and implementation of an 8 bit Vedic
Multipliers have become an integral part of modern processors and multiplier based on Urdhva-Tiryagbhyam Sutra. The number of
computation systems. Especially, in digital signal processors speed steps required to perform a multiplication operation by using
of the computation is extremely important in addition to low power UrdhvaTiryagbhyam Sutra are considerably less compared to the
dissipation. Therefore, there is growing demand for low power and conventional multiplication techniques [11]. In this paper, we have
high performance multipliers [2]. As multiplication is a crucial further explored a novel method to enhance the speed of a Vedic
arithmetic operation in processors and digital computer systems, multiplier by replacing the existing full adders and half adders with
multipliers are the core building block for many algorithms in a multiplexers. The implementation of pre-computation logic using
wide variety of computing applications [3, 4]. Although multipliers multiplexer based adder and XOR logic resulted in reduction of

Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted
use, distribution, and reproduction in any medium, provided the original work is properly cited.
106 International Journal of Engineering & Technology

delay. Moreover, in this paper, we also propose modifications to Figure 3 shows a block where two 4 bits binary inputs are given to
the conventional architecture of multiplier so as to reduce the Vedic_4_bit_mul which produces 8 bit binary product. Pre-
power-delay product. The structure of the paper is divided as computation is used in this method, while calculating the product
follows: The methodology and the architecture of the proposed the column wise carries are obtained first by using MUX addition
Vedic multiplier is given in section 2 and section 3 respectively. also the product values are obtained during this process. Finally,
Results are presented in section 4. Finally, conclusion and future the column wise P [15:0] values are obtained by XORing the
research is given in section 5. values in each column.

2. Methodology of Proposed Vedic Multiplier

The stepwise flow of the proposed Vedic Multiplier has been
shown in Figure 1. The 8 bit binary inputs A[7:0] and B[7:0] are
sent to the Vedic_4_bit_mul (4×4 bit Vedic multiplier) in pairs of
4 bits. The 8 bit outputs from each 4 bit Vedic multiplier are
arranged as shown in the first block of the flow diagram. The
carries obtained from each column are calculated and also the
partial products of each column are XORed column wise side by
side. As shown I the second block in the flow diagram the pre-
calculated carries and the XORed partial products are XORed Figure 3: Block Diagram of a 4 bit Vedic Multiplication
column wise to obtain the 8×8 product P[15:0]
This unit of 4 bit multiplier was used to perform the 8 bit
multiplication as shown in the Figure6 where AH is A7 A6 A5 A4,
AL is A3 A2 A1 A0, BH is B7 B6 B5 B4 & BL is B3 B2 B1 B0.
The outputs from Vedic_4_bit_mul are positioned as shown in the
Figure 4 [13] for addition and the carries are generated using MUX
based addition. After the pre-computation, the calculated carries
from each column and the outputs of 4 bit Vedic modules are
placed as shown in Figure 5 and XORed to obtain the final product
P [15:0].The output gives the final 16 bit product which is obtained
in a parallel mechanism instead of sequential mechanism.

Figure 1: Bitwise flow diagram of 8×8 Vedic Multiplier

3. Architecture of Proposed Vedic Multiplier

In our proposed Vedic multiplier an 8 bit Binary Vedic

multiplication is realized using 4-bit Vedic multiplication, Figure 2
shows 4 bit Vedic multiplication where A3,A2,A1,A0 &
B3,B2,B1,B0 are 4 bit binary inputs and P7,P6,P5,P4,P3,P2,P1,P0
are the binary output bits.

Figure 4: 8 bit Vedic Multiplication

Figure 5: 8 bit Vedic Multiplier with expanded 4 bit module

Figure 2: 4 bit Vedic Multiplication
International Journal of Engineering & Technology 107

4. Results

The synthesis of conventional & Vedic multiplier digital circuits

was implemented using Verilog coding with the help of Cadence
Encounter RTL Compiler in 180nm technology. The physical
Design for the multipliers was obtained using Cadence Encounter
RTL-to-GDSII System. The input to the tool was the netlist file
generated from the Cadence Encounter RTL Compiler. The
remaining parameters and specifications used were standard values
already specified within the tool. While inputting the Import
Design Browser in the Physical Design, the MMMC File is set
with both the best and worst case libraries. Delay, Power & Area
was estimated from the Physical Designs.
The results obtained from the proposed multiplier are given in the
table 1 and 2. Cadence Design Compiler was made use of while
synthesis and Cadence Encounter RTL-to-GDSII System for
obtaining the Physical Layout using standard 180nm technology. Figure 6: Physical Design Layout of Vedic Multiplier
The Physical layout of the proposed multiplier has been shown in
Figure 6. Table 2: Summary of Post Physical Design Results for Multiplier using
The Power-Delay Product obtained from the Vedic Multiplier is Cadence
29.62 % less than the conventional Multiplier. But, the area is
11.54 % more than the conventional design. The delay was 20.94
% less than the Conventional Multiplier delay which is within the
target specification i.e., 10 to 30%. The high speed multiplication
is achieved with the overhead in area and power.

5. Conclusion

In this paper, a high speed and low power architecture for

multiplier was proposed using algorithm based on Vedic
mathematics. An 8 bit Vedic Multiplier using Urdhva-
Tiryagbhyam Sutra has been designed and implemented. The
conventional architecture has been integrated with pre-computation
logic in which adders were replaced by multiplexers.

The results show that the architecture is 20.94% faster, dissipates The power dissipation can be further reduced by employing
10.99% less power and 29.62 % improvement in terms of power existing low power techniques like Dynamic Voltage Scaling,
delay product when simulated in 180nm technology. This clearly operand isolation, use of Multiple Vth devices etc., in the design of
demonstrates that the primary objective of design of an efficient multiplier. Reduction of delay can be further improved by
multiplier and reduction of power-delay product in comparison designing the pre-computation logic using Quine McCluskey
with conventional multiplier and divider has been achieved. This solver in such a way that the number of carries generated in each
will surely help increasethe computation speed of MAC and other column will be reduced.
Arithmetic units in processors, leading to faster execution of
instructions. References
Table 1: Summary of Post Synthesis Layout Results for Multiplier using
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