International Journal of Innovative Research in Computer Science & Technology (IJIRCST)

ISSN: 2347-5552, Volume-10, Issue-2, Mar 2022

https://doi.org/10.55524/ijircst. 2022.10.3.79
Article ID CST1050, Pages 391-394
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The Study of the Various VLSI Design Method

Dharminder Kumar
Assistant Professor, Department of Electrical Engineering, RIMT University, Mandi Gobindgarh, Punjab, India
Correspondence should be addressed to Dharminder Kumar; [email protected]
Copyright © 2022 Made Dharminder Kumar. This is an open-access article distributed under the Creative Commons Attribution License,
which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

ABSTRACT- VLSI outlooks for the Very Large Scale KEYWORDS- Dynamic Power, Leakage power, Very
Integrated, and this is a very advanced electronic Large - Scale Integrated (VLSI), VLSI design.
technology. VLSI circuits have been used in a variety of
applications, including microcontrollers, microcomputers, I. INTRODUCTION
n chips, chips used in a graphics processor, camcorders,
and video cameras. The notion of the "VLSI design VLSI layout is divided into 2 types: high wattage VLSI
approach" is discussed in this article, and research layout and lower power consumption VLSI design[1][2].
methodologies for VLSI design are provided using flow This paper will discuss the recent advancements and trends
charts. The results of VLSI design, as well as the status of in reduced power VLSI design[4][5] The purpose of this
the methodologies and numerous infrastructures and essay is also to illustrate and prove the present and future
designs associated with the VLSI design programme and trends in low power VLSI research and development.
approach, were also illustrated in this article. A network [6].In the field of electronics, the breadth of VLSI is also
security branch, silicon implementation systems, a fairly broad[7].
semiconductors section, and semiconductor foundries Between numerous different papers within the subject of
from throughout the world are all part of the VLSI VLSI study as well as VLSI design technique, a document
architecture design. Since it is responsible for entitled presents a notion of a way of reduced power
manufacturing processes and development such as VLSI[8]. Also, several approaches were employed to
transistor count, processing shrinkage, voltages scaling, tackle complicated complex challenges of computer
timers gating, and fuzzy logic control, this research system as well as electronics systems[3]. The Layout of
examines the newest growth and advances of low power VLSI Design Methods by Lynn Conway discussed the
VLSI. VLSI power loss is a well-known problem, origins of VLSI, stating that in the early 1970s, a British
according to the research, because this limited VLSI is in scientist named Carver Pear brandy began a research and
charge of the manufacturing implementation, including study series titled electronic circuit design, in which he
transistor size, process shrinkage, voltage scaling, clock mentioned how very large scale work could be done with
gating, and so on. This study also aims to demonstrate and the help of small chips, and during this time he founded the
illustrate current and future trends in low-power VLSI nMOS design industry [9][10]. The circuit architecture and
research and innovation. In the realm of electronics, VLSI physical design of a VLSI design are shown in Figure
has a wide variety of applications. 1[11].

Figure 1: Illustrating the Principle of VLSI Design

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 International Journal of Innovative Research in Computer Science & Technology (IJIRCST)

Figure 2: Illustrating the Reduction of Dynamic Power

A. Dynamic Power outcomes based on the Joint Evolution of the Multi-Level

Cluster of Systems. Different work and research in the
Dynamic power is the energy consumed by a system as a
subject of VLSI design, as well as current work in
device switches from one state to another, and this activity
knowledge engineering, have been discussed(19). Due to
may be seen using VLSI design.[12][13]. The power
its complexity, VLSI design may be challenging to solve,
utilised when the device is charging the loads connected to
and societal considerations, infrastructure, and scale
the item, as well as the fault current power of the device
impact can all affect VLSI design techniques. Finally, in
when it is charging, is referred to as dynamic power. The
the sphere of extremely large-scale integration, provide
power dissipation that can occur in CMOS is seen in Figure
knowledge engineering that allows knowledge
2 [14][15] .
transformation [4] [25].
B. Leakage Power L. A. Hemaspaandra addressed the necessity for VLSI in
Leakage power of VLSI hardware, where a certain amount electronic domains like computer systems, mobile phones,
of waste power is not used by scheme once scheme semiconductors, and so on in research papers (19). The
switches from one state to the other, leakage electricity dynamic powers of electronic circuit is swallowed by the
generated by system when device is not linked to device when the gadget is extremely freely and readily
transitions, and then when gadget is both static as well as transformed or flowing from one state to another,
trying to switch, but the most important issue associated according to this study [20] [22]
with leakage power is when gadget has been in inactive However, the most popular and mainstream approaches
form.[16][17]. include clock gating, which is a highly effective way for
reducing leakage power into the loop and also indicates
that the modification of threshold voltage is precisely
II. LITERATURE REVIEW
proportional to the delay and leakage current in a graphical
There have been numerous publications in field of VLSI, representation. Clustered voltage scaling is the second
because it is a rapidly growing and very well technology most common technique for reducing leakage power
in the field of computers. There have been numerous [23][24].
applications of VLSI in various fields, including computer
systems, cellular telephones, and transistor chip resizing. III. DISCUSSION
Various methodologies were also used to resolve complex
issues of embedded scheme and electronic parts Low power and High power VLSI design are the two types
processes[21]. of VLSI design. This paper will look at current
In this article, a graphic titled "Knowledge Dissemination developments and trends in reduced VLSI design. Low
and Evolution" was shown, which discussed how different power VLSI is fixed area, according to the results, since it
techniques practitioners developed into practise artefacts. is responsible about everything from the transistor sizing
The many types of cMos and nMos were discussed by a to process shrinkage, voltages scaling, clock gating, and
receiving community. The MPC experiences sketched out adiabatic logics. The goal of that research is to show and
how the experiment approach and computer connection prove existing and future trends and developments in the
architecture were implemented [18]. field of low-power VLSI. In the field of electronics. In the
This page includes a table displaying the diverse structure field of electronics, the breadth of VLSI is also fairly broad
and results of VLSI design, as well as the numerous [7]. Between numerous different papers within the subject
of VLSI study as well as VLSI design technique, a

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document entitled presents a notion of a way of reduced King Saud University - Computer and Information Sciences.
power VLSI[8]. Also, several approaches were employed 2020.
to tackle complicated complex challenges of computer [6] Sub-threshold Design for Ultra Low-Power Systems. Sub-
system as well as electronics systems threshold Design for Ultra Low-Power Systems. 2007.
[7] Zhang Y. A foundation for the design and analysis of robotic
systems and behaviors. ProQuest Dissertations and Theses.
IV. CONCLUSION 1994.
[8] Venkatraman S, Sundhararajan M. Area and interconnect
This article also exhibits current and new improving length optimization for VLSI floor planning problem by
technologies in field of theVLSI methodology and design, using harmony search algorithm. Int J Recent Technol Eng.
which is based on the research and design of VLSI. To 2019;
fully comprehend the Mead-Conway approach, first learn [9] Tsunekawa Y, Hinosugi M, Miura M. Design and VLSI
about the specific idea, which explains how the qualities of evaluation of a high-speed cellular array divider with a
certain knowledge systems, techniques, and substructure selection function. Electr Eng Japan (English Transl Denki
impact extents and rates of, diffusion, creation, Gakkai Ronbunshi). 1998;
convergence, knowledge, integration, and displacement. [10] Saab Y. New 2-way multi-level partitioning algorithm.
VLSI Des. 2000;
Many topics of the VLSI design approach are explained
[11] Ignatyev V V., Kovalev A V., Spiridonov OB, Kureychik
and clarified. This article presents thoughts and research VM, Ignatyeva AS, Safronenkova IB. Hybrid genetic-
on key cognitive and social phenomena that occur paired-permutation algorithm for improved VLSI
throughout the theory creation, testing, and theory revision placement. ETRI J. 2021;
processes that are involved in the design of design [12] Scalise F, Balanza M, Chauve N, Combelles P, Penard P,
knowledge. We have gained the confidence and Del Toso C, et al. A prototype VLSI solution for digital
understanding to dig more thoroughly into the qualities of terrestrial TV receivers conforming to the DVB-T standard.
knowledge and the processes of its evolution as a result of SMPTE J. 1997;
this effort. As a result, we are identifying potential for the [13] Venkatraman S, Sundhararajan M. A metaheuristic
algorithm for VLSI floorplanning problem. Int J Recent
practical application of computer science and artificial
Technol Eng. 2019;
intelligence findings to the creation and deployment of [14] Scalise F, Balanza M, Chauve N, Combelles P, Penard P,
new knowledge engineering concepts. Del Toso C, et al. A Prototype VLSI Solution for Digital
VLSI has wide ranges of the applications in field of Terrestrial TV Receivers Conforming to the DVB-T
electronics. A document named provides a thought of a Standard. In: International Workshop on HDTV 1996. 2015.
means of reduced power VLSI is among a number of [15] Chen X, Liu G, Xiong N, Su Y, Chen G. A Survey of Swarm
articles on the subject of VLSI research and design Intelligence Techniques in VLSI Routing Problems. IEEE
approach. In addition, numerous ways were used to Access. 2020;
address the complex issues of computer and electronics [16] Wolf M, Mukhopadhyay S. VLSI for the Internet of Things.
Computer (Long Beach Calif). 2017;
systems. The origins of VLSI were discussed in Lynn
[17] Sravani MM, Ananiah Durai S. Attacks on cryptosystems
Conway's The Layout of the VLSI Design Methods, that implemented via VLSI: A review. J Inf Secur Appl. 2021;
stated that in early 1970s, a British scientist name Carver [18] Macii E, Pedram M, Somenzi F. High-level power
Pear brandy began a study and research series titled modeling, estimation, and optimization. IEEE Trans
electronic circuit designs, in which he mentioned how Comput Des Integr Circuits Syst. 1998;
large scales work could done byhelp of small chips, and [19] Sakemi Y, Morino K, Morie T, Aihara K. A Supervised
during this time he founded the nMOS design industry. Learning Algorithm for Multilayer Spiking Neural
Networks Based on Temporal Coding Toward Energy-
Efficient VLSI Processor Design. IEEE Trans Neural
REFERENCES Networks Learn Syst. 2021;
[1] Sharma M, Gupta N, Gupta R. POWER REDUCTION [20] Hemaspaandra LA. SIGACT news complexity theory
TECHNIQUES IN VLSI. Int J Eng Technol Manag Res. column 31. ACM SIGACT News. 2001;
2020; [21] Sathasivam S, Mamat M, Mansor MA, Kasihmuddin MSM.
[2] Soumya N, Sai Kumar K, Raghava Rao K, Rooban S, Hybrid discrete hopfield neural network based modified
Sampath Kuma R P, Santhosh Kumar GN. 4-bit multiplier clonal selection algorithm for VLSI circuit verification.
design using cmos gates in electric VLSI. Int J Recent Pertanika J Sci Technol. 2020;
Technol Eng. 2019; [22] Dewan MI, Kim DH. NP-Separate: A New VLSI Design
[3] Liu B, Qu G. VLSI supply chain security risks and Methodology for Area, Power, and Performance
mitigation techniques: A survey. Integr VLSI J. 2016; Optimization. IEEE Trans Comput Des Integr Circuits Syst.
[4] Brown RB, Bernhardt B, LaMacchia M, Abrokwah J, 2020;
Parakh PN, Basso TD, et al. Overview of complementary [23] Bartolozzi C, Indiveri G. Synaptic dynamics in analog
GaAs technology for high-speed VLSI circuits. IEEE VLSI. Neural Comput. 2007;
Transactions on Very Large Scale Integration (VLSI) [24] Sivakumar R, Jothi D. Recent Trends in Low Power VLSI
Systems. 1998. Design. Int J Comput Electr Eng. 2014;6(6):509–23.
[5] Kumar SBV, Rao P V., Sharath HA, Sachin BM, Ravi US, [25] Elrabaa MS, Abu-Khater IS, Elmasry MI, Elrabaa MS, Abu-
Monica B V. Review on VLSI design using optimization Khater IS, Elmasry MI. Low-Power VLSI Design. In:
and self-adaptive particle swarm optimization. Journal of Advanced Low-Power Digital Circuit Techniques. 1997.

Innovative Research Publication 394