Autonomous Testing for 3D-ICs with IEEE

Std. 1687

Ye, Jin-Cun; Kochte, Michael A.; Lee, Kuen-Jong; Wunderlich,

Hans-Joachim

Proceedings of the 25th IEEE Asian Test Symposium (ATS’16) Hiroshima, Japan,
21-24 November 2016

doi: http://dx.doi.org/10.1109/ATS.2016.56

Abstract: IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing
embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE
Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test
controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and
provide required control signals to control the whole test procedure. This design can achieve at-speed,
autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area
and test cycle overhead of this architecture is small considering its autonomous test capability.

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 Autonomous Testing for 3D-ICs with
IEEE Std. 1687
Jin-Cun Ye1, Michael A. Kochte1,2, Kuen-Jong Lee1, and Hans-Joachim Wunderlich2
1
Dept. EE, National Cheng Kung University, Tainan, Taiwan
2
ITI, University of Stuttgart, Germany

Abstract— IEEE Std. 1687, or IJTAG, defines flexible serial studies in [8] and [9] demonstrate the application of IEEE 1687
scan-based architectures for accessing embedded instruments to setup test sessions in 2D designs and the achievable degree of
efficiently. In this paper, we present a novel test architecture that automation when using ICL and PDL with commercial tools.
employs IEEE Std. 1687 together with an efficient test controller
In [3], IEEE 1687 is adopted in a 3D-IC DFT architecture to
to carry out 3D-IC testing autonomously. The test controller can
deliver parallel test data for the IEEE Std. 1687 structures and the
distribute test data to cores and dies. The architecture supports
cores under test, and provide required control signals to control pre-bond and post-bond test modes. It uses the die-detection
the whole test procedure. This design can achieve at-speed, mechanism of [4] to automatically determine whether another
autonomous and programmable testing in 3D-ICs. Experimental die is stacked and connected on top and accordingly establish the
results show that the additional area and test cycle overhead of this required communication paths. If a pre-bond test is performed,
architecture is small considering its autonomous test capability. test data is provided from external test equipment via probe pads.
Test time and external ATE costs can be reduced by built-in
Index Terms—IEEE Std. 1687, IJTAG, reconfigurable scan test controllers that can drive the test application of complex
network, autonomous testing, 3D-ICs, DFT.
VLSI systems autonomously [7], [10], [11]. Autonomous in-
I. INTRODUCTION field testing is required for safety-critical systems to detect latent
or emerging defects before they cause a failure during operation.
3D-ICs are stacked dies with vertical interconnection using
In [7] and [11], an autonomous on-chip test platform based on
through-silicon vias (TSVs). They provide increased communi-
IEEE 1500 is proposed that extracts test patterns from an
cation bandwidth and allow the integration of heterogeneous external source, distributes the patterns to cores under test, and
dies. The effective and efficient test of such 3D-ICs requires
collects and compares the responses. It also generates the
novel design-for-test (DFT) architectures for pre- and post-bond
required control signals for the test procedure automatically.
testing of both stacked dies and TSVs [1], [12]. The use of the With this test platform, high speed and low-cost testing has been
common test standards IEEE Stdį 1149.1, IEEE Stdį 1500, the achieved for 2D designs.
ongoing proposal IEEE P1838 [13], as well as novel standards In [14], the authors proposed test scheduling algorithms to
for highly reconfigurable scan based access such as IEEE Stdį compute optimal session-based or session-less test schedules in
1687 [2] allows to construct flexible and highly scalable DFT an IEEE 1687 architecture that consider resource conflicts
architectures for 3D-ICs. between tests in a session and power constraints.
In [5], the authors proposed the use of die-level wrappers In this work, we present an architecture for autonomous
based on IEEE 1149.1 (JTAG) and IEEE 1500 for 3D-IC test testing of 3D-ICs with the following features:
supporting pre-bond, mid-bond, and post-bond testing. This 1. A hardware-efficient test architecture for 3D-ICs based on
architecture also supports parallel test access to the IEEE 1500 IEEE 1687 for test access configuration and IEEE 1500 for
wrappers. The test access modes in [5] between the dies of a 3D- core and die test with low access and reconfiguration time.
IC such as die access, die bypass, and turnaround mode are 2. A controller for autonomous testing which extends the work
similar to those outlined in IEEE P1838 [13]į of [7] to support IEEE 1687 so as to facilitate the required
Reconfigurable scan networks have been recently test access modes for 3D-IC testing. The architecture allows
standardized in IEEE 1687 [2] for serial scan-based access of on- both ATE-driven test for high-volume production test as well
chip instrumentation (on-chip test data registers) with low access as autonomous in-field test. Patterns can be accessed from
time via a JTAG test access port (TAP). This standard, also external equipment such as a generic ATE or a low-cost ATE,
called the IJTAG standard, allows hierarchical networks as well or directly from a storage device such as FLASH or SD-card
as irregular networks with complex sequential and (for autonomous in-field testing).
combinational dependencies between instrument accesses [6]. 3. The accessed test data can be formatted and applied to the
The reconfigurability allows to change the scan path such that CUTs directly, or buffered in shared system memory or local
the targeted instruments can be accessed with a minimum memory using a direct memory access (DMA) mechanism
number of shift cycles. The standard also defines the Instrument and then applied to the CUTs. The required memory space
Connectivity Language (ICL) to describe the scan network can be reduced by splitting the test into test sessions. The
structure, and the Procedural Description Language (PDL) to required sessions and test access configurations across the
describe instrument accesses and access sequences. The case dies are setup using IEEE 1687.
4. A modified core test wrapper architecture to reduce the area Table 1 Supported 3D-IC post-bond test modes and control
overhead of a dedicated die-level wrapper for TSV test with signals of multiplexers
low access time. Mode T0 T1
5. Support of wrapper scan cells with one or two flip-flops DieBypass-Turnaround 1 0
depending on the required test modes. DieBypass-Elevator 0 0
The next section describes the proposed architecture and its DieInclude-Turnaround 1 1
components. Section III explains the autonomous test procedure DieInclude-Elevator 0 1
in the 3D-IC. Experimental results are discussed in Section IV, The bottom die contains the TAMC. The TAMC can provide
followed by the conclusion. parallel test data through TAM wires to the cores under test and
II. DFT ARCHITECTURE FOR AUTONOMOUS 3D-IC TEST generate the required control signals for the whole test procedure
of the stacked 3D-IC. With this controller, the test data can be
A. 3D-IC DFT architecture based on IEEE Std. 1687 read from an external source and buffered in the chip. Then the
Figures 1 shows the 3D DFT architecture for a stack of three test application and examination procedures can be carried out
dies. Die0 at the bottom and Die1 in the middle are both logic autonomously without using external test equipment.
dies, and Die2 on the top is a memory die. Every die contains TAP-CTRL From/To Top
four test components: 1) an IEEE 1687 based Scan Path Control Die 2
CSU 0 Scan Out
unit (called “remotely controlled scan mux architecture” in IEEE W

T0
1

T1
1687 [2]), 2) the scan chains of the cores under test that are TAPC
1
0

connected into a number of parallel daisy-chains, 3) a TAP- įġįġį

C0
controller (TAPC) to control the parallel daisy-chains and Scan
Path Control unit, and 4) two top-level multiplexers (T0, T1) to
TAP-
CTRL
1
P Mem
0
0 W
determine the test data paths. The bottom die further contains a BIST
1
test controller, called Test Access Mechanism controller W-1
1
(TAMC). W
1 W
TPI P
The parallel daisy-chains are constructed by serially TPO 1
1
ScanPathControl
0 SelectIR
W Scan In
connecting the parallel scan chains of cores in each die with
TAP-CTRL Data
multiplexers (see Figure 1). Note that we add bypass registers on
the bypass paths to avoid a long combinational path. The Die 1
CSU 0 Scan Out
Ř
multiplexers and test enable signal of cores are controlled by the
T0

1
T1

1
Scan Path Control unit. This allows to setup any combination of TAPC 0

parallel scan chains of cores under test in a test session by C0 C1

shifting appropriate configuration setup data into the Scan Path TAP- 1 Core0 Core1
CTRL P
Control unit and enables flexible test schedules in a complex die 0
0
WIR WIR
since the tested and non-tested cores can be quickly and centrally W
1
changed. By use of IEEE 1687 compliant structures, this setup W-1 1
W
can be easily controlled and the required shift patterns can be TPI
1
P
W
generated/retargeted at higher level using the procedure TPO 1 1
ScanPathControl
W
0 SelectIR
Scan In
description language PDL [2] and EDA tool support.
TAP-CTRL Data
The architecture supports both pre-bond and post-bond
Die 0
testing. For the post-bond test, the top-level multiplexers T0 and CSU 0
Scan Out Ř
T1, which control the flow of test data from daisy-chains of cores
T0

1
T1

at die-level, are added and controlled by the Scan Path Control TAPC Ř
0

unit. With these two multiplexers, we can configure the C0 C1

following 3D-IC test paths: die-bypass, elevator, or turnaround Core0 Core1
TEST
[2]. The cores in a die can be either included or bypassed in the START
configured test path. When a die is in the elevator mode, the test RESULT
TAMC
WIR
1
WIR

data will be forwarded to the die above and test responses will W-1 1
be received from the upper die. In the turnaround mode, the test
ScanPathControl
data will not be delivered to the upper die, but turned back to the WScan In
1
SelectIR
lower die (either including or bypassing the current die). Table
External Memory or ATE
1 summarizes the supported 3D-IC post-bond test modes of the
proposed architecture and the corresponding multiplexer control Figure 1. 3D DFT architecture for autonomous 3D-IC test
signals.
The TAP-controller (TAPC) in each die is used to control the Since IEEE 1687 is a serial access architecture (except for a
JTAG-compliant operations including shift, capture and update. broadcast feature), it cannot be directly used as parallel TAM
The port signals TAP-CTRL in Figure 1, which come from here. To distribute the parallel test data to the IEEE 1500 test
either the TAMC or probe pads, include TCK, TMS, and TRST. wrappers of the cores, we use a dedicated parallel TAM and
control it by IEEE 1687 scan registers. IEEE 1687 is also used TAM_0. When the TAPC is in the configuration stage
to configure the core wrappers. (SelectIR=1), the Scan Path Control unit will be activated such
In the upper dies, we add JTAG-compliant probe pads for the that the configuration setup data can be shifted in serially and
pre-bond test mode and two additional multiplexers (P0, P1) stored in the update register by an update operation. When the
controlled by the automatic die detection mechanism proposed TAPC is in the test data application stage (SelectIR=0), the Scan
in [4] to switch the test path between pre-bond (P0=1, P1=1) and Path Control unit is bypassed so it does not affect the pattern
post-bond (P0=0, P1=0) test modes. Notice that the TPI and TPO load/unload.
are parallel I/Os in order to provide multiple-bit test data in pre- These configuration setup data determine which cores the
bond mode. test data will be delivered to (or bypassed) and which 3D-IC test
For memory testing, we can also use the proposed path at die-level will be used. The length of the Scan Path
architecture to access and enable the memory BIST and shift out Control unit depends on the number of cores and the test modes
the result after the test is finished. to be used in each die. Assume that the number of cores is N,
then the length of the scan path control unit will be N+3 in this
B. Scan Path Control unit case, where the extra three bits denote the control signals of
The main idea of reconfigurable scan networks based on multiplexers T0 and T1, and the signal to enable the TSV testing
IEEE 1687 is to use control registers and multiplexers on the mode of core wrappers as explained in Section II.D.
scan paths so as to configure the scan paths in each die during
testing. One widely used implementation based on IEEE 1687 is Configureparallel SelectIR
the Segment Insertion Bit (SIB)-based hierarchical structure, in scanchains
which each SIB controls the access to the scan segments or ScanPathControl
chains of a core under test, and the SIBs themselves are part of
the scan path. In [2], a “remotely controlled scan mux 1bit
architecture (RCSMA)” is also suggested, which can reduce the
number of shift cycles when accessing the scan chains compared TAM_0
to a SIB-based design. The basic concept of the RCSMA is From
shown in Fig 2. TAMC TothedaisyͲ
In this work, we adapt the RCSMA and call the control TAM_1 chainof
register for the scan paths on a die the Scan Path Control unit. TAM_2 coresunder
WͲ1bits test
The Scan Path Control unit and the scan chains in the cores of 烉
each die are on two separate paths. One can use a select signal TAM_W-1
to switch the active scan path between Scan Path Control and the
scan chains of the cores. Before shifting in the test patterns, one Figure 3. Scan path control unit and TAM signals
has to select the Scan Path Control and shifts in appropriate setup
data to determine the configuration of the test path. After setting C. Test access mechanism controller (TAMC)
up the configuration, the test patterns can be shifted into the The TAMC is essential for autonomous testing in this work.
desired scan chains for test application. It is connected to the cores under test through IEEE 1687. It can
Select read deterministic test patterns from an external ATE through
(enable) probe pads or pins in the manufacturing phase or from external
ScanPathControl Scan out 2 memory like an SD-card through the system bus for in-field test.
Scan In 2
The TAMC distributes the patterns to the cores under test, and
collects and evaluates test responses. It generates all the required
Scan out 1
Scan In 1 ScanChain ScanChain ScanChain control signals for the test architecture and test procedure on-
chip. Upon test completion, the final results can be read and
displayed, for instance, using an LED screen for in-field testing.
Select Even in the pre-bond phase, we can still use a less complex ATE
(enable)
Figure 2. Remotely controlled scan mux architecture (RCSMA)
to send the plain test data to the TAMC through pads and test the
bottom die.
Our test architecture is based on the RCSMA because it is With the TAMC, we achieve the following features:
easier to control with the TAMC. However, with the RCSMA
one needs 2 scan paths and one additional control signal, both 1. Autonomous and at-speed testing.
leading to the increase of TSVs and probe pads (for pre-bond 2. The requirements on external ATE are significantly
test) in 3D-ICs. In this work we address this problem such that reduced for manufacturing test and can be eliminated for
no additional pin is needed. We modify RCSMA by reusing the in-field testing.
selectIR signal from TAPC and sharing the test access 3. Only a few pins are needed for accessing the TAMC. No
mechanism (TAM) wires of the CUTs. Figure 3 shows how the extra test pins are required for parallel scan chains.
Scan Path Control unit is operated after the modification. The
Scan Path Control unit is placed in front of the first TAM wire, More information of the TAMC can be found in [7].
D. Modification of IEEE 1500 wrapper scan cells to test TSVs system bus or pins. These TAMC setup data include the number
In order to test the TSVs, 3D-ICs usually have a die-level of test patterns, location of test patterns of the test session and
wrapper or boundary scan chain in each die [1] so that every shift length of the configuration. Then the TAMC resets the DFT
TSV or I/O can be easily accessed and tested. In a core-based architecture, applies the scan path configuration and starts
SOC environment, there may already exist cores with core-level reading and applying test data for the test session according to
wrappers and some I/Os of cores may also connect to TSVs. If the setup information.
the core-level wrapper scan cells can be reused to access TSVs, The test procedure contains a number of test sessions each of
the die-level wrapper may not be necessary, or the number of which consists of three steps: 1) configuration setup, 2)
wrapper cells can be reduced. instruction register setup, and 3) test data application.
In addition, the boundary scan chain through a core-level In the configuration setup step, the active scan path only
wrapper may be very long. To shorten the test access time to contains the Scan Path Control unit in each die. The TAMC
TSVs accessible from a core-level wrapper, we can bypass the shifts in the configuration setup data into the Scan Path Control
cores that do not connect to TSVs using IEEE Std. 1687 unit and captures it to the update register of the unit to setup the
structures. Figure 4(a) shows a core-level boundary scan chain. configuration of the current test session.
The red blocks denote I/Os that are connected to TSVs. To After the configuration setup, the configuration has been
reduce the access time to the red scan cells, we can add defined. The instruction register setup step is used to shift
multiplexers to bypass the cells that do not connect to TSVs as instructions into the test wrappers of each core under test and
Figure 4(b) shows. When the TSV test signal from the Scan Path define their modes. Because the Scan Path Control unit shares
Control unit is active, the modified core-level wrapper only the selectIR signal in our design in order to reduce test pins and
chains the boundary scan cells that connect to TSVs. Otherwise, TSVs (see Figure 3), the active scan path must contain the Scan
the boundary scan chain contains all cells. In this way, we reuse Path Control unit and the instruction registers of wrappers of
the core-level wrappers for TSV testing and reduce the area and cores under test in each die for the current test session.
performance overhead of additional die-level wrappers. Finally, the TAMC starts to shift test patterns into the parallel
Furthermore, to reduce the area overhead we can use the one- scan chains of the cores under test and collects the test responses
flip-flop boundary scan cell as defined in IEEE Std. 1500. For which are shifted out through the configured test path in the die
complex test patterns, e.g., for TSV crosstalk faults, two-flip- stack. At the same time, the TAMC also reads the mask and
flop boundary scan cells can be added individually. Figure 5 expected responses and compares them with the captured
shows the two boundary scan cells. responses.
The TAMC repeats these steps until every test session has
WSI WSI
been completed. The final test results can be output to external
devices such as ATE or an LED display.
TSV connected
Ƀġ

TSV Test
Ƀġ

IV. EXPERIMENTAL RESULTS

TSV unconnected
In this section, we quantify the area overhead of the proposed
WSO
WSO 3D DFT architecture, estimate the required test time, and report
the obtained area and test scheduling results for a constructed
(a) (b)
experimental 3D-IC. For this 3D-IC, we compare the test time
Figure 4.(a) Original boundary scan chain (b) Modified boundary scan overhead of a SIB-based test architecture and the proposed DFT
chain with bypass for cells not associated with TSVs architecture.
CTO Mode Mode The area overhead Ao for the IEEE Std. 1687 structures in our
CTO
3D DFT architecture can be estimated using the following
CFI 0
CFO
CFI
Shift
0
CFO
equation: Ao = f + W ǘ Tp + N ǘ ( W ǘ Cp + Cr ) (1),
Shift 1

0
0

1
1
where f denotes the fixed area including TAP-controller,
1

FF S U multiplexer P0, and the fixed number of register bits in the scan
path control unit. W and N denote the TAM width and the
WRCK
WRCK Update number of cores in a die. Tp, Cp and Cr represent the area of top-
CTI CTI level paths (including multiplexers T0, T1, P1 and die bypass
Figure 5. Wrapper scan cell with one or two flip-flops registers), core-level paths (including multiplexers Cn and core
bypass register of an individual core), and control bits of cores
III. TEST PROCEDURE in scan path control unit, respectively. Ao depends on the number
of cores and the TAM width, but is independent of the size and
This section explains the test procedure executed by the number of pins of cores.
TAMC. The data for the test application is stored in an external In this work, we use a TSMC 90nm cell library to synthesize
source (external memory or ATE). This data comprises setup the structure. The area in gate count is as follows: f = 165, Tp =
data for the IJTAG architecture, test patterns, masks and 12.9, Cp = 8.6, Cr = 11 and the gate count of the test access
expected test responses. The TAMC loads the setup information mechanism controller (TAMC) in the bottom die is 26525. Table
of the current test session from external source through the 2 shows the area overhead of the DFT components for different
TAM widths (W) and number of cores (N). For medium or large number of test patterns, and fault coverage respectively. The
circuits, the area cost is relatively small. patterns are generated using Synopsys TetraMax. We wrap the
Table 2. Area overhead (in gate count) of IEEE Std. 1687 DFT
cores using IEEE Std. 1500 wrappers and add the required
components in one die for different TAM widths W and numbers of multiplexers such that they can be integrated into the proposed
cores N (without TAMC) architecture for autonomous testing. The width of the TAM is
twelve bits, including a boundary scan chain of the core wrapper.
N
5 10 20 50 100 Circuits b19, b18, b17 are put in the bottom die with the
W
1 275.9 373.9 569.9 1157.9 2137.9 TAMC test controller, and circuits des_perf and ethernet are put
4 443.6 670.6 1124.6 2486.6 4756.6 in the upper die. The area information is shown in Table 4. The
8 667.2 1066.2 1864.2 4258.2 8248.2 columns in Table 4 denote the area of the scan inserted cores, the
16 1114.4 1857.4 3343.4 7801.4 15231.4 area of the core wrappers in gate count, and their percentage in
the whole design respectively. Rows IJTAG_bot and IJTAG_up
We now analyze the number of test cycles in the three steps are the areas of the IJTAG architectures in the bottom die and
of each test session. Assume that D is the number of dies upper die, respectively. The area overhead of the wrapper DFT
included in a test session, Ni is the number of cores in the ith die. and the IJTAG architecture is very small compared to the area
Lij and Lrij denote the length of the scan chains and the length of of the cores. The area overhead of the TAMC test controller is
instruction register of the jth core in the ith die, respectively, and 5.39%. The total area overhead of the proposed DFT architecture
Lsi denotes the scan length of scan path control unit in the ith die. including the TAMC is about 7.69%. Since the area of the
The test cycles of the three steps discussed in Section III can be TAMC does not increase with the number or size of cores or dies,
estimated by the following equations: the area overhead can be even lower for large designs, e.g., less
than 1% for a 4M-gate design.
D 1

¦i 0
Lsi  2  u (Step 1)
Table 4. Area information for the 3D-IC example
D 1 ª N i 1 º Process : TSMC90nm Unit : gate count
¦i 0 ¬
« Ls i  d i ¦ c ij ˜ Lr ij  c ij ˜ 1  d i ˜ 1  1»  u
(Step 2)
Wrap or Wrap or
j 0 ¼ Core Area Area (%)
DFT Area DFT (%)
­° ª
D 1 N i 1 º ½°
®¦ «di ˜ ¦ cij ˜ Lij  c ij ˜ 1  d i ˜ 1  1» ¾ P  1  P ˜ u
(Step 3) b19 144746 912 29.42 0.18
°̄ i 0 ¬ j 0 ¼ °¿ b18 72228 1055 14.68 0.21
b17 25524 1849 5.19 0.38
where cij and di are Boolean variables representing whether the
des_perf 109558 3621 22.26 0.74
cores or dies are included in the scan path. P and u denote the
Ethernet 102154 2667 20.76 0.54
numbers of test patterns in a test session and number of cycles
IJTAG_bot - 668 - 0.14
of update and capture operations. The constant in each equation
IJTAG_up - 549 - 0.11
is due to the bypass register in each path. For a large value of P, TAMC - 26525 - 5.39
the test cycles in Steps 1 and 2 are negligible, since Lij is much Sum 454210 37846 92.31 7.69
larger than Lrij and Lsi. For TSVs testing, we only need to replace Total 492056 100
the parameter Lij in Step 3 with the length of boundary scan
chains for TSVs access. We also calculate the number of test cycles of this design
Note that all of the test data (including the setup data) can be example based on the three test cycle calculation equations
provided to the chip using external test equipment for volume given earlier in this section. For simplicity, we employ the
testing or directly from storage devices such as FLASH or SD optimized session-less (OSL) scheduling algorithm proposed in
card to facilitate autonomous in-field testing. [14] without power and resource constraints to create the desired
In the following experiment, we construct a two-die 3D-IC test sessions. In this session-less schedule, the tests do not have
using ITC’99 and IWLS’05 benchmark circuits. The informa- to start in a synchronized manner, i.e., two cores with different
tion and arrangement of these circuits is shown in Table 3. The numbers of test patterns can start their testing in one session and
columns of the table denote the name of cores, number of I/O after the one with fewer test patterns is fully tested, the one with
ports, number of scan flip-flops, maximum length of scan chains, more test patterns can be further tested in other test session(s).
Table 3. Benchmark circuits and arrangement in 3D-IC example Table 5 shows the details of the computed test sessions for
Core # I/O #SFF SC_len #Pattern FC % post-bond or in-field test. The columns in Table 5 denote the test
b19 51 6642 595 1069 99.59 sessions, tested cores, number of patterns and test cycles in
b18 60 3320 298 764 100 different steps mentioned above. The results show the test cycle
b17 134 1415 129 669 99.98 overhead of the proposed architecture (Steps 1 and 2 of the
des_perf 297 8808 801 55 97.48 equations above), which comprises the additional cycles induced
ethernet 210 10544 959 674 99.53 by the proposed test architecture during the test procedure for
Arrangement of Dies the setup and configuration of the test data paths. This overhead
Die Cores Area Max SC_len is very small compared to Step 3, the actual application time of
0 b19, b18, b17 273507 1023 the pattern data.
1 des_perf, ethernet 218549 1761
 Table 5. Test sessions and test cycles 1687 for scan chain reconfiguration, modify IEEE Std. 1500
Cycles Cycles wrappers for high efficiency parallel scan and TSV test, and
Session #Patterns
step (3) step (1)+(2) employ an embedded controller for autonomous in-field testing.
b19, b18, b17, It can efficiently and flexibly execute the test of a 3D-IC with
1 des_perf, ethernet
55 156179 58
b19, b18, b17, very little or even no use of external test equipment so as to
2 ethernet
614 1223230 55 reduce test cost. The advantages of such a test architecture
3 b19, b18, ethernet 5 11161 52 include: 1) facilitation of in-field autonomous testing; 2) support
4 b19, b18 90 81895 34 of highly flexible test scheduling via IEEE Std. 1687 structures;
5 b19 305 184513 31 3) low area overhead; 4) very small test cycle overhead for
Total test cycles 1657208 reconfiguration; and 5) support of pre-bond, post-bond and TSV
Percentage (%) 99.99 0.01 testing.
ACKNOWLEDGEMENT
We also estimate the reconfiguration overhead if the
This work was partially supported by the Ministry of Science and
architecture uses SIB (Segment Insertion Bit, [2]) bypasses
Technology of Taiwan under contracts 104-2811-E-006-036 and 102-
instead of the central Scan Path Control unit per die. Table 6 2221-E-006-270-MY3, and by the German Research Foundation (DFG)
compares reconfiguration overhead in cycles of the SIB-based under grant WU 245/17-1 (ACCESS).
and the proposed Scan Path Control unit based architectures. The
overhead of the SIB-based architecture is 35 times larger than in REFERENCES
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