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microprocessorMock test

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2 views

microprocessorMock test

Uploaded by

Subho Das
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Microprocessor -8085 Test

Answer Any 5 Questions


FM. 40 Time 2 hours
8X5=40
Q-1
With the help of neat diagram explain the architecture of 8085 microprocessor in
detail. Discuss its flag register.
Q-2
Explain the sequence of events during the execution of the CALL instruction by
8085 processor with the help of neat timing diagram.
Q-3
Explain the sequence of events during the execution of the RET instruction by
8085 processor with the help of neat timing diagram.
Q-4
Write an assembly language program with comment lines. An 8-bit number is
stored in memory location C100H. Count number of ones (i.e. 1) in this byte and
store this count in memory location C200H.
Q-5
Write an assembly language program with comment lines. An array of bytes is
stored starting from memory location C301H. Length of this array is stored in
memory location. C300H. Count how many bytes are greater than 70H. Store
this count in memory location C400H.
Q-6
Write an assembly language program with comment lines. An array of bytes is
stored starting from memory location C501H. Length of this array is stored in
memory location C500H. If 1st and 8th bit of the byte is one then store that byte
in memory location starting from C600 onwards without affecting bytes of source
array.
Q-7
Explain the following instructions with suitable example of each (Any five)
(i) LXI (ii) MOV (iii) SHLD (iv) LDAX (v) CMP (vi) STA
Q-8 Explain arithmetic and logical instruction of 8085 microprocessor in detail.
Q-9
Specify the contents of the registers and the flag status as the following
instructions are executed.
i. MVI A, 00H
ii. MVI B, F8H
iii. MOV C, A
iv. MOV D, B
v. HLT
(b) Write instructions to load the hexadecimal number 65H in register C and 92H
in accumulator A. Display the number 65H at PORT0 and 92H at PORT1.
Q-10
Why the lower order address bus is multiplexed with data bus? How they will be
de-multiplexed? With the help of figure explain demultiplexing of address/data
bus

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