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Lab - Report (Control Hazard and Data Hazards)

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3 views3 pages

Lab - Report (Control Hazard and Data Hazards)

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shahzadktk133
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© © All Rights Reserved
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Name: Shahzad Akhter

Lab # pipelined processor (Data Hazards and Control Hazards)

In this report, we detail the design and implementation of a pipelined processor,


focusing on the management of data hazards and control hazards to optimize
performance. Data hazards arise when instructions that are close together in the
pipeline depend on each other's data. To mitigate these, we implemented
techniques such as data forwarding and stall cycles, allowing the processor to
retrieve the most recent data without significant delays. Control hazards, which
occur due to branch instructions, were addressed using branch prediction
mechanisms and delayed branching strategies to enhance instruction flow and
minimize pipeline stalls. Together, these hazard control techniques ensure a more
efficient execution of instructions, maximizing throughput and maintaining the
integrity of the processing pipeline.

Test instructions:
main: addi x2, x0, 5 # x2 = 5
addi x3, x0, 12 # x3 = 12
addi x7, x3, -9 # x7 = (12 - 9) = 3
or x4, x7, x2 # x4 = (3 OR 5) = 7
xor x5, x3, x4 # x5 = (12 XOR 7) = 11
add x5, x5, x4 # x5 = (11 + 7) = 18
beq x5, x7, end # shouldn't be taken
slt x4, x3, x4 # x4 = (12 < 7) = 0
beq x4, x0, around # should be taken
addi x5, x0, 0 # shouldn't happen
around: slt x4, x7, x2 # x4 = (3 < 5) = 1
add x7, x4, x5 # x7 = (1 + 18) = 19
sub x7, x7, x2 # x7 = (19 - 5) = 14
sw x7, 84(x3) # [96] = 14
lw x2, 96(x0) # x2 = [96] = 14
add x9, x2, x5 # x9 = (14 + 18) = 32
jal x3, end # jump to end, x3 = 0x44
addi x2, x0, 1 # shouldn't happen
end: add x2, x2, x9 # x2 = (14 + 32) = 46
addi x4, x0, 1 # x4 = 1
lui x5, 0x80000 # x5 = 0x80000000
slt x6, x5, x4 # x6 = 1
wrong: beq x6, x0, wrong # shouldn’t be taken
lui x9, 0xABCDE # x3 = 0xABCDE000
add x2, x2, x9 # x2 = 0xABCDE02E
sw x2, 0x40(x3) # mem[33] = 0xABCDE02E
done: beq x2, x2, done # infinite loop
Output:

Regfile:

Data memory:

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