VLSI-Latest Titles

S.No Project Code Project Name Objective

Testing New title for UG

1 TVMABE242 New Title UG

Operates at 1 MS/s sampling rate

A low-power 8 bit 1MSper s single-ended SAR Achieves low power consumption
2 TVMABE273 ADC in 130-nm CMOS for medical devices Utilizes 130-nm CMOS technology
(Back End Domains / Low Power VLSI) Is suitable for medical device
applications

Explore the usage of fast carry

Exploring the Usage of Fast Carry Chains to
chains for implementing multistage
Implement Multistage Ring Oscillators on
3 TVMAFE634 ring oscillators on FPGAs
FPGAs: Design and Characterization
Design and characterize these
(Front End Domains / Communications)
oscillators

Design and performance analysis of 8-bit ALU

for Nano- Processor design for low area, Low
Operates efficiently with low power
4 TVMABE268 power and minimum delay using 32nm CMOS
consumption
technology
(Back End Domains / Low Power VLSI)

The main objective appears to be

designing a RISC (Reduced
Instruction Set Computing)
microprocessor CPU that
Risc processer with Fft are architeture
5 TVMAFE633 incorporates Fast Fourier Transform
(Front End Domains / FPGA)
(FFT) capabilities. This design aims
to address the specific needs of
digital signal processing
applications.

The main objective appears to be

designing and implementing a
low-power cryptographic chip for
Low Power Crypto-chip design for IoT
Internet of Things (IoT) applications.
6 TVMAFE632 applications
Specifically, the focus is on creating
(Front End Domains / Communications)
a low-power RISC-V processor with
integrated cryptographic
acceleration for IoT devices.

The main objective appears to be

designing and verifying a
Design and Verification of a High-Performance high-performance RISC-V
RISC-V SOC with SPI Protocol at IP-Level for System-on-Chip (SoC) with a Serial
7 TVMAFE631
Deep Learning in Medical Imaging Peripheral Interface (SPI) protocol
(Front End Domains / Arithmetic Core) implemented at the IP level,
specifically for deep learning
applications in medical imaging

The main objective appears to be

developing a novel method for
Artificial intelligence techniques for encrypt
image encryption and decryption
images based on the chaotic system
8 TVMAFE630 using artificial neural network
implemented on field-programmable gate array
(ANN)-based chua chaotic system
(Front End Domains / FPGA)
(CCS) implemented on
field-programmable gate arrays

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VLSI-Latest Titles

S.No Project Code Project Name Objective

(FPGAs)

To design a secure image

encryption and decryption system
using reversible logic gates in VLSI
Secure Visual Data Processing: Image
design. The paper aims to address
Encryption and Decryption through Reversible
9 TVMAFE625 challenges like high area and power
Logic Gates in VLSI Design
requirements in cryptography
(Front End Domains / FPGA)
systems by optimizing for low power
consumption while maintaining high
security standards.

The primary objective appears to be

Design of Low Dropout Regulator for Power
designing and optimizing a low
Management Unit of Wearable Healthcare
dropout (LDO) regulator for use in
10 TVMABE263 System Device using 45nm CMOS
the power management unit of a
Technology
wearable healthcare system device,
(Back End Domains / Cadence EDA)
utilizing 45nm CMOS technology

The primary objective appears to be

Design of Low Dropout Regulator for Power
designing and optimizing a low
Management Unit of Wearable Healthcare
dropout (LDO) regulator for use in
11 TVMABE264 System Device using 45nm CMOS
the power management unit of a
Technology
wearable healthcare system device,
(Back End Domains / Low Power VLSI)
utilizing 45nm CMOS technology

The main objective appears to be

Energy Efficient Compact Approximate designing an energy-efficient,
12 TVMAFE623 Multiplier for Error-Resilient Applications compact approximate multiplier
(Front End Domains / Communications) suitable for error-resilient
applications

By creating an energy-efficient,
compact approximate multiplier with
error resilience, this work aims to
contribute to the development of
Energy Efficient Compact Approximate more sustainable and adaptable
13 TVMAFE618 Multiplier for Error-Resilient Applications digital systems. This design could
(Front End Domains / Arithmetic Core) enable the widespread adoption of
edge computing and IoT devices in
various applications where precise
arithmetic is not always necessary
but energy efficiency is paramount.

aims to contribute significantly to the

development of novel digital logic
Realization of Complete Boolean Logic and
technologies. This work could pave
Combinational Logic Functionalities on a
14 TVMABE260 the way for more flexible,
Memristor-Based Universal Logic Circuit
energy-efficient, and compact digital
(Back End Domains / Low Power VLSI)
systems in various fields of
electronics and computing.

HYBRID FULL ADDER CIRCUIT UTILIZING The primary goal is to reduce power
PASS TRANSISTOR AND PFAL ADIABATIC consumption in digital circuits. This
15 TVMABE256
LOGIC STYLE is achieved through the use of
(Back End Domains / Low Power VLSI) adiabatic logic, which allows for

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VLSI-Latest Titles

S.No Project Code Project Name Objective

energy-efficient operation.

• Adiabatic logic is designed to

minimize power dissipation by
gradually changing signal levels
over time. • This approach helps
reduce switching losses and overall
power consumption.

Single Ring-Oscillator-Based Test

Structure
The primary goal is to create a
single ring oscillator-based test
A Single Ring-Oscillator-Based Test Structure
16 TVMABE252 structure specifically designed for
for Timing Characterization of Dynamic Circuit
timing characterization of dynamic
circuits. This approach aims to
simplify the testing process while
maintaining accuracy.

The primary goal is to create a

16-Bit Carry Look-Ahead Adder: Design and 16-bit carry look-ahead adder, which
17 TVMABE251 Layout with Cadence Tools Top of Form is a type of high-speed digital adder
(Back End Domains / Transistor Logic) architecture. This design aims to
achieve fast addition operations.

Lightweight Encryption
The primary goal is to create an
image encryption algorithm that is
computationally inexpensive and
requires minimal resources. This is
crucial for applications running on
A Lightweight Image Encryption Algorithm devices with limited processing
18 TVPGOT07 Based on Secure Key Generation power or memory.
(Others / Matlab Interfacing)
Secure Key Generation
The research focuses on developing
a robust method for generating
secure keys. This is essential for
maintaining the security of the
encrypted images over time

Decoder Reduction
The core idea is to reduce the
complexity of the decoder stage in
Decoder Reduction Approximation Scheme for
Booth multipliers. This is typically
19 TVMAFE615 Booth Multipliers
the most computationally intensive
(Front End Domains / Testing)
part of the multiplier, responsible for
determining the sign and magnitude
of each partial product.

Given the nature of LFSRs in

Analysis of an Efficient Fault Tolerant Linear cryptographic systems, the research
Feedback Shift Register for Low Power may aim to maintain or enhance the
20 TVPGFE338
Applications security properties of the register
(Front End Domains / Arithmetic Core) while improving its reliability and
power efficiency.

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VLSI-Latest Titles

S.No Project Code Project Name Objective

This research paper likely presents

a detailed analysis of the proposed
fault-tolerant LFSR design, including
circuit-level implementations,
simulation results, and potential
applications in fields such as
cryptography, random number
generation, or secure
communication protocols where
reliable and efficient sequence
generation is crucial.

Given the nature of LFSRs in

cryptographic systems, the research
may aim to maintain or enhance the
security properties of the register
while improving its reliability and
power efficiency.
Analysis of an Efficient Fault Tolerant Linear
This research paper likely presents
Feedback Shift Register for Low Power
a detailed analysis of the proposed
21 TVPGFE339 Applications
fault-tolerant LFSR design, including
(Front End Domains / Communications and
circuit-level implementations,
Crypto Core)
simulation results, and potential
applications in fields such as
cryptography, random number
generation, or secure
communication protocols where
reliable and efficient sequence
generation is crucial.

This research paper likely presents

a detailed analysis of the proposed
input grouping and sharing
methods, including comparisons
A New Input Grouping and Sharing Method to with existing approaches,
22 TVMAFE609 Design Low Complexity FFT Implementation performance benchmarks, and
(Front End Domains / Finite State Machines) potential applications such as digital
signal processing, image
processing, or wireless
communication systems where FFT
algorithms are commonly used.

This research paper likely presents

a detailed analysis of the proposed
input grouping and sharing
methods, including comparisons
A New Input Grouping and Sharing Method to with existing approaches,
23 TVMAFE610 Design Low Complexity FFT Implementation performance benchmarks, and
(Front End Domains / FPGA) potential applications such as digital
signal processing, image
processing, or wireless
communication systems where FFT
algorithms are commonly used.

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VLSI-Latest Titles

S.No Project Code Project Name Objective

This research paper likely presents

a detailed analysis of the proposed
input grouping and sharing
methods, including comparisons
A New Input Grouping and Sharing Method to with existing approaches,
24 TVMAFE611 Design Low Complexity FFT Implementation performance benchmarks, and
(Front End Domains / DSP Core) potential applications such as digital
signal processing, image
processing, or wireless
communication systems where FFT
algorithms are commonly used.

This research paper likely presents

a detailed analysis of the proposed
input grouping and sharing
methods, including comparisons
A New Input Grouping and Sharing Method to with existing approaches,
25 TVMAFE612 Design Low Complexity FFT Implementation performance benchmarks, and
(Front End Domains / Arithmetic Core) potential applications such as digital
signal processing, image
processing, or wireless
communication systems where FFT
algorithms are commonly used.

This research paper likely presents

a detailed analysis of the proposed
input grouping and sharing
methods, including comparisons
A New Input Grouping and Sharing Method to with existing approaches,
26 TVMAFE613 Design Low Complexity FFT Implementation performance benchmarks, and
(Front End Domains / Testing) potential applications such as digital
signal processing, image
processing, or wireless
communication systems where FFT
algorithms are commonly used.

This research paper likely presents

a detailed analysis of the FPGA
implementation process, including
circuit design, performance
A Low Cost FPGA Implementation of Retinex benchmarks, and comparisons with
Based Low-Light Image Enhancement software implementations of the
27 TVPGOT06
Algorithm Retinex algorithm. It may also
(Others / Matlab Interfacing) discuss potential applications such
as surveillance systems, mobile
phone cameras, or medical imaging
equipment where low-light image
enhancement is crucial.

The main goal seems to be

Analysis of an Efficient Fault Tolerant Linear designing an efficient fault-tolerant
Feedback Shift Register for Low Power LFSR that is suitable for low-power
28 TVMAFE608
Applications applications. This involves
(Front End Domains / FPGA) addressing both fault tolerance and
power efficiency simultaneously.

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VLSI-Latest Titles

S.No Project Code Project Name Objective

The primary objective of this hybrid

full adder circuit using XOR,
multiplexer, pass transistor logic,
The hybrid full adder following circuit XOR gate
and PFAL is to create a low-power,
and 2:1 multiplexer using pass transistor along
high-speed, and area-efficient
29 TVPGBE169 with PFAL adiabatic logic style and 32-bit
arithmetic unit that can be extended
adders
to build 32-bit adders, suitable for
(Back End Domains / Transistor Logic)
modern digital circuits with strict
power and performance
requirements.

To create a low-power master-slave

DESIGN AND ANALYSIS OF LOW-POWER flip-flop design that minimizes power
AND AREA EFFICIENT MASTER-SLAVE consumption while maintaining
30 TVMABE246
FLIP-FLOP acceptable performance
(Back End Domains / Transistor Logic) characteristics.

This work compares eight different

dynamic and static memory cell
A Benchmark of Cryo CMOS Embedded designs, embedded in identical
31 TVMABE241 SRAM DRAMs in 40 nm CMOS memory architectures in a
(Back End Domains / Core Memories) nanometer CMOS process typically
adopted for QC cryo-CMOS
interfaces

Design and performance analysis of 4-bit ALU

for Nano- Processor design for low area, Low
Operates efficiently with low power
32 TVMABE267 power and minimum delay using 32nm CMOS
consumption
technology
(Back End Domains / Low Power VLSI)

The primary objective of this design

is to create an efficient digital circuit
that performs multiplication
Design and Verification of 8X8 Wallace Tree operations on two 8-bit binary
33 TVMABE266 Multiplier numbers using the Wallace Tree
(Back End Domains / Low Power VLSI) algorithm 5. This multiplier is
designed to be faster and more
area-efficient compared to
traditional methods of multiplication.

Power efficiency: Reversible logic

32-BIT FPGA BASED ALU EMPLOYING
can help reduce power consumption
34 TVMAFE627 REVERSIBLE LOGIC
by allowing for easier energy
(Front End Domains / Arithmetic Core)
recovery

Design and Implementation of a low power The primary objective appears to be

high speed full adder cell for low power designing and implementing a low
35 TVMABE265
applications power, high speed full adder cell
(Back End Domains / Low Power VLSI) optimized for low power applications

Design and Study the Performance of a CMOS-Based Ring Oscillator

CMOS-Based Ring Oscillator Architecture for Design
36 TVMABE255
5G Mobile Communication The primary goal is to design a ring
(Back End Domains / Transistor Logic) oscillator architecture using

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VLSI-Latest Titles

S.No Project Code Project Name Objective

complementary
metal-oxide-semiconductor (CMOS)
technology. This choice of
technology is crucial for 5G
applications due to its scalability and
low power consumption.

The focus on BCD arithmetic makes

Design of High Speed BCD Adder Using
this design particularly relevant for
37 TVMABE259 CMOS Technology
applications dealing with decimal
(Back End Domains / Low Power VLSI)
numbers and financial calculations.

The primary goal seems to be

creating a comparator circuit that
Cascode Cross-Coupled Stage High-Speed operates at very high speeds, likely
38 TVMABE248 Dynamic Comparator in 65 nm CMOS for use in high-frequency
(Back End Domains / Transistor Logic) applications such as
analog-to-digital converters (ADCs)
or other signal processing systems.

This paper explains an application

Encryption and Decryption using optimized
of reconfigurable logic, Encryption of
39 TVMA01 Reconfigurable Reversible Gate
data, Decryption of the same data
(Front End Domains / Communications)
implemented using Verilog coding.

Analysis of Low-Delay in 64-bit Vedic multiplier The main objective of this project is
40 TVMAFE569 based MAC unit to implement MAC unit using vedic
(Front End Domains / Arithmetic Core) multiplier.

In this work an energy efficient

square rooter by using reversible
FUNDAMENTAL DIGITAL MODULE
logic. (RCSM) Reversible Controlled
REALIZATION USING RTL DESIGN FOR
41 TVMATO1148 Subtract Multiplexer is proposed
QUANTUM MECHANICS
which also plays an important part in
(Tools / Xilinx Vivado)
implementing the binary square
rooter.

Design & Verification of AMBA AHB-Lite The main aim of this project is to
42 TVMATO1150 Memory Controller implement AMBA-3AHB lite to
(Tools / Xilinx Vivado) perform read/write operations

This work proposes architectural

Architectural Exploration for Energy-Efficient
solutions for LMS and NLMS
43 TVMAFE586 LMS and NLMS Adaptive Filters VLSI Design
algorithms targeting an
(Front End Domains / DSP Core)
energy-efficient VLSI design.

A Real-Time Object Detection Processor With In this article, we propose an

XNOR-Based Variable-Precision Computing algorithm-hardware co-optimization
44 TVMAOT08
Unit approach to designing a real-time
(Others / Matlab Interfacing) object detection system.

High-Speed Counter With Novel LFSR State The main objective of this project is
45 TVMAFE571 Extension to implement 64-bit counter based
(Front End Domains / Arithmetic Core) on LFSR

46 TVMAFE578 FPGA Implementation of Associative In this brief, we proposed a novel

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VLSI-Latest Titles

S.No Project Code Project Name Objective

FPGA implementation of the AP,

including the CAM and its peripheral
circuits, such as the controller, data
Processors
cache, instruction cache, and
(Front End Domains / DSP Core)
program counter. The design details
of the whole AP architecture are
described by Verilog HDL.

Scalable Low-Cost Sorting Network with The main aim of this work is to
47 TVMAFE572 Weighted Bit-Streams implement new sorting algorithm in
(Front End Domains / Communications) order to reduce area.

Area Reduction AES Algorithm in Hardware The main objective of this project is
48 TVMAFE567 Trojan Detection to implement AES using Trojan
(Front End Domains / Communications) Detection approach

Module Implementation and Simulation of

The main objective of this paper is
Timing Constraint Check Function of I2C
49 TVMAFE568 to implement I2C protocol to
Protocol Using Verilog
perform read/write operations
(Front End Domains / Communications)

The main objective of this project is

An Energy Efficient High Performance CMOS
50 TVMI106 to design the full adder using
Transmission Gate Full Adder Circuit
transmission gate logic

This work presents an

energy-efficient and cost-effective
Towards Energy Efficient Cost Effective Toffoli
51 TVMI108 QCA design of a 3X3 Toffoli gate
Gate Design using Quantum Cellular Automata
which utilizes the Layered T (LT)
logic reduction technique.

The main objective of this project is

Truncated Booth Multiplier Design Of
to implement 16-bit booth multiplier
52 TVMAFE574 Approximate Compressors Using Verilog Hdl
using radix-256 in order to improvise
(Front End Domains / Arithmetic Core)
performance.

Design of Advanced Encryption Standard using The main objective of this AES is to
53 TVMATO1153 Verilog HDL encrypt the data with highly secured
(Tools / Xilinx Vivado) transmission of data.

This study presents an efficient

An Efficient Implementation of the Novel Data implementation of the Novel Data
Encryption Standard (DES) Algorithm with Encryption Standard (DES)
54 TVMAFE577 Improved Key Generation Method Compared algorithm with an improved key
with Viterbi Decoder generation method and the result is
(Front End Domains / Communications) compared with the Viterbi decoder
algorithm.

In this research paper, a novel

Efficient Novel Binary to Gray Code Converter
design for a Binary to gray code
55 TVMI110 Using Coulombic Interaction on Quantum Dot
converter using QCA technology is
Cellular Automata
presented.

Area-Efficient LFSR-Based Stochastic Number The main objective of this project is

56 TVMAFE580 Generators with Minimum Correlation to reduce the size of SNGs,
(Front End Domains / Communications) we propose a new design approach

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VLSI-Latest Titles

S.No Project Code Project Name Objective

that shares a combination of

the permutations and negations of
one LFSR’s output for several
SNGs.

The main objective of this project is

Integration of SPI with AXI Protocol
57 TVMAFE581 to integrate the SPI protocol using
(Front End Domains / Communications)
AXI

The purpose of this paper is to

LOW POWER DESIGN OF SPI AND I2C provide a full description of a
58 TVMAFE582 PROTOCOL IN VERILOG HDL high-speed SPI Master/Slave
(Front End Domains / Communications) implementation with clock gating
technology.

The main objective of this project is

Integration of I2C with AXI Protocol
59 TVMAFE583 to integrate the I2C protocol using
(Front End Domains / Communications)
AXI.

A PROVABLY SECURE STRONG PUF The main objective of this project is

BASED ON LWE:CONSTRUCTION AND to implement strong LFSR based
60 TVMATO1155
IMPLEMENTATION PUF which provides high security to
(Tools / Xilinx Vivado) system hardware.

This paper focuses on the

Implementation of Delayed LMS algorithm
implementation of Delayed Least
61 TVMAFE584 based Adaptive filter using Verilog HDL
Mean Square algorithm based
(Front End Domains / DSP Core)
Adaptive filter in Verilog HDL.

In this work, we introduce

AxPPA Approximate Parallel Prefix Adders approximate PPAs (AxPPAs) by
62 TVMAFE585
(Front End Domains / Arithmetic Core) exploiting approximations in the
POs.

This paper compares three different

techniques: the clocked FBB
Robust Body Biasing Techniques for Dynamic
(CFBB) proposed, an improvement
63 TVMABE230 Comparators
of CFBB and a new hybrid approach
(Back End Domains / Transistor Logic)
that achieves the best performance
in terms of delay.

In this brief, the offset canceling

High-Precision and Low-Power Offset
tri-state sensing latch (OCTSL) is
Canceling Tri-State Sensing Latch in NAND
64 TVMABE232 proposed that achieves
Flash Memory
high-precision and low-power read
(Back End Domains / Low Power VLSI)
operation.

The research investigates various

power reduction techniques,
Design and Implementation of BIST
including test pattern compression,
Architecture for low power VLSI Applications
65 TVMAFE587 selective clock gating, and
using Verilog
power-aware test scheduling, to
(Front End Domains / Testing)
optimize power consumption during
testing.

66 TVMAFE588 Design of a VLSI Router for the Faster Data This paper proposes a modified

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VLSI-Latest Titles

S.No Project Code Project Name Objective

VLSI-based router
Transmission Using Buffer architecture that is optimized for
(Front End Domains / Communications) high-speed data transfer and low
power consumption.

In this paper, we present a new LO

High Performance VLSI Architecture of FIR and LD minimization matrix
67 TVMAFE589 Filter for Seismic Signal Processing grouped CSE algorithm that
(Front End Domains / DSP Core) outperforms existing CSE
algorithms.

For
high mathematical complexity
applications, approximate
Implementation of Area Efficient Adders for
adders are proposed as a feasible
68 TVMAFE590 Inexact Computing
solution in this paper, which can
(Front End Domains / Arithmetic Core)
give a better trade-off with accuracy
in terms of energy consumed, area
occupied and delay

This paper focuses on building

cryptographic systems using a
VLSI ARCHITECTURES FOR SECURITY scrambler circuit constructed using
ANALYSIS WITH DUAL-KEY LFSR USING reversible logic gates, S-Box, a
69 TVMAFE591
BARREL SHIFTER AND S-BOX barrel shifter, and an LFSR that
(Front End Domains / Communications) generates a 4-bit random key which
is then used as a dual key for XOR
and a barrel shifter.

By using the Wallace Tree

VLSI Design of Majority Logic based Wallace multipliers architecture and
70 TVMAFE592 Tree Multiplier improving the adder in each Wallace
(Front End Domains / Arithmetic Core) Tree phase, reduce the unnecessary
latency.

VLSI Synthesis of Multiply and Accumulate This paper shows how the
71 TVMAFE593 Structures Using Distributed Arithmetic parameter of inputs in the data path
(Front End Domains / Arithmetic Core) affects different MAC cores.

The proposed study aims to provide

Realization of High Performance Approximate
a 64-bit approximation multiplier
72 TVMAFE594 Multipliers for FPGA Application
with high throughput and low latency
(Front End Domains / DSP Core)
for cutting-edge DSP applications.

In this work, two current generator

A Rail-to-Rail Transconductance Amplifier circuits are configured based
73 TVMABE235 Based on Current Generator Circuits on n-channel and p-channel
(Back End Domains / Transistor Logic) cascode current mirrors to achieve
a self-biasing topology.

Analysis and Measurements of an Urea In this study, a cross-coupling

Biosensor Based on Instrumentation Amplifier technique was applied to improve
74 TVMABE237
Chip With Cross-Coupled Technique the characteristics of the two-stage
(Back End Domains / Transistor Logic) amplifier.

75 TVMAFE595 Area Efficient Approximate 4-2 Compressor In this brief, we have presented a

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VLSI-Latest Titles

S.No Project Code Project Name Objective

novel area efficient 4-2 compressor

and a brand-new hybrid combination
and Probability-Based Error Adjustment for
method of probabilistic adjustment
Approximate Multiplier
employing approximate
(Front End Domains / Arithmetic Core)
compressors for approximate
multiplier.

This proposes a new multiplier

architecture based on the algorithm
CAAM: Compressor-Based Adaptive
that adapts the approximate
Approximate Multiplier for Neural Network
76 TVMAFE596 compressor from the existing and
Applications
proposed compressors’ set to
(Front End Domains / DSP Core)
reduce error in the respective partial
product columns.

To solve this cost problem, in this

Efficient Approximate Posit Multipliers for Deep
paper, posit multipliers with
77 TVMAFE597 Learning Computation
approximate computing features are
(Front End Domains / Communications)
proposed.

Low Complexity Implementation of OTFS

The main aim of this project is to
Transmitter using Fully Parallel and Pipelined
78 TVMAFE600 design the OTFS for higher
Hardware Architecture
performance.
(Front End Domains / DSP Core)

This paper will fully understand the

structure and principle of UART,
Design And Implementation of UART Based on function and implementation on the
79 TVMAFE601 Verilog HDL basis of the use of Verilog HDL
(Front End Domains / Communications) language, by describing its function,
to achieve the construction of
UART.

An Ultra-Efficient Approximate Multiplier With

The main objective of this project is
Error Compensation for Error-Resilient
80 TVMAFE602 to present an energy efficient
Applications
approximate multiplier.
(Front End Domains / Arithmetic Core)

This work presenting a simple, yet

A Lightweight True Random Number Generator
effective, all-digital lightweight and
81 TVMAFE603 for Root of Trust Applications
self-testable random number
(Front End Domains / Arithmetic Core)
generator to produce a nonce.

In this letter, we focus on the

Design of Implicit Partial Product-LDPC Codes above-mentioned implicit partial
82 TVMAFE604 and Low Complexity Decoding Algorithm product low-density parity-check
(Front End Domains / Testing) (IP-LDPC) codes and discuss their
constructions in details.

A novel approximate computing

Design of Approximate Bilateral Filters for strategy is introduced to reduce the
83 TVMAFE605 Image Denoising on FPGAs computational complexity of the
(Front End Domains / DSP Core) image denoising operation and to
comply with real time requirements.

84 TVMABE231 Overview on Latch-Up Prevention in CMOS An overview on circuit methodology

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VLSI-Latest Titles

S.No Project Code Project Name Objective

used to prevent latch-up issues in

Integrated Circuits by Circuit Solutions
CMOS integrated circuits (ICs) is
(Back End Domains / Transistor Logic)
presented in this article.

This brief presents a novel sensing

A Low-Complexity Sensing Scheme for approach for approximate matching
Approximate Matching Content-Addressable content-addressable memory (CAM)
85 TVMABE236
Memory designed to handle large Hamming
(Back End Domains / Core Memories) distances (HDs) between the query
pattern and stored data.

In this article, a new hardware

Scan Chain Architecture With Data Duplication architecture with data duplication is
86 TVPGBE165 for Multiple Scan Cell Fault Diagnosis proposed to diagnose fault locations
(Back End Domains / Transistor Logic) by deliberate voltage collision even
if multiple faults occur.

To protect filter coefficients from an

adversary, efficient obfuscation
Hybrid Protection of Digital FIR Filters techniques have been proposed,
87 TVPGTO936
(Tools / Xilinx Vivado) either by hiding them behind decoys
or
replacing them by key bits.

This work presents two novel

Design of Optimal Multiplierless FIR Filters
methods that simultaneously
88 TVPGFE336 With Minimal Number of Adders
optimize both the design of a finite
(Front End Domains / DSP Core)
impulse response (FIR) filter.

Low power Dadda multiplier using approximate

In this work, we proposed a very
almost full adder and Majority logic based
89 TVPGFE335 novel design approaches based on
adder compressors
various monolithic 4:2 compressors.
(Front End Domains / Arithmetic Core)

High-performance multiply-accumulate unit by The main objective of this project is

integrating binary carry select adder and to design MAC unit in order to
90 TVPGFE334 counter-based modular wallace tree multiplier achieve lower power consumption
for embedding system on utilizing the high-speed binary
(Front End Domains / Arithmetic Core) carry select adder.

The paper seeks to develop

Two Efficient Approximate Unsigned Multipliers
approximate compressors that align
by Developing New Configuration for
91 TVPGFE333 positive and negative
Approximate 4:2 Compressors
approximations for input patterns
(Front End Domains / DSP Core)
that have the same probability.

To balance the generated errors for

enlarging the range of
Simplified Compressor and Encoder Designs
approximation, we force two
for Low-Cost Approximate Radix-4 Booth
92 TVPGFE332 simplified operations to have
Multiplier
different error directions while
(Front End Domains / Arithmetic Core)
minimizing their hardware costs with
aggressive unit-gate architectures.

Implementation of a Multipath Fully Differential In this brief, two FVF cells are used
93 TVPGBE160
OTA in 0.18-um CMOS Process as two nonlinear tail current

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VLSI-Latest Titles

S.No Project Code Project Name Objective

sources with the capability of

increasing the dynamic currents
(Back End Domains / Transistor Logic) under
large-signal operation, causing a
high SR performance.

In this work, we propose a novel

DFT-compatible EDAC structure and
A DFT-Compatible In-Situ Timing Error
corresponding test methods with
Detection and Correction Structure Featuring
94 TVPGBE159 signal control simplification and
Low Area and Test Overhead
pattern-generation complexity
(Back End Domains / Transistor Logic)
reduction to achieve a low area
overhead and test complexity.

In this paper, a high-speed

CMOS Clock-Gated Synchronous Up-Down low-power CMOS synchronous
Counter With High-Speed Local Clock up/down counter with a novel
95 TVPGBE158
Generation and Compact Toggle Flip-Flop compact toggle flipflop is proposed
(Back End Domains / Transistor Logic) to achieve energy- and
area-efficient speed enhancement

A DIFFERENTIAL FLIP-FLOP WITH STATIC

A static contention-free differential
CONTENTION-FREE CHARACTERISTICS IN
flip-flop (SCDFF) is presented in
96 TVPGBE157 28 NM FOR LOW-VOLTAGE, LOW-POWER
28-nm CMOS for low-voltage and
APPLICATIONS
low-power applications.
(Back End Domains / Low Power VLSI)

In this brief, a local bit-line (LBL)

Local Bit-Line SRAM Architecture With SRAM with data-aware
97 TVPGBE156 Data-Aware Power-Gating Write Assist power-gating write assist is
(Back End Domains / Low Power VLSI) proposed for near-threshold
operation.

This work goes to test various

Comparative Analysis of Phase & Frequency different phase/frequency detector
98 TVPGTO935 Detector in a Complete PLL System blocks with a standard charge pump
(Tools / Cadence EDA) and Voltage controlled oscillator
design.

The proposed SE10T improves read

stability and write stability with the
help of a built-in read-assist scheme
Energy-Efficient Single-Ended Read Write 10T and a power-gating technique,
99 TVPGBE155 Near Threshold SRAM respectively, and reduces
(Back End Domains / Core Memories) power/energy consumption by using
single-ended read/write operation
and stacking of transistors in the cell
core.

In this research, we suggest

FPGA-Supported HDL Approach to Implement adopting reversible logic gates
100 TVPGFE331 Reversible Logic Gate-Based ALU rather than conventional gates to
(Front End Domains / Arithmetic Core) design and synthesize a 16-bit
reversible ALU

101 TVPGFE329 VLSI Design of Pipelined FFT Architecture for The main objective of this paper is

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VLSI-Latest Titles

S.No Project Code Project Name Objective

DSP Application to implement single delay feedback

(Front End Domains / DSP Core) FFT.

By addressing these objectives,

researchers and engineers aim to
create robust, efficient, and reliable
VLSI implementations of error
VLSI Implementation of Error Detection and detection and correction codes
102 TVMAFE616 Correction Codes for Space Engineering specifically tailored for space
(Front End Domains / FPGA) engineering applications. This work
contributes significantly to
advancing satellite communication
systems and ensuring the reliability
of critical spacecraft operations.

The primary goal is to construct a

complete PLL that supports both
analog and digital circuits,
emphasizing its critical role in clock
A Design of 45nm Low Jitter Charge Pump generation and recovery in
PhaseLocked Loop Architecture for VHF and microprocessors, communication
103 TVPGBE166
UHF Field systems, digital networking, and
(Back End Domains / Low Power VLSI) frequency synthesizers. PLLs are
particularly important in
high-performance digital systems for
generating accurately timed on-chip
clocks

In this
FPGA implementation of high performance
technique, the basic hybrid adder is
digital FIR filter design using a hybrid adder
104 TVPGFE337 designed with the help of
and multiplier
2-bit adders, BEC and 4:1
(Front End Domains / DSP Core)
Multiplexer for high performance.

Design and Implementation of RNB multiplier The main objective of this project is
105 TVPGBE164 Using NP Domino logic to reduce the delay of RNB
(Back End Domains / Transistor Logic) multiplier using NP Domino Logic.

This paper investigates the

Design of High-Performance GDI Logic based
modelling and implementation of a
8-Tap FIR Filter at 22nm CMOS Technology
106 TVPGBE163 Finite Impulse-Response (FIR)
using Array Multiplier
block developed utilizing GDI-based
(Back End Domains / Transistor Logic)
circuits as well as basic blocks.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The primary goal seems to be

creating a resource-efficient and
high-accuracy digital implementation
A Resource-Efficient and High-Accuracy
of the Hodgkin-Huxley neuron
CORDIC-Based Digital Implementation of the
1 TVMAFE629 model on FPGA platforms 4. This
Hodgkin–Huxley Neuron
involves addressing several
(Front End Domains / FPGA)
challenges related to the complexity
of the Hodgkin-Huxley model and
the limitations of FPGA resources.

AMCAL: Approximate Multiplier With the The AMCAL (Approximate Multiplier

Configurable Accuracy Levels for Image with Configurable Accuracy Levels)
2 TVMAFE628
Processing and Convolutional Neural Network aims to perform multiplication
(Front End Domains / Arithmetic Core) operations with adjustable accuracy

The use of pass transistor logic is a

Design of Low Power Pass Transistor Logic technique aimed at reducing power
Based Adders for Multiplier in 90nm CMOS consumption in digital circuits. PTL
3 TVMABE258
Process replaces pull-up transistors with
(Back End Domains / Cadence EDA) pass transistors, which can
significantly lower power dissipation

To minimize power consumption by

optimizing the design of the
transmission gate-based full adder,
An Energy Efficient High-Performance CMOS
reducing leakage currents, and
4 TVMABE261 Transmission Gate Full Adder Circuit
achieving low switching activity. This
(Back End Domains / Low Power VLSI)
is particularly important in
battery-operated and low-power
applications.

By utilizing the non-volatile nature of

memristors, the hybrid design can
drastically reduce static power
consumption, which is a significant
High Performance and Scalable Hybrid portion of total power dissipation in
5 TVMABE244
Memristor-CMOS Based Full Adder modern CMOS circuits. This is
particularly beneficial for
battery-powered devices and
large-scale data centers where
energy efficiency is critical.

Increase Operational Speed:

High-speed operation is crucial for
modern computing applications,
including real-time processing,
High speed low power multipliers based on high-performance computing, and
6 TVMAFE607 reversible logic methods data-intensive tasks. Reversible
(Front End Domains / FPGA) logic methods can potentially offer
faster computation by minimizing
the propagation delay across logic
gates, thereby enhancing the speed
of multiplication operations.

A DC to 20 GHz Variable Gain Amplifier with The design and characterization of a

7 TVMATO1151
Tunable Input Matching in 22 nm FDSOI broadband radio-frequency

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

variable-gain baseband amplifier,

enhanced with tunable
Technology input-impedance matching and
(Tools / Cadence EDA) implemented in a 22 nm
fully-depleted silicon-on-insulator
technology is presented

The main objective of this paper is

A High CMRR Instrumentation Amplifier to design efficient Instrumentation
Employing Pseudo-Differential Inverter for Amplifier in terms of Area and power
8 TVMABE177
Neural Signal Sensing consumption. The designs of IA is
(Back End Domains / Transistor Logic) built using Psuedo differential logic
and also single ended topology.

The main objective of this paper is

A High CMRR Instrumentation Amplifier to design efficient Instrumentation
Employing Pseudo-Differential Inverter for Amplifier in terms of Area and power
9 TVMATO1010
Neural Signal Sensing consumption. The designs of IA is
(Tools / Tanner EDA) built using Psuedo differential logic
and also single ended topology.

The objective is to compute-a small

group of intermediate prefixes, then
a large group of-prefixes, and so on,
Design and Implementation of 4-bit and 8-bit
until all of the carry bits have been
10 TVPGBE142 KSA in 18nm FinFET Technology
computed. Parallel-prefix structures
(Back End Domains / Low Power VLSI)
have been discovered to appeal to
adders due to their logarithmic
latency.

The objective is to compute-a small

group of intermediate prefixes, then
a large group of-prefixes, and so on,
Design and Implementation of 4-bit and 8-bit
until all of the carry bits have been
11 TVMATO1062 KSA in 18nm FinFET Technology
computed. Parallel-prefix structures
(Tools / H-Spice)
have been discovered to appeal to
adders due to their logarithmic
latency.

The proposed design of the 4-bit

Design and Analysis of Low-Power High
PIPO shift register is designed using
Performance 4-Bit Parallel Shift Register using
TSPC flip-flop and its operation and
12 TVMABE176 Retentive True Single Phase Clocked D-Flip
performance is discussed below 1V
Flop
operating voltage to yield minimal
(Back End Domains / Low Power VLSI)
power consumption.

The proposed design of the 4-bit

Design and Analysis of Low-Power High
PIPO shift register is designed using
Performance 4-Bit Parallel Shift Register using
TSPC flip-flop and its operation and
13 TVMATO1007 Retentive True Single Phase Clocked D-Flip
performance is discussed below 1V
Flop
operating voltage to yield minimal
(Tools / Tanner EDA)
power consumption.

Design and Analysis of Low-Power High The proposed design of the 4-bit
14 TVMATO1008 Performance 4-Bit Parallel Shift Register using PIPO shift register is designed using
Retentive True Single Phase Clocked D-Flip TSPC flip-flop and its operation and

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

performance is discussed below 1V

Flop
operating voltage to yield minimal
(Tools / Cadence EDA)
power consumption.

The proposed design of the 4-bit

Design and Analysis of Low-Power High
PIPO shift register is designed using
Performance 4-Bit Parallel Shift Register using
TSPC flip-flop and its operation and
15 TVMATO1009 Retentive True Single Phase Clocked D-Flip
performance is discussed below 1V
Flop
operating voltage to yield minimal
(Tools / LT-Spice)
power consumption.

The proposed design of the 4-bit

Design and Analysis of Low-Power High
PIPO shift register is designed using
Performance 4-Bit Parallel Shift Register using
TSPC flip-flop and its operation and
16 TVPGTO844 Retentive True Single Phase Clocked D-Flip
performance is discussed below 1V
Flop
operating voltage to yield minimal
(Tools / Tanner EDA)
power consumption.

The proposed design of the 4-bit

Design and Analysis of Low-Power High
PIPO shift register is designed using
Performance 4-Bit Parallel Shift Register using
TSPC flip-flop and its operation and
17 TVPGTO845 Retentive True Single Phase Clocked D-Flip
performance is discussed below 1V
Flop
operating voltage to yield minimal
(Tools / Cadence EDA)
power consumption.

The main aim of this project is to

A Partially Static High Frequency 18T Hybrid
design master slave flip-flop using
Topological Flip-Flop Design for Low Power
18 TVPGTO899 adaptive coupling techniques with
Application
minimum number of transistors in
(Tools / Tanner EDA)
order to reduce power consumption.

The main aim of this project is to

A Partially Static High Frequency 18T Hybrid
design master slave flip-flop using
Topological Flip-Flop Design for Low Power
19 TVPGTO900 adaptive coupling techniques with
Application
minimum number of transistors in
(Tools / Cadence EDA)
order to reduce power consumption.

The main aim of this project is to

A Partially Static High Frequency 18T Hybrid
design master slave flip-flop using
Topological Flip-Flop Design for Low Power
20 TVMATO1106 adaptive coupling techniques with
Application
minimum number of transistors in
(Tools / Tanner EDA)
order to reduce power consumption.

The main aim of this project is to

A Partially Static High Frequency 18T Hybrid
design master slave flip-flop using
Topological Flip-Flop Design for Low Power
21 TVMATO1107 adaptive coupling techniques with
Application
minimum number of transistors in
(Tools / Cadence EDA)
order to reduce power consumption.

The main aim of this project is to

A Partially Static High Frequency 18T Hybrid
design master slave flip-flop using
Topological Flip-Flop Design for Low Power
22 TVMABE194 adaptive coupling techniques with
Application
minimum number of transistors in
(Back End Domains / Low Power VLSI)
order to reduce power consumption.

23 TVMABE195 A Partially Static High Frequency 18T Hybrid The main aim of this project is to

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

design master slave flip-flop using

Topological Flip-Flop Design for Low Power
adaptive coupling techniques with
Application
minimum number of transistors in
(Back End Domains / Transistor Logic)
order to reduce power consumption.

The main objective of this paper is

Design and Synthesis of a 256-Point Radix-2
to implementation of a 256-point DIT
DIT FFT Core with Design Ware Library using
24 TVPGTO878 (Decimation in Time) FFT algorithm
Fixed-Point Number Representation
with fixed-point number
(Tools / Xilinx Vivado)
representation.

The main objective of this paper is

Design and Synthesis of a 256-Point Radix-2
to implementation of a 256-point DIT
DIT FFT Core with Design Ware Library using
25 TVPGTO879 (Decimation in Time) FFT algorithm
Fixed-Point Number Representation
with fixed-point number
(Tools / Xilinx ISE)
representation.

The main objective of this paper is

Design and Synthesis of a 256-Point Radix-2
to implementation of a 256-point DIT
DIT FFT Core with Design Ware Library using
26 TVMATO1076 (Decimation in Time) FFT algorithm
Fixed-Point Number Representation
with fixed-point number
(Tools / Xilinx Vivado)
representation.

The main objective of this paper is

Design and Synthesis of a 256-Point Radix-2
to implementation of a 256-point DIT
DIT FFT Core with Design Ware Library using
27 TVMATO1077 (Decimation in Time) FFT algorithm
Fixed-Point Number Representation
with fixed-point number
(Tools / Xilinx ISE)
representation.

The main objective of this paper is

Design and Synthesis of a 256-Point Radix-2
to implementation of a 256-point DIT
DIT FFT Core with Design Ware Library using
28 TVMAFE513 (Decimation in Time) FFT algorithm
Fixed-Point Number Representation
with fixed-point number
(Front End Domains / Arithmetic Core)
representation.

The main objective of this paper is

Reversible Logic Based 1-bit Comparator using to implement the reversible logic in
29 TVMATO1084 QCA QCA technology in order to achieve
(Tools / QCA) low power consumption with fast
performance.

The main objective of this paper is

Reversible Logic Based 1-bit Comparator using to implement the reversible logic in
30 TVMAFE517 QCA QCA technology in order to achieve
(Front End Domains / Arithmetic Core) low power consumption with fast
performance.

The main objective of this paper is

EfficientDesign of Vedic Square Calculator to present an optimized architecture
31 TVMATO1087 Using Quantum Dot Cellular Automata QCA of a 2-bit square calculator using
(Tools / QCA) vedic sutra based on E-shaped
XOR gate and majority gate.

EfficientDesign of Vedic Square Calculator The main objective of this paper is

32 TVMAFE519 Using Quantum Dot Cellular Automata QCA to present an optimized architecture
(Front End Domains / Arithmetic Core) of a 2-bit square calculator using

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

vedic sutra based on E-shaped

XOR gate and majority gate.

The main objective of this paper is

Fast Supersingular Isogeny DiffieHellman and to design the
Key Encapsulation Using a Customized Pipelined Montgomery multiplier in
33 TVPGTO876
Pipelined Montgomery Multiplier order to minimize the latency of
(Tools / Xilinx Vivado) multiplier is far shorter.

The main objective of this paper is

Fast Supersingular Isogeny DiffieHellman and to design the
Key Encapsulation Using a Customized Pipelined Montgomery multiplier in
34 TVPGTO877
Pipelined Montgomery Multiplier order to minimize the latency of
(Tools / Xilinx ISE) multiplier is far shorter.

The main objective of this paper is

Fast Supersingular Isogeny DiffieHellman and to design the
Key Encapsulation Using a Customized Pipelined Montgomery multiplier in
35 TVMATO1074
Pipelined Montgomery Multiplier order to minimize the latency of
(Tools / Xilinx Vivado) multiplier is far shorter.

The main objective of this paper is

Fast Supersingular Isogeny DiffieHellman and to design the
Key Encapsulation Using a Customized Pipelined Montgomery multiplier in
36 TVMATO1075
Pipelined Montgomery Multiplier order to minimize the latency of
(Tools / Xilinx ISE) multiplier is far shorter.

The main objective of this paper is

Fast Supersingular Isogeny DiffieHellman and to design the
Key Encapsulation Using a Customized Pipelined Montgomery multiplier in
37 TVMAFE512
Pipelined Montgomery Multiplier order to minimize the latency of
(Front End Domains / Arithmetic Core) multiplier is far shorter.

For testing the VLSI design, a 32-

bit Low Power-LFSR (LP-LFSR) is
proposed in this paper. This 32-bit
FPGA Implementation of Efficient and Low
test pattern generator is built along
38 TVMAFE575 Power Test Pattern Generator
a traditional LFSR
(Front End Domains / Testing)
and additional combinational
network to achieve low power
consumption.

DESIGN AND SIMULATION OF SERIAL

The main objective of this project is
PERIPHERAL INTERFACE CORE WITH APB
39 TVMAFE573 to implement SPI by using APB
INTERFACING
protocol.
(Front End Domains / Communications)

The main objective of this project is

Efficient Design of Vedic Square Calculator
to design a coplanar QCA
40 TVMATO1152 Using Quantum Dot Cellular Automata QCA
architecture for 2-bit Square
(Tools / QCA)
calculator using Vedic mathematics.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
41 TVMAFE489 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Front End Domains / Arithmetic Core)
accuracy as per the user and to
obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
42 TVMATO969 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx Vivado)
accuracy as per the user and to
obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
43 TVMATO970 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx ISE)
accuracy as per the user and to
obtain power optimization.

The proposed design of Modified

Design of Three Stage Dynamic Comparator three stage comparator by using the
with Tail Transistor using 20nm FinFET tail transistor has been implemented
44 TVMABE173
Technology for ADCs to achieve the lower leakage power
(Back End Domains / Transistor Logic) consumption and reducing the short
channel effects.

In this project we are going to

implement the circuit functions
Design and optimization of MIMO filter using represent low pass filter (LPF), high
45 TVMATO1004 current conveyor pass filter (HPF) and band pass
(Tools / Tanner EDA) filter (BPF) function while taking
different input and output port
combinations.

In this project we are going to

implement the circuit functions
Design and optimization of MIMO filter using represent low pass filter (LPF), high
46 TVPGTO842 current conveyor pass filter (HPF) and band pass
(Tools / Tanner EDA) filter (BPF) function while taking
different input and output port
combinations.

In this paper, 3-bit encoder using

Low Power 3-Bit Encoder Design using memristors is proposed. And this
47 TVMABE181 Memristor architecture is also compared with
(Back End Domains / Core Memories) 3-bit encoder using CMOS and
PSEUDO NMOS Logic.

In this paper, 3-bit encoder using

Low Power 3-Bit Encoder Design using memristors is proposed. And this
48 TVMATO1024 Memristor architecture is also compared with
(Tools / LT-Spice) 3-bit encoder using CMOS and
PSEUDO NMOS Logic.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The proposed design of Modified

Design of Three Stage Dynamic Comparator three stage comparator by using the
with Tail Transistor using 20nm FinFET tail transistor has been implemented
49 TVMATO1058
Technology for ADCs to achieve the lower leakage power
(Tools / H-Spice) consumption and reducing the short
channel effects.

The main objective of this project is

Fully Automated Traffic Light Controller system to design the fully automated traffic
50 TVPGTO886 for a four-way intersection using Verilog light controller using clock divider for
(Tools / Xilinx Vivado) timing control and FSM for reducing
power consumption.

The main objective of this project is

Fully Automated Traffic Light Controller system to design the fully automated traffic
51 TVPGTO887 for a four-way intersection using Verilog light controller using clock divider for
(Tools / Xilinx ISE) timing control and FSM for reducing
power consumption.

The main objective of this project is

Fully Automated Traffic Light Controller system to design the fully automated traffic
52 TVMATO1085 for a four-way intersection using Verilog light controller using clock divider for
(Tools / Xilinx Vivado) timing control and FSM for reducing
power consumption.

The main objective of this project is

Fully Automated Traffic Light Controller system to design the fully automated traffic
53 TVMATO1086 for a four-way intersection using Verilog light controller using clock divider for
(Tools / Xilinx ISE) timing control and FSM for reducing
power consumption.

The main objective of this project is

Fully Automated Traffic Light Controller system to design the fully automated traffic
54 TVMAFE518 for a four-way intersection using Verilog light controller using clock divider for
(Front End Domains / Finite State Machines) timing control and FSM for reducing
power consumption.

The main objective of this project is

Approach for Implementation of Vending
to implement Vending Machine
55 TVMATO1089 Machine through Verilog HDL
using FSM in order to reduce power
(Tools / Xilinx Vivado)
consumption

The main objective of this project is

Approach for Implementation of Vending
to implement Vending Machine
56 TVMATO1090 Machine through Verilog HDL
using FSM in order to reduce power
(Tools / Xilinx ISE)
consumption

The main objective of this project is

Approach for Implementation of Vending
to implement Vending Machine
57 TVMAFE523 Machine through Verilog HDL
using FSM in order to reduce power
(Front End Domains / Finite State Machines)
consumption

Design and implementation of subway The main objective of this project is

automatic ticketing system based on Verilog to implement automatic ticketing
58 TVPGTO888
HDL system using FSM to reduce power
(Tools / Xilinx Vivado) consumption

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Design and implementation of subway The main objective of this project is

automatic ticketing system based on Verilog to implement automatic ticketing
59 TVPGTO889
HDL system using FSM to reduce power
(Tools / Xilinx ISE) consumption

Design and implementation of subway The main objective of this project is

automatic ticketing system based on Verilog to implement automatic ticketing
60 TVMAFE521
HDL system using FSM to reduce power
(Front End Domains / Finite State Machines) consumption

The main objective of this project is

Approach for Implementation of Vending
to implement Vending Machine
61 TVPGTO890 Machine through Verilog HDL
using FSM in order to reduce power
(Tools / Xilinx Vivado)
consumption

The main objective of this project is

Approach for Implementation of Vending
to implement Vending Machine
62 TVPGTO891 Machine through Verilog HDL
using FSM in order to reduce power
(Tools / Xilinx ISE)
consumption

The main objective of this paper is

Design and Performance Analysis of Various to implementation of different type of
63 TVPGTO880 32-bit Hybrid Adders using Verilog 32-bit VLSI adders will be done
(Tools / Xilinx Vivado) using differing types of combination
of adders and logic.

The main objective of this paper is

Design and Performance Analysis of Various to implementation of different type of
64 TVPGTO881 32-bit Hybrid Adders using Verilog 32-bit VLSI adders will be done
(Tools / Xilinx ISE) using differing types of combination
of adders and logic.

The main objective of this paper is

Design and Performance Analysis of Various to implementation of different type of
65 TVMATO1078 32-bit Hybrid Adders using Verilog 32-bit VLSI adders will be done
(Tools / Xilinx Vivado) using differing types of combination
of adders and logic.

The main objective of this paper is

Design and Performance Analysis of Various to implementation of different type of
66 TVMATO1079 32-bit Hybrid Adders using Verilog 32-bit VLSI adders will be done
(Tools / Xilinx ISE) using differing types of combination
of adders and logic.

The main objective of this paper is

Design and Performance Analysis of Various to implementation of different type of
67 TVMAFE514 32-bit Hybrid Adders using Verilog 32-bit VLSI adders will be done
(Front End Domains / Arithmetic Core) using differing types of combination
of adders and logic.

The main objective of this paper is

to design the
A Programmable and Parameterisable
LFSR using Reseeding technique to
68 TVPGTO884 Reseeding Linear Feedback Shift Register
generate higher number of
(Tools / Xilinx Vivado)
sequences without luring the
storage requirements.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main objective of this paper is

to design the
A Programmable and Parameterisable LFSR using Reseeding technique to
69 TVPGTO885 Reseeding Linear Feedback Shift Register generate higher number of
(Tools / Xilinx ISE) sequences without luring the
storage requirements.

The main objective of this paper is

to design the
A Programmable and Parameterisable LFSR using Reseeding technique to
70 TVMAFE516 Reseeding Linear Feedback Shift Register generate higher number of
(Front End Domains / Arithmetic Core) sequences without luring the
storage requirements.

The main objective of this paper is

to design the
A Programmable and Parameterisable LFSR using Reseeding technique to
71 TVMATO1082 Reseeding Linear Feedback Shift Register generate higher number of
(Tools / Xilinx Vivado) sequences without luring the
storage requirements.

The main objective of this paper is

to design the
A Programmable and Parameterisable LFSR using Reseeding technique to
72 TVMATO1083 Reseeding Linear Feedback Shift Register generate higher number of
(Tools / Xilinx ISE) sequences without luring the
storage requirements.

The main objective of this paper is

Algorithm Level Error Detection in Low Voltage
to design a systolic array based
73 TVPGTO882 Systolic Array
multiplier to achieve significant
(Tools / Xilinx Vivado)
improvement in power efficiency.

The main objective of this paper is

Algorithm Level Error Detection in Low Voltage
to design a systolic array based
74 TVPGTO883 Systolic Array
multiplier to achieve significant
(Tools / Xilinx ISE)
improvement in power efficiency.

The main objective of this paper is

Algorithm Level Error Detection in Low Voltage
to design a systolic array based
75 TVMATO1080 Systolic Array
multiplier to achieve significant
(Tools / Xilinx Vivado)
improvement in power efficiency.

The main objective of this paper is

Algorithm Level Error Detection in Low Voltage
to design a systolic array based
76 TVMATO1081 Systolic Array
multiplier to achieve significant
(Tools / Xilinx ISE)
improvement in power efficiency.

Algorithm Level Error Detection in Low Voltage The main objective of this paper is
77 TVMAFE515
Systolic Array to design a systolic array based

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

multiplier to achieve significant

(Front End Domains / DSP Core)
improvement in power efficiency.

The main objective of this paper is

Performance Analysis of 4-Bit Multiplier using
to implement 4-bit multiplier to
78 TVMABE192 90nm Technology
reduce the power consumption by
(Back End Domains / Low Power VLSI)
using modified full adder.

The main objective of this paper is

Performance Analysis of 4-Bit Multiplier using
to implement 4-bit multiplier to
79 TVMATO1091 90nm Technology
reduce the power consumption by
(Tools / Tanner EDA)
using modified full adder.

The main objective of this paper is

Performance Analysis of 4-Bit Multiplier using
to implement 4-bit multiplier to
80 TVMATO1092 90nm Technology
reduce the power consumption by
(Tools / Cadence EDA)
using modified full adder.

The main objective of this paper is

Performance Analysis of 4-Bit Multiplier using
to implement 4-bit multiplier to
81 TVPGTO892 90nm Technology
reduce the power consumption by
(Tools / Tanner EDA)
using modified full adder.

The main objective of this paper is

Performance Analysis of 4-Bit Multiplier using
to implement 4-bit multiplier to
82 TVPGTO893 90nm Technology
reduce the power consumption by
(Tools / Cadence EDA)
using modified full adder.

Turbo code has become the coding

technique of choice in many
communication and storage
systems due to its near Shannon
Implementation of Turbo Encoder and Decoder
83 TVMAFE537 limit error correction capability. With
(Front End Domains / Arithmetic Core)
requirement on increasing data
rates for deep space mission, it is
required to have efficient encoder
and decoder.

Turbo code has become the coding

technique of choice in many
communication and storage
systems due to its near Shannon
Implementation of Turbo Encoder and Decoder
84 TVMATO1130 limit error correction capability. With
(Tools / Xilinx Vivado)
requirement on increasing data
rates for deep space mission, it is
required to have efficient encoder
and decoder.

Turbo code has become the coding

technique of choice in many
communication and storage
Implementation of Turbo Encoder and Decoder systems due to its near Shannon
85 TVMATO1131
(Tools / Xilinx ISE) limit error correction capability. With
requirement on increasing data
rates for deep space mission, it is
required to have efficient encoder

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

and decoder.

DESIGN AND IMPLEMENTATION OF LOW In this article, presenting novel

POWER VCO USING PSEUDO NMOS LOGIC design of PLL using modified VCO.
86 TVMATO1147
FOR PLL Here, the VCO block is redesigned
(Tools / Cadence EDA) using Pseudo NMOS configuration.

The main objective of this paper is

to secure the data from side channel
A Highly Secure FPGA-Based Dual-Hiding attacks by utilizing the Async-logic
Asynchronous-Logic AES Accelerator against AES with less area and low energy.
87 TVMAFE493
Side-Channel Attacks The dual rail hiding is used in
(Front End Domains / Communications) vertical SCA and ZV compensate
S-box are employed to hide the
horizontal SCA.

The main objective of this paper is

to secure the data from side channel
A Highly Secure FPGA-Based Dual-Hiding attacks by utilizing the Async-logic
Asynchronous-Logic AES Accelerator against AES with less area and low energy.
88 TVMATO975
Side-Channel Attacks The dual rail hiding is used in
(Tools / Xilinx Vivado) vertical SCA and ZV compensate
S-box are employed to hide the
horizontal SCA.

The main objective of this paper is

to secure the data from side channel
A Highly Secure FPGA-Based Dual-Hiding attacks by utilizing the Async-logic
Asynchronous-Logic AES Accelerator against AES with less area and low energy.
89 TVMATO976
Side-Channel Attacks The dual rail hiding is used in
(Tools / Xilinx ISE) vertical SCA and ZV compensate
S-box are employed to hide the
horizontal SCA.

The main objective of this paper is

to secure the data from side channel
A Highly Secure FPGA-Based Dual-Hiding attacks by utilizing the Async-logic
Asynchronous-Logic AES Accelerator against AES with less area and low energy.
90 TVPGTO814
Side-Channel Attacks The dual rail hiding is used in
(Tools / Xilinx Vivado) vertical SCA and ZV compensate
S-box are employed to hide the
horizontal SCA.

The main objective of this paper is

to secure the data from side channel
A Highly Secure FPGA-Based Dual-Hiding attacks by utilizing the Async-logic
Asynchronous-Logic AES Accelerator against AES with less area and low energy.
91 TVPGTO815
Side-Channel Attacks The dual rail hiding is used in
(Tools / Xilinx ISE) vertical SCA and ZV compensate
S-box are employed to hide the
horizontal SCA.

The main objective of this project is

A Low-Power and High-Accuracy Approximate
to design an approximate multiplier
92 TVPGTO808 Multiplier With Reconfigurable Truncation
with high accuracy and dynamically
(Tools / Xilinx Vivado)
truncate to maintain the required

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

accuracy as per the user and to

obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
93 TVPGTO809 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx ISE)
accuracy as per the user and to
obtain power optimization.

The main aim of this project is to

reduce the area complexity of
An Optimized M-Term Karatsuba-Like Binary
multiplier over the delay. This will be
94 TVMATO977 Polynomial Multiplier for Finite Field Arithmetic
applicable when the design needs
(Tools / Xilinx Vivado)
finite number of inputs and outputs
in operation.

The main aim of this project is to

reduce the area complexity of
An Optimized M-Term Karatsuba-Like Binary
multiplier over the delay. This will be
95 TVMATO978 Polynomial Multiplier for Finite Field Arithmetic
applicable when the design needs
(Tools / Xilinx ISE)
finite number of inputs and outputs
in operation.

The main aim of this project is to

reduce the area complexity of
An Optimized M-Term Karatsuba-Like Binary
multiplier over the delay. This will be
96 TVPGTO816 Polynomial Multiplier for Finite Field Arithmetic
applicable when the design needs
(Tools / Xilinx Vivado)
finite number of inputs and outputs
in operation.

The main aim of this project is to

reduce the area complexity of
An Optimized M-Term Karatsuba-Like Binary
multiplier over the delay. This will be
97 TVPGTO817 Polynomial Multiplier for Finite Field Arithmetic
applicable when the design needs
(Tools / Xilinx ISE)
finite number of inputs and outputs
in operation.

The main aim of this project is to

reduce the area complexity of
An Optimized M-Term Karatsuba-Like Binary
multiplier over the delay. This will be
98 TVMAFE494 Polynomial Multiplier for Finite Field Arithmetic
applicable when the design needs
(Front End Domains / Arithmetic Core)
finite number of inputs and outputs
in operation.

The main aim of this paper is to

generate the true random numbers
A Novel Ultra-Compact FPGA-Compatible
with less FPGA resources. It will be
TRNG Architecture Exploiting Latched Ring
99 TVMAFE495 applicable when we introduce the
Oscillators
LRO. The randomness and
(Front End Domains / Communications)
metastability reduction are the
added advantages.

A Novel Ultra-Compact FPGA-Compatible The main aim of this paper is to

100 TVMATO979 TRNG Architecture Exploiting Latched Ring generate the true random numbers
Oscillators with less FPGA resources. It will be

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

applicable when we introduce the

LRO. The randomness and
(Tools / Xilinx Vivado)
metastability reduction are the
added advantages.

The main aim of this paper is to

generate the true random numbers
A Novel Ultra-Compact FPGA-Compatible
with less FPGA resources. It will be
TRNG Architecture Exploiting Latched Ring
101 TVMATO980 applicable when we introduce the
Oscillators
LRO. The randomness and
(Tools / Xilinx ISE)
metastability reduction are the
added advantages.

The main aim of this paper is to

generate the true random numbers
A Novel Ultra-Compact FPGA-Compatible
with less FPGA resources. It will be
TRNG Architecture Exploiting Latched Ring
102 TVPGTO818 applicable when we introduce the
Oscillators
LRO. The randomness and
(Tools / Xilinx Vivado)
metastability reduction are the
added advantages.

The main aim of this paper is to

generate the true random numbers
A Novel Ultra-Compact FPGA-Compatible
with less FPGA resources. It will be
TRNG Architecture Exploiting Latched Ring
103 TVPGTO819 applicable when we introduce the
Oscillators
LRO. The randomness and
(Tools / Xilinx ISE)
metastability reduction are the
added advantages.

The idea of this paper is to reduce

the time complexity over the existing
A High-Throughput VLSI Architecture Design
standard Huffman encoder. This will
104 TVPGTO821 of Canonical Huffman Encoder
be achieved using the splitting tree
(Tools / Xilinx ISE)
technique. High compression radio
is added advantage of CHN.

The main aim of this paper is to

TROT: A Three-Edge Ring Oscillator Based generate the true random numbers
True Random Number Generator with through 3 edge ring oscillators to
105 TVMAFE497
Time-to-Digital Conversion increase the hardware security as
(Front End Domains / Communications) well as increase the randomness of
the output.

The main aim of this paper is to

TROT: A Three-Edge Ring Oscillator Based generate the true random numbers
True Random Number Generator with through 3 edge ring oscillators to
106 TVMATO983
Time-to-Digital Conversion increase the hardware security as
(Tools / Xilinx Vivado) well as increase the randomness of
the output.

In this project a reconfigurable

FPGA Implementation of Reconfigurable CORDIC hardware approach is
CORDIC Algorithm and a Memristive Chaotic designed with two approaches of
107 TVMAFE499
System with Transcendental Nonlinearities single multiplier and multiplier
(Front End Domains / DSP Core) approach. Here these two are
compared both have its own

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

advantages and these are designed

for the purpose of memristive
chaotic system.

The idea of this paper is to reduce

the time complexity over the existing
A High-Throughput VLSI Architecture Design
standard Huffman encoder. This will
108 TVMAFE496 of Canonical Huffman Encoder
be achieved using the splitting tree
(Front End Domains / Communications)
technique. High compression radio
is added advantage of CHN.

The idea of this paper is to reduce

the time complexity over the existing
A High-Throughput VLSI Architecture Design
standard Huffman encoder. This will
109 TVMATO981 of Canonical Huffman Encoder
be achieved using the splitting tree
(Tools / Xilinx Vivado)
technique. High compression radio
is added advantage of CHN.

The idea of this paper is to reduce

the time complexity over the existing
A High-Throughput VLSI Architecture Design
standard Huffman encoder. This will
110 TVMATO982 of Canonical Huffman Encoder
be achieved using the splitting tree
(Tools / Xilinx ISE)
technique. High compression radio
is added advantage of CHN.

The idea of this paper is to reduce

the time complexity over the existing
A High-Throughput VLSI Architecture Design
standard Huffman encoder. This will
111 TVPGTO820 of Canonical Huffman Encoder
be achieved using the splitting tree
(Tools / Xilinx Vivado)
technique. High compression radio
is added advantage of CHN.

The main aim of this paper is to

TROT: A Three-Edge Ring Oscillator Based generate the true random numbers
True Random Number Generator with through 3 edge ring oscillators to
112 TVMATO984
Time-to-Digital Conversion increase the hardware security as
(Tools / Xilinx ISE) well as increase the randomness of
the output.

The main aim of this paper is to

TROT: A Three-Edge Ring Oscillator Based generate the true random numbers
True Random Number Generator with through 3 edge ring oscillators to
113 TVPGTO822
Time-to-Digital Conversion increase the hardware security as
(Tools / Xilinx Vivado) well as increase the randomness of
the output.

The main aim of this paper is to

TROT: A Three-Edge Ring Oscillator Based generate the true random numbers
True Random Number Generator with through 3 edge ring oscillators to
114 TVPGTO823
Time-to-Digital Conversion increase the hardware security as
(Tools / Xilinx ISE) well as increase the randomness of
the output.

Effective Hardware Accelerator for 2D DCT In this implementation, a DCT/IDCT

115 TVMAFE501 IDCT Using Improved Loeffler Architecture hardware architecture using loeffler
(Front End Domains / DSP Core) algorithm with multiplier les DCT

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

was proposed. To implement

multiplier less DCT, CDS encoding
was implemented and thereby the
efficiency of the design of DCT has
been optimized.

In this implementation, a DCT/IDCT

hardware architecture using loeffler
algorithm with multiplier les DCT
Effective Hardware Accelerator for 2D DCT
was proposed. To implement
116 TVMATO991 IDCT Using Improved Loeffler Architecture
multiplier less DCT, CDS encoding
(Tools / Xilinx Vivado)
was implemented and thereby the
efficiency of the design of DCT has
been optimized.

In this implementation, a DCT/IDCT

hardware architecture using loeffler
algorithm with multiplier les DCT
Effective Hardware Accelerator for 2D DCT
was proposed. To implement
117 TVMATO992 IDCT Using Improved Loeffler Architecture
multiplier less DCT, CDS encoding
(Tools / Xilinx ISE)
was implemented and thereby the
efficiency of the design of DCT has
been optimized.

In this implementation, a DCT/IDCT

hardware architecture using loeffler
algorithm with multiplier les DCT
Effective Hardware Accelerator for 2D DCT
was proposed. To implement
118 TVPGTO830 IDCT Using Improved Loeffler Architecture
multiplier less DCT, CDS encoding
(Tools / Xilinx Vivado)
was implemented and thereby the
efficiency of the design of DCT has
been optimized.

In this implementation, a DCT/IDCT

hardware architecture using loeffler
algorithm with multiplier les DCT
Effective Hardware Accelerator for 2D DCT
was proposed. To implement
119 TVPGTO831 IDCT Using Improved Loeffler Architecture
multiplier less DCT, CDS encoding
(Tools / Xilinx ISE)
was implemented and thereby the
efficiency of the design of DCT has
been optimized.

In this project a reconfigurable

CORDIC hardware approach is
designed with two approaches of
FPGA Implementation of Reconfigurable
single multiplier and multiplier
CORDIC Algorithm and a Memristive Chaotic
120 TVMATO987 approach. Here these two are
System with Transcendental Nonlinearities
compared both have its own
(Tools / Xilinx Vivado)
advantages and these are designed
for the purpose of memristive
chaotic system.

FPGA Implementation of Reconfigurable In this project a reconfigurable

CORDIC Algorithm and a Memristive Chaotic CORDIC hardware approach is
121 TVMATO988
System with Transcendental Nonlinearities designed with two approaches of
(Tools / Xilinx ISE) single multiplier and multiplier

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

approach. Here these two are

compared both have its own
advantages and these are designed
for the purpose of memristive
chaotic system.

In this project a reconfigurable

CORDIC hardware approach is
designed with two approaches of
FPGA Implementation of Reconfigurable
single multiplier and multiplier
CORDIC Algorithm and a Memristive Chaotic
122 TVPGTO826 approach. Here these two are
System with Transcendental Nonlinearities
compared both have its own
(Tools / Xilinx Vivado)
advantages and these are designed
for the purpose of memristive
chaotic system.

In this project a reconfigurable

CORDIC hardware approach is
designed with two approaches of
FPGA Implementation of Reconfigurable
single multiplier and multiplier
CORDIC Algorithm and a Memristive Chaotic
123 TVPGTO827 approach. Here these two are
System with Transcendental Nonlinearities
compared both have its own
(Tools / Xilinx ISE)
advantages and these are designed
for the purpose of memristive
chaotic system.

This an approximate multiplier with

Radix-256 booth based encoding
Design of Approximate Radix-256 Booth has been suggested. In order to
124 TVMAFE500 Encoding for Error-Tolerant Computing evaluate the booth encoding based
(Front End Domains / Arithmetic Core) on radix-256 a 16 bit approximate
multiplier was designed and
implemented.

This an approximate multiplier with

Radix-256 booth based encoding
Design of Approximate Radix-256 Booth has been suggested. In order to
125 TVMATO989 Encoding for Error-Tolerant Computing evaluate the booth encoding based
(Tools / Xilinx Vivado) on radix-256 a 16 bit approximate
multiplier was designed and
implemented.

This an approximate multiplier with

Radix-256 booth based encoding
Design of Approximate Radix-256 Booth has been suggested. In order to
126 TVMATO990 Encoding for Error-Tolerant Computing evaluate the booth encoding based
(Tools / Xilinx ISE) on radix-256 a 16 bit approximate
multiplier was designed and
implemented.

This an approximate multiplier with

Radix-256 booth based encoding
Design of Approximate Radix-256 Booth
has been suggested. In order to
127 TVPGTO828 Encoding for Error-Tolerant Computing
evaluate the booth encoding based
(Tools / Xilinx Vivado)
on radix-256 a 16 bit approximate
multiplier was designed and

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

implemented.

This an approximate multiplier with

Radix-256 booth based encoding
Design of Approximate Radix-256 Booth has been suggested. In order to
128 TVPGTO829 Encoding for Error-Tolerant Computing evaluate the booth encoding based
(Tools / Xilinx ISE) on radix-256 a 16 bit approximate
multiplier was designed and
implemented.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
129 TVMAFE504 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Front End Domains / DSP Core)
accuracy as per the user and to
obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
130 TVMATO998 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx ISE)
accuracy as per the user and to
obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
131 TVPGTO836 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx Vivado)
accuracy as per the user and to
obtain power optimization.

The main objective of this project is

to design an approximate multiplier
A Low-Power and High-Accuracy Approximate
with high accuracy and dynamically
132 TVPGTO837 Multiplier With Reconfigurable Truncation
truncate to maintain the required
(Tools / Xilinx ISE)
accuracy as per the user and to
obtain power optimization.

In this project we are going to

implement the circuit functions
Design and optimization of MIMO filter using represent low pass filter (LPF), high
133 TVMABE175 current conveyor pass filter (HPF) and band pass
(Back End Domains / Transistor Logic) filter (BPF) function while taking
different input and output port
combinations.

A Reliable Low Standby Power 10T SRAM Cell The main objective of this paper is
134 TVMABE179 with Expanded Static Noise Margins to implement LP10TSRAM in order
(Back End Domains / Core Memories) to achieve lesser power dissipation.

A Reliable Low Standby Power 10T SRAM Cell The main objective of this paper is
135 TVMATO1016 with Expanded Static Noise Margins to implement LP10TSRAM in order
(Tools / Tanner EDA) to achieve lesser power dissipation.

A Reliable Low Standby Power 10T SRAM Cell The main objective of this paper is
136 TVPGTO850
with Expanded Static Noise Margins to implement LP10TSRAM in order

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S.No Project Code Project Name Objective

(Tools / Tanner EDA) to achieve lesser power dissipation.

. In this paper, we proposed efficient

quantum-classical modular
multipliers and the first
Quantum Modular Multiplication quantum-quantum modular
137 TVPGTO907
(Tools / Xilinx Vivado) multipliers that do not require a
reduction stage by transforming the
partial product used in multiplication
utilizing bit-shift operation.

. In this paper, we proposed efficient

quantum-classical modular
multipliers and the first
Quantum Modular Multiplication quantum-quantum modular
138 TVPGTO908
(Tools / Xilinx ISE) multipliers that do not require a
reduction stage by transforming the
partial product used in multiplication
utilizing bit-shift operation.

. In this paper, we proposed efficient

quantum-classical modular
multipliers and the first
Quantum Modular Multiplication quantum-quantum modular
139 TVMAFE530
(Front End Domains / Arithmetic Core) multipliers that do not require a
reduction stage by transforming the
partial product used in multiplication
utilizing bit-shift operation.

. In this paper, we proposed efficient

quantum-classical modular
multipliers and the first
Quantum Modular Multiplication quantum-quantum modular
140 TVMATO1116
(Tools / Xilinx Vivado) multipliers that do not require a
reduction stage by transforming the
partial product used in multiplication
utilizing bit-shift operation.

. In this paper, we proposed efficient

quantum-classical modular
multipliers and the first
Quantum Modular Multiplication quantum-quantum modular
141 TVMATO1117
(Tools / Xilinx ISE) multipliers that do not require a
reduction stage by transforming the
partial product used in multiplication
utilizing bit-shift operation.

The main aim of this paper is to

An Efficient TDC Using a Dual-Mode implement the
Resource-Saving Method Evaluated in a 28-nm time-to-digital-converter (TDC)
142 TVMAFE532
FPGA based on the dual-mode tapped
(Front End Domains / Arithmetic Core) delay line using CARRY4 sequence
to reduce the dead-time.

An Efficient TDC Using a Dual-Mode The main aim of this paper is to

143 TVMATO1120
Resource-Saving Method Evaluated in a 28-nm implement the

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S.No Project Code Project Name Objective

time-to-digital-converter (TDC)
FPGA based on the dual-mode tapped
(Tools / Xilinx Vivado) delay line using CARRY4 sequence
to reduce the dead-time.

The main aim of this paper is to

An Efficient TDC Using a Dual-Mode implement the
Resource-Saving Method Evaluated in a 28-nm time-to-digital-converter (TDC)
144 TVMATO1121
FPGA based on the dual-mode tapped
(Tools / Xilinx ISE) delay line using CARRY4 sequence
to reduce the dead-time.

This paper presents a

comprehensive design space
Energy-Quality Scalable Design Space exploration for boosting energy
Exploration of Approximate FFT Hardware efficiency of a fast Fourier transform
145 TVMAFE533
Architectures (FFT) VLSI accelerator, exploiting
(Front End Domains / Arithmetic Core) several approximate multipliers (Ax
M) combined with approximate
adder (Ax A) circuits.

This paper presents a

comprehensive design space
Energy-Quality Scalable Design Space exploration for boosting energy
Exploration of Approximate FFT Hardware efficiency of a fast Fourier transform
146 TVMATO1122
Architectures (FFT) VLSI accelerator, exploiting
(Tools / Xilinx Vivado) several approximate multipliers (Ax
M) combined with approximate
adder (Ax A) circuits.

This paper presents a

comprehensive design space
Energy-Quality Scalable Design Space exploration for boosting energy
Exploration of Approximate FFT Hardware efficiency of a fast Fourier transform
147 TVMATO1123
Architectures (FFT) VLSI accelerator, exploiting
(Tools / Xilinx ISE) several approximate multipliers (Ax
M) combined with approximate
adder (Ax A) circuits.

The design of high-performance

processors with very low power
Design of RISC & MIPS Architecture
148 TVMAFE534 requirements is the primary goal of
(Front End Domains / Communications)
many contemporary and futuristic
applications.

The design of high-performance

processors with very low power
Design of RISC & MIPS Architecture
149 TVMATO1124 requirements is the primary goal of
(Tools / Xilinx Vivado)
many contemporary and futuristic
applications.

The design of high-performance

processors with very low power
Design of RISC & MIPS Architecture
150 TVMATO1125 requirements is the primary goal of
(Tools / Xilinx ISE)
many contemporary and futuristic
applications.

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S.No Project Code Project Name Objective

This paper proposes a Very Large

Scale Integration (VLSI) architecture
for the implementation of Turbo
VLSI Implementation of Turbo Coder for LTE
decoder. Soft-in-soft out decoders,
151 TVPGTO911 using Verilog HDL
interleavers and deinterleavers is
(Tools / Xilinx Vivado)
used in the decoder side which
employs Maximum-a-Posteriori
(MAP) algorithm.

This paper proposes a Very Large

Scale Integration (VLSI) architecture
for the implementation of Turbo
VLSI Implementation of Turbo Coder for LTE
decoder. Soft-in-soft out decoders,
152 TVPGTO912 using Verilog HDL
interleavers and deinterleavers is
(Tools / Xilinx ISE)
used in the decoder side which
employs Maximum-a-Posteriori
(MAP) algorithm.

This paper proposes a Very Large

Scale Integration (VLSI) architecture
for the implementation of Turbo
VLSI Implementation of Turbo Coder for LTE
decoder. Soft-in-soft out decoders,
153 TVMATO1126 using Verilog HDL
interleavers and deinterleavers is
(Tools / Xilinx Vivado)
used in the decoder side which
employs Maximum-a-Posteriori
(MAP) algorithm.

This paper proposes a Very Large

Scale Integration (VLSI) architecture
for the implementation of Turbo
VLSI Implementation of Turbo Coder for LTE
decoder. Soft-in-soft out decoders,
154 TVMATO1127 using Verilog HDL
interleavers and deinterleavers is
(Tools / Xilinx ISE)
used in the decoder side which
employs Maximum-a-Posteriori
(MAP) algorithm.

This paper proposes a Very Large

Scale Integration (VLSI) architecture
for the implementation of Turbo
VLSI Implementation of Turbo Coder for LTE
decoder. Soft-in-soft out decoders,
155 TVMAFE535 using Verilog HDL
interleavers and deinterleavers is
(Front End Domains / DSP Core)
used in the decoder side which
employs Maximum-a-Posteriori
(MAP) algorithm.

This paper proposes the VLSI

implementation of Fully parallel and
CSD FIR filter architecture. In this
VLSI Implementation of Fully Parallel and CSD
technique, the area and power
156 TVMAFE538 FIR Filter Architecture
optimization are achieved by the
(Front End Domains / DSP Core)
incorporation of Vedic multiplier and
Koggestone adder instead of
traditional multiplier and adder.

VLSI Implementation of Fully Parallel and CSD This paper proposes the VLSI
157 TVMATO1132
FIR Filter Architecture implementation of Fully parallel and

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

CSD FIR filter architecture. In this

technique, the area and power
optimization are achieved by the
(Tools / Xilinx Vivado)
incorporation of Vedic multiplier and
Koggestone adder instead of
traditional multiplier and adder.

This paper proposes the VLSI

implementation of Fully parallel and
CSD FIR filter architecture. In this
VLSI Implementation of Fully Parallel and CSD
technique, the area and power
158 TVMATO1133 FIR Filter Architecture
optimization are achieved by the
(Tools / Xilinx ISE)
incorporation of Vedic multiplier and
Koggestone adder instead of
traditional multiplier and adder.

UART- Universal Asynchronous

Receiver Transmitter is a serial
Simulation and synthesis of UART through
communication protocol. UART
159 TVMAFE539 FPGA Zedboard for IoT applications
consists of two main modules;
(Front End Domains / Communications)
UART Transmitter and UART
Receiver.

UART- Universal Asynchronous

Receiver Transmitter is a serial
Simulation and synthesis of UART through
communication protocol. UART
160 TVMATO1134 FPGA Zedboard for IoT applications
consists of two main modules;
(Tools / Xilinx Vivado)
UART Transmitter and UART
Receiver.

UART- Universal Asynchronous

Receiver Transmitter is a serial
Simulation and synthesis of UART through
communication protocol. UART
161 TVMATO1135 FPGA Zedboard for IoT applications
consists of two main modules;
(Tools / Xilinx ISE)
UART Transmitter and UART
Receiver.

The main objective of this project is

A Unified NVRAM and TRNG in Standard
to present a NVRAM TRNG using a
162 TVPGTO905 CMOS Technology
novel mechanism to manage the
(Tools / Tanner EDA)
charges into SFG.

The main objective of this project is

A Unified NVRAM and TRNG in Standard
to present a NVRAM TRNG using a
163 TVMATO1114 CMOS Technology
novel mechanism to manage the
(Tools / Tanner EDA)
charges into SFG.

The main objective of this project is

A Unified NVRAM and TRNG in Standard
to present a NVRAM TRNG using a
164 TVMABE201 CMOS Technology
novel mechanism to manage the
(Back End Domains / Core Memories)
charges into SFG.

The main objective of this project is

A Unified NVRAM and TRNG in Standard
to present a NVRAM TRNG using a
165 TVMABE202 CMOS Technology
novel mechanism to manage the
(Back End Domains / Low Power VLSI)
charges into SFG.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

A Novel Clock Gating Approach for the Design The main objective of this project is
166 TVMATO1108 of Low-Power Linear Feedback Shift Registers to reduce the power consumption of
(Tools / Tanner EDA) LFSR using gated clock approach.

A Novel Clock Gating Approach for the Design The main objective of this project is
167 TVMATO1109 of Low-Power Linear Feedback Shift Registers to reduce the power consumption of
(Tools / Cadence EDA) LFSR using gated clock approach.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
168 TVPGTO903 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Tools / Tanner EDA)
reference of current.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
169 TVPGTO904 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Tools / Cadence EDA)
reference of current.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
170 TVMATO1111 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Tools / Tanner EDA)
reference of current.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
171 TVMATO1112 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Tools / Cadence EDA)
reference of current.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
172 TVMABE198 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Back End Domains / Low Power VLSI)
reference of current.

The main aim of this project is to

An Accurate Low-Power Power-on-Reset
present a Low-Power
173 TVMABE199 Circuit in 55-nm CMOS Technology
Power-on-Reset circuit based on the
(Back End Domains / Transistor Logic)
reference of current.

The main objective of this project is

Low Power and High-Performance Associative
to analyze the design a CAM
174 TVMABE208 Memory Design
Module using transmission gate
(Back End Domains / Low Power VLSI)
logic for various applications.

The main objective of this project is

Low Power and High-Performance Associative
to analyze the design a CAM
175 TVMABE209 Memory Design
Module using transmission gate
(Back End Domains / Transistor Logic)
logic for various applications.

The main objective of this project is

Low Power and High-Performance Associative
to analyze the design a CAM
176 TVPGTO923 Memory Design
Module using transmission gate
(Tools / Tanner EDA)
logic for various applications.

The main objective of this project is

Low Power and High-Performance Associative
to analyze the design a CAM
177 TVPGBE148 Memory Design
Module using transmission gate
(Back End Domains / Low Power VLSI)
logic for various applications.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main objective of this project is

Low Power and High-Performance Associative
to analyze the design a CAM
178 TVPGBE149 Memory Design
Module using transmission gate
(Back End Domains / Transistor Logic)
logic for various applications.

The paper presents a novel

High-Speed Grouping and Decomposition
approach to binary multiplication by
179 TVMABE212 Multiplier for Binary Multiplication
introducing a high-speed grouping
(Back End Domains / Core Memories)
and decomposition multiplier.

The paper presents a novel

High-Speed Grouping and Decomposition
approach to binary multiplication by
180 TVPGTO930 Multiplier for Binary Multiplication
introducing a high-speed grouping
(Tools / Tanner EDA)
and decomposition multiplier.

A High-Speed FPGA-based True Random The main objective of this paper is

Number Generator using Metastability with to describes a novel methodology
181 TVMAFE546
Clock Managers to easily design a TRNG on FPGA
(Front End Domains / Arithmetic Core) devices.

This paper presents an overview of

the steps involved in designing
efficient majority-logic-based
Efficient Design of Majority-Logic-Based
182 TVMAFE544 approximate arithmetic circuits and
Approximate Arithmetic Circuits
highlights some of the key
challenges and opportunities in this
field.

This paper presents an overview of

the steps involved in designing
Efficient Design of Majority-Logic-Based efficient majority-logic-based
183 TVPGTO926 Approximate Arithmetic Circuits approximate arithmetic circuits and
(Tools / Xilinx Vivado) highlights some of the key
challenges and opportunities in this
field.

This paper presents an overview of

the steps involved in designing
Efficient Design of Majority-Logic-Based efficient majority-logic-based
184 TVPGTO927 Approximate Arithmetic Circuits approximate arithmetic circuits and
(Tools / Xilinx ISE) highlights some of the key
challenges and opportunities in this
field.

The core idea of this paper is to

confirm whether the given image is
A Secure method for Image Signaturing using
original or manipulated one. Even
SHA 256, RSA, and Advanced Encryption
185 TVMAFE498 though a single pixel varied means it
Standard (AES)
will identify. This will identify using
(Front End Domains / Communications)
the 3 different algorithms SHA,
RSA, AES.

A Secure method for Image Signaturing using The core idea of this paper is to
SHA 256, RSA, and Advanced Encryption confirm whether the given image is
186 TVMATO985
Standard (AES) original or manipulated one. Even
(Tools / Xilinx Vivado) though a single pixel varied means it

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

will identify. This will identify using

the 3 different algorithms SHA,
RSA, AES.

The core idea of this paper is to

confirm whether the given image is
A Secure method for Image Signaturing using
original or manipulated one. Even
SHA 256, RSA, and Advanced Encryption
187 TVMATO986 though a single pixel varied means it
Standard (AES)
will identify. This will identify using
(Tools / Xilinx ISE)
the 3 different algorithms SHA,
RSA, AES.

The objective of this paper is to

Analysis and Comparison in the Energy-Delay analyze, design and compare six
Space of Nanometer CMOS One-Bit significant topologies of one-bit full
188 TVMATO1144
Full-Adders adders in terms of their
(Tools / Cadence EDA) Energy-Efficient Curves in the
Energy-Delay Space

Design and implementation of subway The main objective of this project is

automatic ticketing system based on Verilog to implement automatic ticketing
189 TVMAFE520
HDL system using FSM to reduce power
(Front End Domains / Finite State Machines) consumption

Security is always the need of the

Implementation of Smart Home using Finite hour in a home. An automation
190 TVMAFE561 State Machine Model system, which provides security as
(Front End Domains / Arithmetic Core) well as comfort, ensures reliability
and ease.

This work aims at creating a parking

system with multiple slots to
Multi-Car Parking System Using Verilog mitigate the problem of tight parking
191 TVMAFE562
(Front End Domains / Arithmetic Core) spaces and high manual efforts to
keep track of free space within a
constrained area.

VLSI IMPLEMENTATION OF HIGH SPEED Single-precision floating-point

SINGLE PRECESSION FLOATING POINT format is a computer number format
192 TVMAFE564
UNIT USING VERILOG that is used to represent a wide
(Front End Domains / Arithmetic Core) dynamic range of values

Based on the concept of obfuscation

Design Flow for The Implementation of
mode, in this paper, we study the
193 TVMAFE553 Obfuscated Finite State Machines
design flow for FPGA
(Front End Domains / Finite State Machines)
implementation.

The main objective of this paper is

A High-Efficiency Fast-Transient LDO with to implement Low Dropout
Low-Impedance Transient-Current Enhanced Regulator by employing novel
194 TVMABE178
Buffer buffer. The buffer designed is of
(Back End Domains / Transistor Logic) low-impedance transient-current
enhanced buffer.

A High-Efficiency Fast-Transient LDO with The main objective of this paper is

195 TVMATO1014
Low-Impedance Transient-Current Enhanced to implement Low Dropout

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Regulator by employing novel

Buffer buffer. The buffer designed is of
(Tools / Cadence EDA) low-impedance transient-current
enhanced buffer.

The main objective of this paper is

A High-Efficiency Fast-Transient LDO with to implement Low Dropout
Low-Impedance Transient-Current Enhanced Regulator by employing novel
196 TVPGTO849
Buffer buffer. The buffer designed is of
(Tools / Cadence EDA) low-impedance transient-current
enhanced buffer.

Offering a broad introduction to

low-power design principles applied
to SAR ADCs.
LOW-POWER SAR ADC DESIGN OVERVIEW
Presenting various state-of-the-art
AND SURVEY OF STATE-OF-THE-ART
197 TVMABE262 techniques used in modern SAR
TECHNIQUES
ADC designs.
(Back End Domains / Transistor Logic)
Comparing and analyzing different
approaches to achieve low power
consumption in SAR ADCs.

The primary objective is to develop

a hardware accelerator that
efficiently computes the
Effective Hardware Accelerator for 2D DCT or two-dimensional Discrete Cosine
198 TVMAFE620 IDCT Using Improved Loeffler Architecture Transform (DCT) and its inverse
(Front End Domains / Communications) (IDCT). The focus is on improving
processing speed and reducing
latency compared to existing
implementations.

The primary goal seems to be

DeBAM: Decoder Based Approximate creating a decoder-based
199 TVMAFE622 Multiplier for Low Power Applications approximate multiplier optimized for
(Front End Domains / Communications) low power consumption in electronic
circuits

The primary objective of designing a

BTI and Soft-Error Tolerant Voltage
Bootstrapped Schmitt Trigger Circuit
is to enhance the reliability and
stability of digital systems,
especially under conditions where
BTI and Soft-Error Tolerant Voltage
they are exposed to various forms of
200 TVMABE243 Bootstrapped Schmitt Trigger Circuit
stressors such as voltage
(Back End Domains / Cadence EDA)
fluctuations, temperature changes,
and radiation effects. This circuit
aims to mitigate the adverse effects
of these stressors on the
performance and longevity of digital
device

BTI and Soft-Error Tolerant Voltage The main of this project is to reduce
201 TVMATO715 Bootstrapped Schmitt Trigger Circuit the delay and NBTI effects by using
(Tools / Cadence EDA) N-mos transistors in Schmitt trigger

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

design

The main of this project is to reduce

BTI and Soft-Error Tolerant Voltage
the delay and NBTI effects by using
202 TVPGTO575 Bootstrapped Schmitt Trigger Circuit
N-mos transistors in Schmitt trigger
(Tools / Cadence EDA)
design

DESIGN OF 16 BIT RISC PROCESSOR

203 TVMATO1160
(Tools / Xilinx Vivado)

In this research, a 16-bit RISC

DESIGN OF 16 BIT RISC PROCESSOR processor with suggested
204 TVMATO1154
(Tools / Xilinx Vivado) behavioral design and functional
properties is put forth.

This brief bridges this gap by

AxBMs: Approximate Radix-8 Booth Multipliers
proposing high performance
for High-Performance FPGA-Based
205 TVMAFE606 approximate radix-8 Booth
Accelerators
multipliers whose designs target
(Front End Domains / Arithmetic Core)
FPGA-based systems.

Wideband Variable-Gain Amplifiers Based on a This paper reports two variable-gain

Pseudo-Current-Steering Gain-Tuning amplifiers (VGAs) featuring a new
206 TVMATO1156
Technique pseudo-current-steering gain-tuning
(Tools / Cadence EDA) technique.

This article presents a compact and

Compact Bit-Parallel Systolic Multiplier Over
efficient bit-parallel systolic array
207 TVMAFE598 GF(2m)
structure for multiplication over the
(Front End Domains / DSP Core)
extended binary field, GF(2m).

Design and performance analysis of 4-bit

The major concentration is on the
Nano-Processor design for low area, low
proposed 4-bit Nano processor
208 TVMABE229 power and minimum delay using 32nm CMOS
using CMOS 32nm technology by
technology.
using the Tanner EDA software tool.
(Back End Domains / Core Memories)

In this article, a segmented DAC

An Area-Efficient High-Resolution Segmented architecture is proposed. The
209 TVMABE228 ?-?-DAC for Built-In Self-Test Applications proposed architecture is realized
(Back End Domains / Transistor Logic) using two sub-DACs, where both
are delta sigma-based.

This paper describes the study of

sample and hold
Power Efficient 4-bit Flash ADC using Cadence
circuit, comparator and encoder in
210 TVPGBE154 Virtuoso
4-bit Flash Analog to Digital
(Back End Domains / Low Power VLSI)
Converter (ADC) to get a power
efficient ADC.

The main objective of this project is

Power optimization in configurable ALU using to reduce the power dissipation for
211 TVPGFE330 blend of techniques the design of ALU using different
(Front End Domains / Arithmetic Core) configurations of Clock gating
Technique.

212 TVMABE116 A Very-Low-Voltage Frequency Divider in The main aim of this project is to

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Folded MOS Current Mode Logic With reduce the power in Frequency
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Back End Domains / Transistor Logic) with novel architecture.

A Very-Low-Voltage Frequency Divider in The main aim of this project is to

Folded MOS Current Mode Logic With reduce the power in Frequency
213 TVMATO726
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Tools / Tanner EDA) with novel architecture.

A Very-Low-Voltage Frequency Divider in The main aim of this project is to

Folded MOS Current Mode Logic With reduce the power in Frequency
214 TVMATO727
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Tools / Cadence EDA) with novel architecture.

A Very-Low-Voltage Frequency Divider in The main aim of this project is to

Folded MOS Current Mode Logic With reduce the power in Frequency
215 TVPGBE121
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Back End Domains / Transistor Logic) with novel architecture.

A Very-Low-Voltage Frequency Divider in The main aim of this project is to

Folded MOS Current Mode Logic With reduce the power in Frequency
216 TVPGTO587
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Tools / Cadence EDA) with novel architecture.

A Very-Low-Voltage Frequency Divider in The main aim of this project is to

Folded MOS Current Mode Logic With reduce the power in Frequency
217 TVPGTO588
Complementary n- and p-type Flip-Flops divided by 16 circuit by using FCML
(Tools / Tanner EDA) with novel architecture.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
218 TVMABE119 Implementation of Flash ADC
thermometer to a binary encoder.
(Back End Domains / Transistor Logic)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
219 TVMABE120 Implementation of Flash ADC
thermometer to a binary encoder.
(Back End Domains / Low Power VLSI)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
220 TVMATO716 Implementation of Flash ADC
thermometer to a binary encoder.
(Tools / Tanner EDA)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
221 TVMATO717 Implementation of Flash ADC
thermometer to a binary encoder.
(Tools / Cadence EDA)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
222 TVPGBE115 Implementation of Flash ADC
thermometer to a binary encoder.
(Back End Domains / Transistor Logic)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
223 TVPGBE116 Implementation of Flash ADC
thermometer to a binary encoder.
(Back End Domains / Low Power VLSI)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
224 TVPGTO577 Implementation of Flash ADC
thermometer to a binary encoder.
(Tools / Cadence EDA)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The aim of this paper is to

implement a Flash ADC structure
consists of a resistive ladder
Design of Two Stage Operational Amplifier and
network, comparators, and the
225 TVPGTO578 Implementation of Flash ADC
thermometer to a binary encoder.
(Tools / Tanner EDA)
Encoder structure in this paper is
implemented using 2:1 mux based
on switch logic.

The main objective of this paper is

to implement fast saturated binary
Fast Binary Counters and Compressors
counters based on sorting network
226 TVMAFE383 Generated by Sorting Network
to improve the efficiency of designs
(Front End Domains / Arithmetic Core)
involving summation of multiple
operands.

The main objective of this paper is

Fast Binary Counters and Compressors
to implement fast saturated binary
227 TVMATO738 Generated by Sorting Network
counters based on sorting network
(Tools / Xilinx Vivado)
to improve the efficiency of designs

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

involving summation of multiple

operands.

The main objective of this paper is

to implement fast saturated binary
Fast Binary Counters and Compressors
counters based on sorting network
228 TVMATO739 Generated by Sorting Network
to improve the efficiency of designs
(Tools / Xilinx ISE)
involving summation of multiple
operands.

The main objective of this paper is

to implement fast saturated binary
Fast Binary Counters and Compressors
counters based on sorting network
229 TVPGFE308 Generated by Sorting Network
to improve the efficiency of designs
(Front End Domains / Arithmetic Core)
involving summation of multiple
operands.

The main objective of this paper is

to implement fast saturated binary
Fast Binary Counters and Compressors
counters based on sorting network
230 TVPGTO602 Generated by Sorting Network
to improve the efficiency of designs
(Tools / Xilinx Vivado)
involving summation of multiple
operands.

The main objective of this paper is

to implement fast saturated binary
Fast Binary Counters and Compressors
counters based on sorting network
231 TVPGTO603 Generated by Sorting Network
to improve the efficiency of designs
(Tools / Xilinx ISE)
involving summation of multiple
operands.

The main objective of this paper is

to reduce fan-out and improve the
Constant-time Synchronous Binary Counter
counting rate, for this we are
232 TVMAFE378 with Minimal Clock Period
implementing constant-time
(Front End Domains / Testing)
synchronous binary counter based
on pre-scaling concept.

The main objective of this paper is

to reduce fan-out and improve the
Constant-time Synchronous Binary Counter
counting rate, for this we are
233 TVMATO728 with Minimal Clock Period
implementing constant-time
(Tools / Xilinx Vivado)
synchronous binary counter based
on pre-scaling concept.

The main objective of this paper is

to reduce fan-out and improve the
Constant-time Synchronous Binary Counter
counting rate, for this we are
234 TVMATO729 with Minimal Clock Period
implementing constant-time
(Tools / Xilinx ISE)
synchronous binary counter based
on pre-scaling concept.

The main objective of this paper is

Constant-time Synchronous Binary Counter
to reduce fan-out and improve the
235 TVPGFE303 with Minimal Clock Period
counting rate, for this we are
(Front End Domains / Design for Testability)
implementing constant-time

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

synchronous binary counter based

on pre-scaling concept.

The main objective of this paper is

to reduce fan-out and improve the
Constant-time Synchronous Binary Counter
counting rate, for this we are
236 TVPGTO592 with Minimal Clock Period
implementing constant-time
(Tools / Xilinx Vivado)
synchronous binary counter based
on pre-scaling concept.

The main objective of this paper is

to reduce fan-out and improve the
Constant-time Synchronous Binary Counter
counting rate, for this we are
237 TVPGTO593 with Minimal Clock Period
implementing constant-time
(Tools / Xilinx ISE)
synchronous binary counter based
on pre-scaling concept.

The main objective of this paper is

to enhance the operation speed with
A High-Performance Core Micro-Architecture
the help of instruction set
Based on RISC-V ISA for Low Power
238 TVPGFE302 architecture. The multiplier and
Applications
dividers are employed to perform
(Front End Domains / DSP Core)
both signed and unsigned
operations with less area cost

The main objective of this paper is

to enhance the operation speed with
A High-Performance Core Micro-Architecture
the help of instruction set
Based on RISC-V ISA for Low Power
239 TVPGTO589 architecture. The multiplier and
Applications
dividers are employed to perform
(Tools / Cadence EDA)
both signed and unsigned
operations with less area cost

The main objective of this paper is

to enhance the operation speed with
A High-Performance Core Micro-Architecture
the help of instruction set
Based on RISC-V ISA for Low Power
240 TVPGTO590 architecture. The multiplier and
Applications
dividers are employed to perform
(Tools / Xilinx Vivado)
both signed and unsigned
operations with less area cost

The main objective of this paper is

to enhance the operation speed with
A High-Performance Core Micro-Architecture
the help of instruction set
Based on RISC-V ISA for Low Power
241 TVPGTO591 architecture. The multiplier and
Applications
dividers are employed to perform
(Tools / Xilinx ISE)
both signed and unsigned
operations with less area cost

The main aim of this paper is to

Low-Power Multiplexer Structures Targeting implement mux architecture based
242 TVMAFE398 Efficient QCA Nanotechnology Circuit Designs on QCA in an efficient way and
(Front End Domains / Arithmetic Core) improve the performance of the
design.

243 TVPGFE323 Low-Power Multiplexer Structures Targeting The main aim of this paper is to

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S.No Project Code Project Name Objective

implement mux architecture based

Efficient QCA Nanotechnology Circuit Designs on QCA in an efficient way and
(Front End Domains / Arithmetic Core) improve the performance of the
design.

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
244 TVMAFE374 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Front End Domains / Communications)
transformation for optimization.

In this paper, two proposed circuits

of PMOS-biased sense amplifier is
Low Power, High Performance PMOS Biased implemented. A fast access time
245 TVMABE137 Sense Amplifier and low power dissipation are
(Back End Domains / Cadence EDA) achieved with newly developed
circuits of sense amplifier for low
voltage supply.

In this paper, two proposed circuits

of PMOS-biased sense amplifier is
Low Power, High Performance PMOS Biased implemented. A fast access time
246 TVMABE138 Sense Amplifier and low power dissipation are
(Back End Domains / Low Power VLSI) achieved with newly developed
circuits of sense amplifier for low
voltage supply.

In this paper, two proposed circuits

of PMOS-biased sense amplifier is
Low Power, High Performance PMOS Biased implemented. A fast access time
247 TVPGTO646 Sense Amplifier and low power dissipation are
(Tools / Cadence EDA) achieved with newly developed
circuits of sense amplifier for low
voltage supply.

In this paper, two proposed circuits

of PMOS-biased sense amplifier is
Low Power, High Performance PMOS Biased implemented. A fast access time
248 TVPGTO647 Sense Amplifier and low power dissipation are
(Tools / Tanner EDA) achieved with newly developed
circuits of sense amplifier for low
voltage supply.

In this paper, two proposed circuits

of PMOS-biased sense amplifier is
Low Power, High Performance PMOS Biased implemented. A fast access time
249 TVPGBE137 Sense Amplifier and low power dissipation are
(Back End Domains / Low Power VLSI) achieved with newly developed
circuits of sense amplifier for low
voltage supply.

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
250 TVMATO742 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Tools / Xilinx Vivado)
transformation for optimization.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
251 TVMATO743 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Tools / Xilinx ISE)
transformation for optimization.

Virtex 7 FPGA Implementation of 256 Bit Key The main objective of this paper is
AES Algorithm with Key Schedule and Sub to improve the security by extending
252 TVPGFE310 Bytes Block Optimization the cipher key size into 256 bit key
(Front End Domains / Communications and AES algorithm and applied selective
Crypto Core) transformation for optimization.

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
253 TVPGTO606 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Tools / Xilinx Vivado)
transformation for optimization.

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
254 TVPGTO607 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Tools / Xilinx ISE)
transformation for optimization.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
255 TVPGBE135 Bio Medical Applications
for the read operation can be
(Back End Domains / Core Memories)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
256 TVPGTO644 Bio Medical Applications
for the read operation can be
(Tools / Cadence EDA)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
257 TVPGTO645 Bio Medical Applications
for the read operation can be
(Tools / Tanner EDA)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

Transmission Gate -Based 8T SRAM Cell For gate based SRAM is designed for
258 TVMABE135 Bio Medical Applications biomedical applications. By using
(Back End Domains / Cadence EDA) this SRAM, the extra circuit required
for the read operation can be

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

reduced. Hence the proposed

SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
259 TVMABE136 Bio Medical Applications
for the read operation can be
(Back End Domains / Core Memories)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
260 TVMATO778 Bio Medical Applications
for the read operation can be
(Tools / Tanner EDA)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

In this paper, a novel transmission

gate based SRAM is designed for
biomedical applications. By using
Transmission Gate -Based 8T SRAM Cell For
this SRAM, the extra circuit required
261 TVMATO779 Bio Medical Applications
for the read operation can be
(Tools / Cadence EDA)
reduced. Hence the proposed
SRAM provides better performance
in terms of area and power.

The main objective of this paper is

Virtex 7 FPGA Implementation of 256 Bit Key
to improve the security by extending
AES Algorithm with Key Schedule and Sub
262 TVPGTO658 the cipher key size into 256 bit key
Bytes Block Optimization
AES algorithm and applied selective
(Tools / FPGA)
transformation for optimization.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
263 TVMAFE407 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Front End Domains / Arithmetic Core)
efficiency.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
264 TVMATO801 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Xilinx Vivado)
efficiency.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
265 TVMATO802 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Xilinx ISE)
efficiency.

266 TVMATO803 An Efficient and High-Speed Overlap-Free The main aim of this project is to

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

implement the Overlap-Free

Karatsuba-Based Finite-Field Multiplier for
Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Cadence EDA)
efficiency.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
267 TVPGTO677 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Xilinx Vivado)
efficiency.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
268 TVPGTO678 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Xilinx ISE)
efficiency.

The main aim of this project is to

An Efficient and High-Speed Overlap-Free
implement the Overlap-Free
Karatsuba-Based Finite-Field Multiplier for
269 TVPGTO679 Karatsuba-Based Finite-Field
FGPA Implementation
Multiplier with high speed and area
(Tools / Cadence EDA)
efficiency.

The main aim of this paper is to

A Cost-Efficient QCA XOR-XNOR Topology for implement xor xnor gates with
270 TVMAFE444 Nanotechnology Applications reduced number on QCA cells in an
(Front End Domains / Arithmetic Core) efficient way and improve the
performance of the design.

The main aim of this paper is to

A Cost-Efficient QCA XOR-XNOR Topology for implement xor xnor gates with
271 TVMATO874 Nanotechnology Applications reduced number on QCA cells in an
(Tools / QCA) efficient way and improve the
performance of the design.

Area Efficient Multilayer Arithmetic Logic Unit

Implementation in Quantum-dot Cellular
272 TVMAFE450
Automata
(Front End Domains / Arithmetic Core)

Area Efficient Multilayer Arithmetic Logic Unit

Implementation in Quantum-dot Cellular
273 TVMATO884
Automata
(Tools / QCA)

Binary Coded Decimal Seven Segment Circuit

Designing using Quantum dot Cellular
274 TVMAFE456
Automata
(Front End Domains / Arithmetic Core)

Binary Coded Decimal Seven Segment Circuit

Designing using Quantum dot Cellular
275 TVMATO895
Automata
(Tools / QCA)

276 TVMAFE464 QCA based design of cost-efficient code The main aim of this paper is to

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

implement code converters with

converter with temperature stability and energy
reduced number on QCA cells in an
efficiency analysis
efficient way and improve the
(Front End Domains / Arithmetic Core)
performance of the design.

The main aim of this paper is to

QCA based design of cost-efficient code
implement code converters with
converter with temperature stability and energy
277 TVMATO903 reduced number on QCA cells in an
efficiency analysis
efficient way and improve the
(Tools / QCA)
performance of the design.

The main objective of this project is

A High-Speed Floating-Point to design a floating point multiply
278 TVMAFE543 Multiply-Accumulator Based on FPGAs accumulator which comprises of
(Front End Domains / DSP Core) signed soft multiplier and a single
floating point accumulator.

The main objective of this project is

A High-Speed Floating-Point to design a floating point multiply
279 TVMATO1141 Multiply-Accumulator Based on FPGAs accumulator which comprises of
(Tools / Xilinx Vivado) signed soft multiplier and a single
floating point accumulator.

The main objective of this project is

A High-Speed Floating-Point to design a floating point multiply
280 TVMATO1142 Multiply-Accumulator Based on FPGAs accumulator which comprises of
(Tools / Xilinx ISE) signed soft multiplier and a single
floating point accumulator.

The main objective of this project is

Design of Full Adder and Parity Generator to design a full adder and parity
281 TVMABE215 Based on Reversible Logic generator using reversible logic
(Back End Domains / Core Memories) gates in order to reduce power
dissipation.

The Kogge Stone adder is a widely

Design an Area Efficient Kogge Stone Adder used high-speed parallel adder, and
282 TVMABE213 using Pass Transistor Logic the proposed design aims to reduce
(Back End Domains / Low Power VLSI) its area overhead while maintaining
its performance characteristics.

The Kogge Stone adder is a widely

Design an Area Efficient Kogge Stone Adder used high-speed parallel adder, and
283 TVMABE214 using Pass Transistor Logic the proposed design aims to reduce
(Back End Domains / Transistor Logic) its area overhead while maintaining
its performance characteristics.

The Kogge Stone adder is a widely

Design an Area Efficient Kogge Stone Adder used high-speed parallel adder, and
284 TVPGTO931 using Pass Transistor Logic the proposed design aims to reduce
(Tools / Tanner EDA) its area overhead while maintaining
its performance characteristics.

EFFICIENT MULTIPLIERS DESIGN USING In this paper, design of three

285 TVMAFE554 HYBRID ADDERS different Array, Vedic and booth
(Front End Domains / Arithmetic Core) multipliers are presented, one by

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

using ripple carry adder

(RCA),carry select adder (CSLA)
and ling adder’s logic for addition of
partial product terms in partial
product lines.

The main aim of doing this work is

to neglect the logic blocks when
A Mixed Style Multiplier Architecture for Low
their function is not required which
286 TVMAFE545 Dynamic and Leakage Power Dissipation
tend to decrease latency and area
(Front End Domains / Arithmetic Core)
which are due to transmission
gates.

The main aim of doing this work is

to neglect the logic blocks when
A Mixed Style Multiplier Architecture for Low
their function is not required which
287 TVPGTO932 Dynamic and Leakage Power Dissipation
tend to decrease latency and area
(Tools / Xilinx Vivado)
which are due to transmission
gates.

The main aim of doing this work is

to neglect the logic blocks when
A Mixed Style Multiplier Architecture for Low
their function is not required which
288 TVPGTO933 Dynamic and Leakage Power Dissipation
tend to decrease latency and area
(Tools / Xilinx ISE)
which are due to transmission
gates.

Approximate multiplier using low

Low-Power Compressor-Based Approximate power compressor with error
289 TVMAFE507 Multipliers With Error Correcting Module correcting module is synthesized
(Front End Domains / Arithmetic Core) and simulated using ISE and
working efficiently.

Approximate multiplier using low

Low-Power Compressor-Based Approximate power compressor with error
290 TVMATO1047 Multipliers With Error Correcting Module correcting module is synthesized
(Tools / Xilinx Vivado) and simulated using ISE and
working efficiently.

Approximate multiplier using low

Low-Power Compressor-Based Approximate power compressor with error
291 TVMATO1048 Multipliers With Error Correcting Module correcting module is synthesized
(Tools / Xilinx ISE) and simulated using ISE and
working efficiently.

Approximate multiplier using low

Low-Power Compressor-Based Approximate power compressor with error
292 TVPGTO871 Multipliers With Error Correcting Module correcting module is synthesized
(Tools / Xilinx Vivado) and simulated using ISE and
working efficiently.

Approximate multiplier using low

Low-Power Compressor-Based Approximate power compressor with error
293 TVPGTO872 Multipliers With Error Correcting Module correcting module is synthesized
(Tools / Xilinx ISE) and simulated using ISE and
working efficiently.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
294 TVMABE121
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Back End Domains / Low Power VLSI) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
295 TVMATO718
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Tools / Tanner EDA) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
296 TVMATO719
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Tools / Cadence EDA) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
297 TVPGBE117
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Back End Domains / Low Power VLSI) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
298 TVPGTO579
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Tools / Cadence EDA) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

In this project, an energy-ef?cient

retentive True Single-Phase-Clocked
Low-Power Retentive True (TSPC) FF is proposed. With the
Single-Phase-Clocked Flip-Flop With employment of input-aware pre
299 TVPGTO580
Redundant-Precharge-Free Operation charge scheme, the proposed TSPC
(Tools / Tanner EDA) FF pre charge only when necessary.
By adopting this technique, power
consumption is minimized.

Design of Ultra-Low Power Consumption The main aim of this work is to

300 TVMAFE381
Approximate 4-2 Compressors Based on the reduce the power in multiplier by

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Compensation Characteristic using different 4:2 compressors

(Front End Domains / Arithmetic Core) designs

Design of Ultra-Low Power Consumption The main aim of this work is to

Approximate 4-2 Compressors Based on the reduce the power in multiplier by
301 TVMATO734
Compensation Characteristic using different 4:2 compressors
(Tools / Xilinx Vivado) designs

Design of Ultra-Low Power Consumption The main aim of this work is to

Approximate 4-2 Compressors Based on the reduce the power in multiplier by
302 TVMATO735
Compensation Characteristic using different 4:2 compressors
(Tools / Xilinx ISE) designs

Design of Ultra-Low Power Consumption The main aim of this work is to

Approximate 4-2 Compressors Based on the reduce the power in multiplier by
303 TVPGFE306
Compensation Characteristic using different 4:2 compressors
(Front End Domains / Arithmetic Core) designs

Design of Ultra-Low Power Consumption The main aim of this work is to

Approximate 4-2 Compressors Based on the reduce the power in multiplier by
304 TVPGTO598
Compensation Characteristic using different 4:2 compressors
(Tools / Xilinx Vivado) designs

Design of Ultra-Low Power Consumption The main aim of this work is to

Approximate 4-2 Compressors Based on the reduce the power in multiplier by
305 TVPGTO599
Compensation Characteristic using different 4:2 compressors
(Tools / Xilinx ISE) designs

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift to minimize the delay and power by
306 TVMABE155 register with 2PASCL Adiabatic logic implementing the Bi-Directional shift
(Back End Domains / Cadence EDA) register with 2PASCL Adiabatic
logic.

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift to minimize the delay and power by
307 TVMABE156 register with 2PASCL Adiabatic logic implementing the Bi-Directional shift
(Back End Domains / Low Power VLSI) register with 2PASCL Adiabatic
logic.

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift to minimize the delay and power by
308 TVMATO791 register with 2PASCL Adiabatic logic implementing the Bi-Directional shift
(Tools / Tanner EDA) register with 2PASCL Adiabatic
logic.

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift to minimize the delay and power by
309 TVMATO792 register with 2PASCL Adiabatic logic implementing the Bi-Directional shift
(Tools / Cadence EDA) register with 2PASCL Adiabatic
logic.

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift
to minimize the delay and power by
310 TVPGTO664 register with 2PASCL Adiabatic logic
implementing the Bi-Directional shift
(Tools / Tanner EDA)
register with 2PASCL Adiabatic

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

logic.

The main objective of this paper is

Implementation of 4-Bit Bi-Directional Shift to minimize the delay and power by
311 TVPGTO665 register with 2PASCL Adiabatic logic implementing the Bi-Directional shift
(Tools / Cadence EDA) register with 2PASCL Adiabatic
logic.

This paper aims to implement a full

adder sum circuit and carry circuit is
designed using Energy-Efficient
Secure Positive Feedback Adiabatic
Logic (EE-SPFAL). Energy-Efficient
Approximate Adiabatic Logic for Low-Power Secure Positive Feedback Adiabatic
312 TVMABE129 and Secure Edge Computing Logic (EE-SPFAL) is an adiabatic
(Back End Domains / Low Power VLSI) logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

This paper aims to implement a full

adder sum circuit and carry circuit is
designed using Energy-Efficient
Secure Positive Feedback Adiabatic
Logic (EE-SPFAL). Energy-Efficient
Approximate Adiabatic Logic for Low-Power Secure Positive Feedback Adiabatic
313 TVMATO774 and Secure Edge Computing Logic (EE-SPFAL) is an adiabatic
(Tools / Tanner EDA) logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

This paper aims to implement a full

adder sum circuit and carry circuit is
designed using Energy-Efficient
Secure Positive Feedback Adiabatic
Logic (EE-SPFAL). Energy-Efficient
Approximate Adiabatic Logic for Low-Power Secure Positive Feedback Adiabatic
314 TVMATO775 and Secure Edge Computing Logic (EE-SPFAL) is an adiabatic
(Tools / Cadence EDA) logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

This paper aims to implement a full

adder sum circuit and carry circuit is
Approximate Adiabatic Logic for Low-Power
designed using Energy-Efficient
315 TVPGBE126 and Secure Edge Computing
Secure Positive Feedback Adiabatic
(Back End Domains / Low Power VLSI)
Logic (EE-SPFAL). Energy-Efficient
Secure Positive Feedback Adiabatic

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Logic (EE-SPFAL) is an adiabatic

logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

This paper aims to implement a full

adder sum circuit and carry circuit is
designed using Energy-Efficient
Secure Positive Feedback Adiabatic
Logic (EE-SPFAL). Energy-Efficient
Approximate Adiabatic Logic for Low-Power Secure Positive Feedback Adiabatic
316 TVPGTO638 and Secure Edge Computing Logic (EE-SPFAL) is an adiabatic
(Tools / Cadence EDA) logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

This paper aims to implement a full

adder sum circuit and carry circuit is
designed using Energy-Efficient
Secure Positive Feedback Adiabatic
Logic (EE-SPFAL). Energy-Efficient
Approximate Adiabatic Logic for Low-Power Secure Positive Feedback Adiabatic
317 TVPGTO639 and Secure Edge Computing Logic (EE-SPFAL) is an adiabatic
(Tools / Tanner EDA) logic family which is suitable to
design low-power and secure
adiabatic circuit. EE-SPFAL has
uniform power consumption and is
secure against Differential Power
Analysis (DPA) based attacks.

The main aim of this project is to

A Low-Power Timing-Error-Tolerant Circuit by implement the timing error tolerant
318 TVMABE112 Controlling a Clock circuit using time borrow scheme for
(Back End Domains / Transistor Logic) reducing the setup timing violations
generated in the next stage

The main aim of this project is to

A Low-Power Timing-Error-Tolerant Circuit by implement the timing error tolerant
319 TVMATO708 Controlling a Clock circuit using time borrow scheme for
(Tools / Tanner EDA) reducing the setup timing violations
generated in the next stage

The main aim of this project is to

A Low-Power Timing-Error-Tolerant Circuit by implement the timing error tolerant
320 TVMATO709 Controlling a Clock circuit using time borrow scheme for
(Tools / Cadence EDA) reducing the setup timing violations
generated in the next stage

A Low-Power Timing-Error-Tolerant Circuit by The main aim of this project is to

321 TVPGBE110
Controlling a Clock implement the timing error tolerant

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

circuit using time borrow scheme for

(Back End Domains / Transistor Logic) reducing the setup timing violations
generated in the next stage

The main aim of this project is to

A Low-Power Timing-Error-Tolerant Circuit by implement the timing error tolerant
322 TVPGTO569 Controlling a Clock circuit using time borrow scheme for
(Tools / Cadence EDA) reducing the setup timing violations
generated in the next stage

The main aim of this project is to

A Low-Power Timing-Error-Tolerant Circuit by implement the timing error tolerant
323 TVPGTO570 Controlling a Clock circuit using time borrow scheme for
(Tools / Tanner EDA) reducing the setup timing violations
generated in the next stage

Fixed-Posit: A Floating-Point Representation

324 TVMAFE426 for Error-Resilient Applications
(Front End Domains / Cadence EDA)

Fixed-Posit: A Floating-Point Representation

325 TVMAFE427 for Error-Resilient Applications
(Front End Domains / Arithmetic Core)

Fixed-Posit: A Floating-Point Representation

326 TVMATO841 for Error-Resilient Applications
(Tools / Xilinx Vivado)

Fixed-Posit: A Floating-Point Representation

327 TVMATO842 for Error-Resilient Applications
(Tools / Xilinx ISE)

Fixed-Posit: A Floating-Point Representation

328 TVPGTO714 for Error-Resilient Applications
(Tools / Xilinx Vivado)

Fixed-Posit: A Floating-Point Representation

329 TVPGTO715 for Error-Resilient Applications
(Tools / Xilinx ISE)

Implementation of FPGA signed multiplier

330 TVMAFE429 using different adders
(Front End Domains / Arithmetic Core)

Implementation of FPGA signed multiplier

331 TVMATO845 using different adders
(Tools / Xilinx Vivado)

Implementation of FPGA signed multiplier

332 TVMATO846 using different adders
(Tools / Xilinx ISE)

Implementation of FPGA signed multiplier

333 TVPGTO718 using different adders
(Tools / Xilinx Vivado)

334 TVPGTO719 Implementation of FPGA signed multiplier

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

using different adders

(Tools / Xilinx ISE)

In this project, the 32 nm

CNTFET-based Ternary Half Adder
(THA) and Multiplier (TMUL) circuits
use novel ternary unary operator
Novel Ternary Adder and Multiplier Designs
circuits and implement two power
335 TVMATO860 Without Using Decoders or Encoders
supplies Vdd and Vdd/2 without
(Tools / H-Spice)
using any ternary decoders, basic
logic gates, or encoders to minimize
the number of used transistors and
improve the energy efficiency.

In this project, the 32 nm

CNTFET-based Ternary Half Adder
(THA) and Multiplier (TMUL) circuits
use novel ternary unary operator
Novel Ternary Adder and Multiplier Designs
circuits and implement two power
336 TVMABE127 Without Using Decoders or Encoders
supplies Vdd and Vdd/2 without
(Back End Domains / Transistor Logic)
using any ternary decoders, basic
logic gates, or encoders to minimize
the number of used transistors and
improve the energy efficiency.

In this project, the 32 nm

CNTFET-based Ternary Half Adder
(THA) and Multiplier (TMUL) circuits
use novel ternary unary operator
Novel Ternary Adder and Multiplier Designs
circuits and implement two power
337 TVPGBE124 Without Using Decoders or Encoders
supplies Vdd and Vdd/2 without
(Back End Domains / Transistor Logic)
using any ternary decoders, basic
logic gates, or encoders to minimize
the number of used transistors and
improve the energy efficiency.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
338 TVMAFE447 Architecture Using Modular Approach so that the number of half adders
(Front End Domains / Arithmetic Core) and stages of reduction can be
minimized.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
339 TVMATO878 Architecture Using Modular Approach so that the number of half adders
(Tools / Xilinx Vivado) and stages of reduction can be
minimized.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
340 TVMATO879 Architecture Using Modular Approach so that the number of half adders
(Tools / Xilinx ISE) and stages of reduction can be
minimized.

Design of Low-Power Wallace Tree Multiplier The main objective of this project is
341 TVMATO880
Architecture Using Modular Approach to design a counter based multiplier

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S.No Project Code Project Name Objective

so that the number of half adders

(Tools / Cadence EDA) and stages of reduction can be
minimized.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
342 TVPGTO745 Architecture Using Modular Approach so that the number of half adders
(Tools / Xilinx Vivado) and stages of reduction can be
minimized.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
343 TVPGTO746 Architecture Using Modular Approach so that the number of half adders
(Tools / Xilinx ISE) and stages of reduction can be
minimized.

The main objective of this project is

Design of Low-Power Wallace Tree Multiplier to design a counter based multiplier
344 TVPGTO747 Architecture Using Modular Approach so that the number of half adders
(Tools / Cadence EDA) and stages of reduction can be
minimized.

Analysis of High Speed Hybrid Full Adder

345 TVMABE158
(Back End Domains / Cadence EDA)

Analysis of High Speed Hybrid Full Adder

346 TVMABE159
(Back End Domains / Transistor Logic)

Analysis of High Speed Hybrid Full Adder

347 TVMATO887
(Tools / H-Spice)

Analysis of High Speed Hybrid Full Adder

348 TVMATO888
(Tools / Tanner EDA)

Analysis of High Speed Hybrid Full Adder

349 TVMATO889
(Tools / Cadence EDA)

Analysis of High Speed Hybrid Full Adder

350 TVPGTO753
(Tools / Tanner EDA)

Analysis of High Speed Hybrid Full Adder

351 TVPGTO754
(Tools / Cadence EDA)

The main aim of this project is to

Power Efficient Clock Pulsed D Flip Flop Using
implement the clock pulsed D flip
352 TVMABE161 Transmission Gate
flop using Transmisson gate to
(Back End Domains / Low Power VLSI)
reduce the power

The main aim of this project is to

Power Efficient Clock Pulsed D Flip Flop Using
implement the clock pulsed D flip
353 TVMATO918 Transmission Gate
flop using Transmisson gate to
(Tools / Tanner EDA)
reduce the power

The main aim of this project is to

Power Efficient Clock Pulsed D Flip Flop Using
implement the clock pulsed D flip
354 TVMATO919 Transmission Gate
flop using Transmisson gate to
(Tools / Cadence EDA)
reduce the power

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S.No Project Code Project Name Objective

The main aim of this project is to

Power Efficient Clock Pulsed D Flip Flop Using
implement the clock pulsed D flip
355 TVMATO920 Transmission Gate
flop using Transmisson gate to
(Tools / LT-Spice)
reduce the power

The main aim of this project is to

Power Efficient Clock Pulsed D Flip Flop Using
implement the clock pulsed D flip
356 TVPGTO777 Transmission Gate
flop using Transmisson gate to
(Tools / Tanner EDA)
reduce the power

The main aim of the IIR design is

realized by parallel–pipeline-based
High performance IIR filter implementation on finite impulse response (FIR) filter.
357 TVMAFE476 FPGA The FIR filters have excellent
(Front End Domains / DSP Core) characteristics such as high stability,
linear phase response and fewer
finite precision errors.

The main aim of the IIR design is

realized by parallel–pipeline-based
High performance IIR filter implementation on finite impulse response (FIR) filter.
358 TVMATO925 FPGA The FIR filters have excellent
(Tools / Xilinx Vivado) characteristics such as high stability,
linear phase response and fewer
finite precision errors.

The main aim of the IIR design is

realized by parallel–pipeline-based
High performance IIR filter implementation on finite impulse response (FIR) filter.
359 TVMATO926 FPGA The FIR filters have excellent
(Tools / Xilinx ISE) characteristics such as high stability,
linear phase response and fewer
finite precision errors.

The main aim of the IIR design is

realized by parallel–pipeline-based
High performance IIR filter implementation on finite impulse response (FIR) filter.
360 TVPGTO782 FPGA The FIR filters have excellent
(Tools / Xilinx Vivado) characteristics such as high stability,
linear phase response and fewer
finite precision errors.

The main aim of the IIR design is

realized by parallel–pipeline-based
High performance IIR filter implementation on finite impulse response (FIR) filter.
361 TVPGTO783 FPGA The FIR filters have excellent
(Tools / Xilinx ISE) characteristics such as high stability,
linear phase response and fewer
finite precision errors.

High Performance Reconfigurable Viterbi

362 TVMAFE479 Decoder Design for Multi-Standard Receiver
(Front End Domains / DSP Core)

High Performance Reconfigurable Viterbi

363 TVMATO937
Decoder Design for Multi-Standard Receiver

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S.No Project Code Project Name Objective

(Tools / Xilinx Vivado)

High Performance Reconfigurable Viterbi

364 TVMATO938 Decoder Design for Multi-Standard Receiver
(Tools / Xilinx ISE)

High Performance Reconfigurable Viterbi

365 TVPGTO789 Decoder Design for Multi-Standard Receiver
(Tools / Xilinx Vivado)

High Performance Reconfigurable Viterbi

366 TVPGTO790 Decoder Design for Multi-Standard Receiver
(Tools / Xilinx ISE)

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
367 TVMABE143 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Back End Domains / Cadence EDA)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
368 TVMABE144 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Back End Domains / Transistor Logic)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
369 TVMATO784 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Tools / Tanner EDA)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
370 TVMATO785 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Tools / Cadence EDA)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
371 TVPGTO652 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Tools / Cadence EDA)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

This paper presents the 4-bit vedic

multiplier using CMOS and MGDI
A comparative study of 4-bit Vedic multiplier
Techniques. Here, the 4-bit vedic
372 TVPGTO653 using CMOS and MGDI Technology
multiplier is designed using 2-bit
(Tools / Tanner EDA)
vedic multipliers, Ripple Carry
Adders and a Half Adder.

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S.No Project Code Project Name Objective

An Ultra-Low-Voltage Level Shifter With

Embedded Re-Configurable Logic and
373 TVMABE186
Time-Borrowing Latch Technique
(Back End Domains / Transistor Logic)

An Ultra-Low-Voltage Level Shifter With

Embedded Re-Configurable Logic and
374 TVMATO1037
Time-Borrowing Latch Technique
(Tools / Tanner EDA)

An Ultra-Low-Voltage Level Shifter With

Embedded Re-Configurable Logic and
375 TVPGTO864
Time-Borrowing Latch Technique
(Tools / Tanner EDA)

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
376 TVMABE113 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Back End Domains / Transistor Logic)
CMOS process to perform the True
random number generation.

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
377 TVMABE114 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Back End Domains / Low Power VLSI)
CMOS process to perform the True
random number generation.

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
378 TVMATO710 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Tools / Tanner EDA)
CMOS process to perform the True
random number generation.

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
379 TVMATO711 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Tools / Cadence EDA)
CMOS process to perform the True
random number generation.

A New Energy-Efficient and High Throughput The main objective of this work is to
Two-Phase Multi-Bit per Cycle Ring achieve the high throughput of
380 TVPGTO571 Oscillator-Based True Random Number Random number generation and
Generator make the system to be energy
(Tools / Cadence EDA) efficient. The proposed circuit is

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

designed in a standard 45 nm 1.2 V

CMOS process to perform the True
random number generation.

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
381 TVPGTO572 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Tools / Tanner EDA)
CMOS process to perform the True
random number generation.

The main objective of this work is to

achieve the high throughput of
A New Energy-Efficient and High Throughput
Random number generation and
Two-Phase Multi-Bit per Cycle Ring
make the system to be energy
382 TVPGBE111 Oscillator-Based True Random Number
efficient. The proposed circuit is
Generator
designed in a standard 45 nm 1.2 V
(Back End Domains / Transistor Logic)
CMOS process to perform the True
random number generation.

Low-Power Ternary Multiplication using

383 TVMABE131 Approximate Computing
(Back End Domains / Low Power VLSI)

Low-Power Ternary Multiplication using

384 TVPGBE128 Approximate Computing
(Back End Domains / Low Power VLSI)

Novel Memristor-based Nonvolatile D Latch

385 TVMABE133 and Flip-flop Designs
(Back End Domains / Core Memories)

Novel Memristor-based Nonvolatile D Latch

386 TVPGBE131 and Flip-flop Designs
(Back End Domains / Core Memories)

Novel Memristor-based Nonvolatile D Latch

387 TVMATO866 and Flip-flop Designs
(Tools / LT-Spice)

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC Logic Unit (ALU) and Multiplier and
388 TVMAFE380 Processor Using Vedic Mathematics Accumulator (MAC) is implemented
(Front End Domains / DSP Core) using Vedic Sutras reduce
computation delay and improve the
performance of the RISC design.

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC
Logic Unit (ALU) and Multiplier and
389 TVMATO732 Processor Using Vedic Mathematics
Accumulator (MAC) is implemented
(Tools / Xilinx Vivado)
using Vedic Sutras reduce
computation delay and improve the

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S.No Project Code Project Name Objective

performance of the RISC design.

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC Logic Unit (ALU) and Multiplier and
390 TVMATO733 Processor Using Vedic Mathematics Accumulator (MAC) is implemented
(Tools / Xilinx ISE) using Vedic Sutras reduce
computation delay and improve the
performance of the RISC design.

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC Logic Unit (ALU) and Multiplier and
391 TVPGFE305 Processor Using Vedic Mathematics Accumulator (MAC) is implemented
(Front End Domains / DSP Core) using Vedic Sutras reduce
computation delay and improve the
performance of the RISC design.

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC Logic Unit (ALU) and Multiplier and
392 TVPGTO596 Processor Using Vedic Mathematics Accumulator (MAC) is implemented
(Tools / Xilinx Vivado) using Vedic Sutras reduce
computation delay and improve the
performance of the RISC design.

The main aim of this paper is that

the multiplier unit in Arithmetic and
Design and Verification of 16 bit RISC Logic Unit (ALU) and Multiplier and
393 TVPGTO597 Processor Using Vedic Mathematics Accumulator (MAC) is implemented
(Tools / Xilinx ISE) using Vedic Sutras reduce
computation delay and improve the
performance of the RISC design.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for approximate adders for FPGAs. We
394 TVMAFE392 FPGAs are implementing the approximate
(Front End Domains / Arithmetic Core) adders based on optimized LUT
based designs at the LSP of the
adder implementation.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for approximate adders for FPGAs. We
395 TVMATO756 FPGAs are implementing the approximate
(Tools / Xilinx Vivado) adders based on optimized LUT
based designs at the LSP of the
adder implementation.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for
approximate adders for FPGAs. We
396 TVMATO757 FPGAs
are implementing the approximate
(Tools / Xilinx ISE)
adders based on optimized LUT
based designs at the LSP of the

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

adder implementation.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for approximate adders for FPGAs. We
397 TVPGFE317 FPGAs are implementing the approximate
(Front End Domains / Arithmetic Core) adders based on optimized LUT
based designs at the LSP of the
adder implementation.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for approximate adders for FPGAs. We
398 TVPGTO620 FPGAs are implementing the approximate
(Tools / Xilinx Vivado) adders based on optimized LUT
based designs at the LSP of the
adder implementation.

The main aim of this paper is to

design low error efficient
Low Error Efficient Approximate Adders for approximate adders for FPGAs. We
399 TVPGTO621 FPGAs are implementing the approximate
(Tools / Xilinx ISE) adders based on optimized LUT
based designs at the LSP of the
adder implementation.

Inexact Signed Wallace Tree Multiplier Design

400 TVMAFE391 Using Reversible Logic
(Front End Domains / Arithmetic Core)

Inexact Signed Wallace Tree Multiplier Design

401 TVMATO754 Using Reversible Logic
(Tools / Xilinx Vivado)

Inexact Signed Wallace Tree Multiplier Design

402 TVMATO755 Using Reversible Logic
(Tools / Xilinx ISE)

Inexact Signed Wallace Tree Multiplier Design

403 TVPGFE316 Using Reversible Logic
(Front End Domains / Arithmetic Core)

Inexact Signed Wallace Tree Multiplier Design

404 TVPGTO618 Using Reversible Logic
(Tools / Xilinx Vivado)

Inexact Signed Wallace Tree Multiplier Design

405 TVPGTO619 Using Reversible Logic
(Tools / Xilinx ISE)

High-speed and low-cost carry select adders

utilizing new optimized add-one circuit and
406 TVMAFE492
multiplexer-based logic
(Front End Domains / Arithmetic Core)

High-speed and low-cost carry select adders

407 TVMATO973
utilizing new optimized add-one circuit and

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S.No Project Code Project Name Objective

multiplexer-based logic
(Tools / Xilinx Vivado)

High-speed and low-cost carry select adders

utilizing new optimized add-one circuit and
408 TVMATO974
multiplexer-based logic
(Tools / Xilinx ISE)

High-speed and low-cost carry select adders

utilizing new optimized add-one circuit and
409 TVPGTO812
multiplexer-based logic
(Tools / Xilinx Vivado)

High-speed and low-cost carry select adders

utilizing new optimized add-one circuit and
410 TVPGTO813
multiplexer-based logic
(Tools / Xilinx ISE)

The primary objective appears to be

High speed Dadda multiplier using 4:2 designing a high-speed Dadda
411 TVMAFE624 compressor multiplier circuit optimized for low
(Front End Domains / Arithmetic Core) power consumption and compact
design

By creating a DADDA multiplier

using approximate 4-2 compressors,
this work aims to contribute to the
development of more sustainable
DESIGN AND ANALYSIS OF DADDA
and adaptable digital systems. This
MULTIPLIER USING APPROXIMATE 4-2
412 TVMAFE619 design could enable the widespread
COMPRESSOR
adoption of edge computing and IoT
(Front End Domains / Arithmetic Core)
devices in various applications
where precise arithmetic is not
always necessary but energy
efficiency is paramount.

The main aim of this project is

1-Bit Full Subtractor using Zipper Logic design a full subtractor using zipper
413 TVMABE227
(Back End Domains / Low Power VLSI) logic in order to reduce power
consumption.

The technique of Vedic more

multiple is Urdhva-Triyakbhyam
VLSI IMPLEMENTATION OF VEDIC (Vertically and Crosswise) sutra.
414 TVMAFE565 MULTIPLIER This sutra was customarily used in
(Front End Domains / Arithmetic Core) the ancient history of Indian culture
to multiply two decimal numbers
with minimum time.

This work presents and analyses

INDUCTOR LESS MULTI-MODE RF-CMOS
the design of a multi-mode Low
LOW NOISE AMPLIFIER DEDICATED TO
415 TVMABE223 Noise Amplifier (LNA) dedicated to
ULTRA LOW POWER APPLICATIONS
2.4 GHz Wireless Sensor Network
(Back End Domains / Transistor Logic)
(WSN) applications.

416 TVMABE224 INDUCTOR LESS MULTI-MODE RF-CMOS This work presents and analyses

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S.No Project Code Project Name Objective

the design of a multi-mode Low

LOW NOISE AMPLIFIER DEDICATED TO
Noise Amplifier (LNA) dedicated to
ULTRA LOW POWER APPLICATIONS
2.4 GHz Wireless Sensor Network
(Back End Domains / Transistor Logic)
(WSN) applications.

In this work ,we advocate that these

HIGH-PERFORMANCE ACCURATE AND
soft multiplier IP cores for FPGAs
APPROXIMATE MULTIPLIERS FOR
417 TVMAFE555 still need better designs to provide
FPGA-BASED HARDWARE ACCELERATORS
high-performance and resource
(Front End Domains / Arithmetic Core)
efficiency.

In this work ,we advocate that these

HIGH-PERFORMANCE ACCURATE AND
soft multiplier IP cores for FPGAs
APPROXIMATE MULTIPLIERS FOR
418 TVMAFE556 still need better designs to provide
FPGA-BASED HARDWARE ACCELERATORS
high-performance and resource
(Front End Domains / DSP Core)
efficiency.

In this project, three novel

approximate 4-2 compressors are
DESIGN OF LOWER POWER
proposed and utilized in 8-bit
CONSUMPTION APPROXIMATE 4 : 2
multipliers. Meanwhile, an
COMPRESSOR USING BOOTH MULTIPLIER
419 TVMAFE551 error-correcting module (ECM) is
BASED ON THE COMPENSATION
presented to promote the error
CHARACTERISTICS
performance of approximate
(Front End Domains / Arithmetic Core)
multiplier with the proposed 4-2
compressors on booth multiplier.

This project proposes the design of

Design of 6T, 8T & 10T ternary SRAM cells
420 TVMABE218 a ternary inverter that uses low
(Back End Domains / Low Power VLSI)
current as input voltage is VDD/2.

An Efficient Modified Distributed Arithmetic

421 TVMAFE371 Architecture Suitable for FIR Filter
(Front End Domains / DSP Core)

An Efficient Modified Distributed Arithmetic

422 TVMATO696 Architecture Suitable for FIR Filter
(Tools / Xilinx Vivado)

An Efficient Modified Distributed Arithmetic

423 TVMATO697 Architecture Suitable for FIR Filter
(Tools / Xilinx ISE)

An Efficient Modified Distributed Arithmetic

424 TVPGTO559 Architecture Suitable for FIR Filter
(Tools / Xilinx Vivado)

An Efficient Modified Distributed Arithmetic

425 TVPGTO560 Architecture Suitable for FIR Filter
(Tools / Xilinx ISE)

An Efficient Modified Distributed Arithmetic

426 TVPGFE296 Architecture Suitable for FIR Filter
(Front End Domains / DSP Core)

Accuracy-Configurable Radix-4 Adder with a

427 TVMABE125
Dynamic Output Modification Scheme

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S.No Project Code Project Name Objective

(Back End Domains / Transistor Logic)

Accuracy-Configurable Radix-4 Adder with a

428 TVMATO772 Dynamic Output Modification Scheme
(Tools / Tanner EDA)

Accuracy-Configurable Radix-4 Adder with a

429 TVMATO773 Dynamic Output Modification Scheme
(Tools / Cadence EDA)

Accuracy-Configurable Radix-4 Adder with a

430 TVPGBE122 Dynamic Output Modification Scheme
(Back End Domains / Transistor Logic)

Accuracy-Configurable Radix-4 Adder with a

431 TVPGTO636 Dynamic Output Modification Scheme
(Tools / Cadence EDA)

Accuracy-Configurable Radix-4 Adder with a

432 TVPGTO637 Dynamic Output Modification Scheme
(Tools / Tanner EDA)

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
433 TVPGBE120
(Back End Domains / Transistor Logic) ADC using Threshed hold inverter
quantizer based comparator.

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
434 TVPGTO585
(Tools / Cadence EDA) ADC using Threshed hold inverter
quantizer based comparator.

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
435 TVPGTO586
(Tools / Tanner EDA) ADC using Threshed hold inverter
quantizer based comparator.

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
436 TVMABE124
(Back End Domains / Transistor Logic) ADC using Threshed hold inverter
quantizer based comparator.

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
437 TVMATO724
(Tools / Tanner EDA) ADC using Threshed hold inverter
quantizer based comparator.

The main aim of this project is to

TIQ flash ADC with threshold compensation analyze the performance of flash
438 TVMATO725
(Tools / Cadence EDA) ADC using Threshed hold inverter
quantizer based comparator.

The main of this project is to reduce

BTI and Soft-Error Tolerant Voltage
the delay and NBTI effects by using
439 TVMABE118 Bootstrapped Schmitt Trigger Circuit
N-mos transistors in Schmitt trigger
(Back End Domains / Transistor Logic)
design

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S.No Project Code Project Name Objective

The main of this project is to reduce

BTI and Soft-Error Tolerant Voltage
the delay and NBTI effects by using
440 TVMATO714 Bootstrapped Schmitt Trigger Circuit
N-mos transistors in Schmitt trigger
(Tools / Tanner EDA)
design

The main of this project is to reduce

BTI and Soft-Error Tolerant Voltage
the delay and NBTI effects by using
441 TVPGBE113 Bootstrapped Schmitt Trigger Circuit
N-mos transistors in Schmitt trigger
(Back End Domains / Transistor Logic)
design

The main of this project is to reduce

BTI and Soft-Error Tolerant Voltage
the delay and NBTI effects by using
442 TVPGTO576 Bootstrapped Schmitt Trigger Circuit
N-mos transistors in Schmitt trigger
(Tools / Tanner EDA)
design

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
443 TVMABE115 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Back End Domains / Transistor Logic) pair and extra circuitry in latch stage
respectively

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
444 TVMATO712 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Tools / Tanner EDA) pair and extra circuitry in latch stage
respectively

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
445 TVMATO713 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Tools / Cadence EDA) pair and extra circuitry in latch stage
respectively

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
446 TVPGTO573 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Tools / Cadence EDA) pair and extra circuitry in latch stage
respectively

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
447 TVPGTO574 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Tools / Tanner EDA) pair and extra circuitry in latch stage
respectively

The main aim of this work to reduce

A Three-Stage Comparator and Its Modified the kickback noise and delay in
448 TVPGBE112 Version With Fast Speed and Low Kickback Comparator by using cmos input
(Back End Domains / Transistor Logic) pair and extra circuitry in latch stage
respectively

Low Power High Performance 4-bit Vedic

449 TVMABE130 Multiplier in 32nm
(Back End Domains / Low Power VLSI)

450 TVMATO776 Low Power High Performance 4-bit Vedic

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Multiplier in 32nm
(Tools / Tanner EDA)

Low Power High Performance 4-bit Vedic

451 TVMATO777 Multiplier in 32nm
(Tools / Cadence EDA)

Low Power High Performance 4-bit Vedic

452 TVPGBE127 Multiplier in 32nm
(Back End Domains / Low Power VLSI)

Low Power High Performance 4-bit Vedic

453 TVPGTO640 Multiplier in 32nm
(Tools / Cadence EDA)

Low Power High Performance 4-bit Vedic

454 TVPGTO641 Multiplier in 32nm
(Tools / Tanner EDA)

Rapid Low power Voltage level shifter Utilizing

455 TVMABE123 Regulated Cross Coupled Pull Up Network
(Back End Domains / Low Power VLSI)

Rapid Low power Voltage level shifter Utilizing

456 TVMATO722 Regulated Cross Coupled Pull Up Network
(Tools / Tanner EDA)

Rapid Low power Voltage level shifter Utilizing

457 TVMATO723 Regulated Cross Coupled Pull Up Network
(Tools / Cadence EDA)

Rapid Low power Voltage level shifter Utilizing

458 TVPGBE119 Regulated Cross Coupled Pull Up Network
(Back End Domains / Low Power VLSI)

Rapid Low power Voltage level shifter Utilizing

459 TVPGTO583 Regulated Cross Coupled Pull Up Network
(Tools / Cadence EDA)

Rapid Low power Voltage level shifter Utilizing

460 TVPGTO584 Regulated Cross Coupled Pull Up Network
(Tools / Tanner EDA)

Performance Analysis of Full Adder based on

461 TVMABE122 Domino Logic Technique
(Back End Domains / Transistor Logic)

Performance Analysis of Full Adder based on

462 TVMATO720 Domino Logic Technique
(Tools / Tanner EDA)

Performance Analysis of Full Adder based on

463 TVMATO721 Domino Logic Technique
(Tools / Cadence EDA)

Performance Analysis of Full Adder based on

464 TVPGBE118
Domino Logic Technique

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

(Back End Domains / Transistor Logic)

Performance Analysis of Full Adder based on

465 TVPGTO581 Domino Logic Technique
(Tools / Cadence EDA)

Performance Analysis of Full Adder based on

466 TVPGTO582 Domino Logic Technique
(Tools / Tanner EDA)

SIXOR: Single-Cycle In-Memristor XOR

467 TVPGBE132
(Back End Domains / Core Memories)

SIXOR: Single-Cycle In-Memristor XOR

468 TVPGBE133
(Back End Domains / Core Memories)

Ultra-Efficient Nonvolatile Approximate

Full-Adder with Spin-Hall-Assisted MTJ Cells
469 TVMABE134
for In-Memory Computing Applications
(Back End Domains / Core Memories)

Ultra-Efficient Nonvolatile Approximate

Full-Adder with Spin-Hall-Assisted MTJ Cells
470 TVPGBE134
for In-Memory Computing Applications
(Back End Domains / Core Memories)

Improved High Speed or Low Complexity

Memristor-based Content Addressable
471 TVMABE132
Memory (MCAM) Cell
(Back End Domains / Core Memories)

Improved High Speed or Low Complexity

Memristor-based Content Addressable
472 TVPGBE130
Memory (MCAM) Cell
(Back End Domains / Core Memories)

Design of Approximate Multiplier less DCT with

473 TVMAFE393 CSD Encoding for Image Processing
(Front End Domains / Arithmetic Core)

Design of Approximate Multiplier less DCT with

474 TVMATO758 CSD Encoding for Image Processing
(Tools / Xilinx Vivado)

Design of Approximate Multiplier less DCT with

475 TVMATO759 CSD Encoding for Image Processing
(Tools / Xilinx ISE)

Design of Approximate Multiplier less DCT with

476 TVPGFE318 CSD Encoding for Image Processing
(Front End Domains / Arithmetic Core)

Design of Approximate Multiplier less DCT with

477 TVPGTO622 CSD Encoding for Image Processing
(Tools / Xilinx Vivado)

478 TVPGTO623 Design of Approximate Multiplier less DCT with

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S.No Project Code Project Name Objective

CSD Encoding for Image Processing

(Tools / Xilinx ISE)

Design of Approximate Multiplier less DCT with

479 TVMAOT07 CSD Encoding for Image Processing
(Others / Matlab Interfacing)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
480 TVMAFE395
Architecture
(Front End Domains / DSP Core)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
481 TVMATO762
Architecture
(Tools / Xilinx Vivado)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
482 TVMATO763
Architecture
(Tools / Xilinx ISE)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
483 TVPGFE320
Architecture
(Front End Domains / DSP Core)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
484 TVPGTO626
Architecture
(Tools / Xilinx Vivado)

A Fully Synthesizable All-Digital Phase-Locked

Loop with Parametrized and Portable
485 TVPGTO627
Architecture
(Tools / Xilinx ISE)

CORDIC Architecture For Discrete Cosine

486 TVMAFE367 Transform
(Front End Domains / DSP Core)

CORDIC Architecture For Discrete Cosine

487 TVPGFE291 Transform
(Front End Domains / DSP Core)

CORDIC Architecture For Discrete Cosine

488 TVMATO688 Transform
(Tools / Xilinx Vivado)

CORDIC Architecture For Discrete Cosine

489 TVMATO689 Transform
(Tools / Xilinx ISE)

Designs and implements a

Design and Implementation of Arbitrary Point
dedicated microprocessor
490 TVMAFE397 FFT Based on RISC-V SoC
architecture based on the RISC-V
(Front End Domains / DSP Core)
(the fifth-generation Reduced

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S.No Project Code Project Name Objective

Instruction Set Computing) with only

20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

Designs and implements a

dedicated microprocessor
architecture based on the RISC-V
Design and Implementation of Arbitrary Point
(the fifth-generation Reduced
491 TVMATO766 FFT Based on RISC-V SoC
Instruction Set Computing) with only
(Tools / Xilinx Vivado)
20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

Designs and implements a

dedicated microprocessor
architecture based on the RISC-V
Design and Implementation of Arbitrary Point
(the fifth-generation Reduced
492 TVMATO767 FFT Based on RISC-V SoC
Instruction Set Computing) with only
(Tools / Xilinx ISE)
20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

Designs and implements a

dedicated microprocessor
architecture based on the RISC-V
Design and Implementation of Arbitrary Point
(the fifth-generation Reduced
493 TVPGFE322 FFT Based on RISC-V SoC
Instruction Set Computing) with only
(Front End Domains / DSP Core)
20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

Designs and implements a

dedicated microprocessor
architecture based on the RISC-V
Design and Implementation of Arbitrary Point
(the fifth-generation Reduced
494 TVPGTO630 FFT Based on RISC-V SoC
Instruction Set Computing) with only
(Tools / Xilinx Vivado)
20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

Designs and implements a

dedicated microprocessor
architecture based on the RISC-V
Design and Implementation of Arbitrary Point
(the fifth-generation Reduced
495 TVPGTO631 FFT Based on RISC-V SoC
Instruction Set Computing) with only
(Tools / Xilinx ISE)
20 instructions for arbitrary-point
FFT (Fast Fourier Transform)
algorithm

The Constant Multiplier FFT

496 TVMAFE400
(Front End Domains / DSP Core)

The Constant Multiplier FFT

497 TVMATO770
(Tools / Xilinx Vivado)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The Constant Multiplier FFT

498 TVMATO771
(Tools / Xilinx ISE)

The Constant Multiplier FFT

499 TVPGFE325
(Front End Domains / DSP Core)

The Constant Multiplier FFT

500 TVPGTO634
(Tools / Xilinx Vivado)

The Constant Multiplier FFT

501 TVPGTO635
(Tools / Xilinx ISE)

Design of Very High-Speed Pipeline FIR Filter

502 TVMAFE382 Through Precise Critical Path Analysis
(Front End Domains / DSP Core)

Design of Very High-Speed Pipeline FIR Filter

503 TVMATO736 Through Precise Critical Path Analysis
(Tools / Xilinx Vivado)

Design of Very High-Speed Pipeline FIR Filter

504 TVMATO737 Through Precise Critical Path Analysis
(Tools / Xilinx ISE)

Design of Very High-Speed Pipeline FIR Filter

505 TVPGFE307 Through Precise Critical Path Analysis
(Front End Domains / DSP Core)

Design of Very High-Speed Pipeline FIR Filter

506 TVPGTO600 Through Precise Critical Path Analysis
(Tools / Xilinx Vivado)

Design of Very High-Speed Pipeline FIR Filter

507 TVPGTO601 Through Precise Critical Path Analysis
(Tools / Xilinx ISE)

SAM: A Segmentation based Approximate

508 TVMAFE394 Multiplier for Error Tolerant Applications
(Front End Domains / Arithmetic Core)

SAM: A Segmentation based Approximate

509 TVMATO760 Multiplier for Error Tolerant Applications
(Tools / Xilinx Vivado)

SAM: A Segmentation based Approximate

510 TVMATO761 Multiplier for Error Tolerant Applications
(Tools / Xilinx ISE)

SAM: A Segmentation based Approximate

511 TVPGFE319 Multiplier for Error Tolerant Applications
(Front End Domains / Arithmetic Core)

SAM: A Segmentation based Approximate

512 TVPGTO624 Multiplier for Error Tolerant Applications
(Tools / Xilinx Vivado)

513 TVPGTO625 SAM: A Segmentation based Approximate

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S.No Project Code Project Name Objective

Multiplier for Error Tolerant Applications

(Tools / Xilinx ISE)

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
514 TVMAFE390 efficiency. This paper presents
Truncation
approximate adder design using
(Front End Domains / Arithmetic Core)
Carry prediction logic and constant
truncation.

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
515 TVMATO752 efficiency. This paper presents
Truncation
approximate adder design using
(Tools / Xilinx Vivado)
Carry prediction logic and constant
truncation.

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
516 TVMATO753 efficiency. This paper presents
Truncation
approximate adder design using
(Tools / Xilinx ISE)
Carry prediction logic and constant
truncation.

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
517 TVPGFE315 efficiency. This paper presents
Truncation
approximate adder design using
(Front End Domains / Arithmetic Core)
Carry prediction logic and constant
truncation.

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
518 TVPGTO616 efficiency. This paper presents
Truncation
approximate adder design using
(Tools / Xilinx Vivado)
Carry prediction logic and constant
truncation.

The main aim of this paper is to

improve the computation accuracy
A Novel Approximate Adder Design using Error
while providing excellent hardware
Reduced Carry Prediction and Constant
519 TVPGTO617 efficiency. This paper presents
Truncation
approximate adder design using
(Tools / Xilinx ISE)
Carry prediction logic and constant
truncation.

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
520 TVMAFE379
in MAC Operator
(Front End Domains / Arithmetic Core)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
521 TVMATO730
in MAC Operator
(Tools / Xilinx Vivado)

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
522 TVMATO731
in MAC Operator
(Tools / Xilinx ISE)

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
523 TVPGFE304
in MAC Operator
(Front End Domains / Arithmetic Core)

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
524 TVPGTO594
in MAC Operator
(Tools / Xilinx Vivado)

Design and Analysis of Approximate

Compressors for Balanced Error Accumulation
525 TVPGTO595
in MAC Operator
(Tools / Xilinx ISE)

In this paper, A 2-bit multiplier is

ANALYSIS OF MULTIPLIER USING 20T FULL implemented using novel proposed
526 TVMI102
ADDER full adder. The Hybrid adder
designed using 20Transistors.

By creating an efficient multiplier

design using novel compressors,
this work aims to contribute to the
Approximate Multiplier Design Using Novel
field of digital circuit design,
527 TVMAFE617 Dual-Stage 4 : 2 Compressors
potentially leading to improvements
(Front End Domains / Arithmetic Core)
in various electronic devices and
systems where arithmetic
operations are crucial.

This paper explain genetic algorithm

GENETIC ALGORITHM FOR SOLVING
in brief with the help of flowchart
SIMPLE MATHEMATICAL EQUALITY
528 TVMATO1149 and solve the simple mathematical
PROBLEM
equality problem with the help of
(Tools / Xilinx Vivado)
genetic algorithm.

This paper presents approximate

multipliers which are efficiently
FPGA-Based Multi-Level Approximate
deployed on Field Programmable
Multipliers for High-Performance Error-Resilient
529 TVMATO1157 Gate Arrays (FPGAs) by using
Applications
newly proposed approximate logic
(Tools / Xilinx Vivado)
compressors at different levels of
accuracy.

A Wide-Range Static Current-Free Current The objective is to propose a current

530 TVPGBE162 Mirror-Based LS With Logic Error Detection for mirror-based level shifter (LS) with a
Near-Threshold Operation logic error detection (CMLS-LED),

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S.No Project Code Project Name Objective

which is capable of converting a

(Back End Domains / Low Power VLSI) near-threshold signal to a
super-threshold signal.

By using the forward body biasing,

input feedback capacitor,
A 0.6-V Low-Power Variable-Gain LNA in
current-reuse and multiple-gate
531 TVPGBE161 0.18-um CMOS Technology
topologies, the LNA can achieve low
(Back End Domains / Low Power VLSI)
power consumption, small chip
area, and high linearity.

Design and Implementation of 4-Bit ALU for

In this paper, a novel low-power
Low-Power using Adiabatic Logic based on
532 TVMABE238 adiabatic logic based on CMOS
CMOS
devices has been proposed.
(Back End Domains / Core Memories)

The main objective of this project is

Design of 16-bit SAR ADC
533 TVPGBE152 to design ADC for 16-bit using Flip
(Back End Domains / Transistor Logic)
flop-based SAR Logic

The main objective of this project is

8-Bit ALU Design using m-GDI Technique to reduce the power consumption
534 TVMATO648
(Tools / Cadence EDA) and delay by using GDI technique
for implementing the ALU circuit.

The main objective of this project is

8-Bit ALU Design using m-GDI Technique to reduce the power consumption
535 TVMABA107
(Back End Domains / Transistor Logic) and delay by using GDI technique
for implementing the ALU circuit.

The main objective of this project is

8-Bit ALU Design using m-GDI Technique to reduce the power consumption
536 TVMATO647
(Tools / Tanner EDA) and delay by using GDI technique
for implementing the ALU circuit.

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
537 TVMAFE111 Three-Operand Binary Adder operands binary addition for efficient
(Front End Domains / Arithmetic Core) computation of modular arithmetic
used in cryptography and PRBG
applications

This paper presents the area

efficient N-bit digital comparator and
High-Speed and Area-Efficient Scalable N-bit it was designed with the help of two
538 TVMABE66 Digital Comparator different modules which are
(Back End Domains / Low Power VLSI) comparison evaluation modules
(CEM) and the second module is
the final module (FM).

This paper presents the area

High-Speed and Area-Efficient Scalable N-bit efficient N-bit digital comparator and
539 TVMATO418 Digital Comparator it was designed with the help of two
(Tools / Cadence EDA) different modules which are
comparison evaluation modules

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S.No Project Code Project Name Objective

(CEM) and the second module is

the final module (FM).

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
540 TVPGTO364
MTCMOS glitch-free and contention-free. Thus
(Tools / Cadence EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
541 TVMATO469 Three-Operand Binary Adder operands binary addition for efficient
(Tools / Xilinx Vivado) computation of modular arithmetic
used in cryptography and PRBG
applications

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
542 TVMATO470 Three-Operand Binary Adder operands binary addition for efficient
(Tools / Xilinx ISE) computation of modular arithmetic
used in cryptography and PRBG
applications

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
543 TVPGTO02
MTCMOS glitch-free and contention-free. Thus
(Tools / Tanner EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
544 TVPGTO62 TCAM for Network Packet Routing
addressable memory and it can be
(Tools / Tanner EDA)
reduced by using the continuous
feature of mask data.

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
545 TVPGBE63
MTCMOS glitch-free and contention-free. Thus
(Back End Domains / Cadence EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

A Low-Power High-Speed The main objective of this work is to

546 TVPGBE64 Sense-Amplifier-Based Flip-Flop in 55 nm reduce the power and to increase
MTCMOS the speed of the sense amplifier and

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S.No Project Code Project Name Objective

the latch was designed with a

glitch-free and contention-free. Thus
(Back End Domains / Low Power VLSI) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

This paper presents the area

efficient N-bit digital comparator and
High-Speed and Area-Efficient Scalable N-bit it was designed with the help of two
547 TVMATO419 Digital Comparator different modules which are
(Tools / Tanner EDA) comparison evaluation modules
(CEM) and the second module is
the final module (FM).

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
548 TVMATO450
MTCMOS glitch-free and contention-free. Thus
(Tools / Tanner EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
549 TVMATO449
MTCMOS glitch-free and contention-free. Thus
(Tools / Cadence EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
550 TVMABE49
MTCMOS glitch-free and contention-free. Thus
(Back End Domains / Low Power VLSI) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

The main objective of this work is to

reduce the power and to increase
A Low-Power High-Speed the speed of the sense amplifier and
Sense-Amplifier-Based Flip-Flop in 55 nm the latch was designed with a
551 TVMABE50
MTCMOS glitch-free and contention-free. Thus
(Back End Domains / Cadence EDA) proposed SAFF is a good choice for
replacing master-slave flip-flop in
digital systems

This paper presents the area

efficient N-bit digital comparator and
High-Speed and Area-Efficient Scalable N-bit
it was designed with the help of two
552 TVPGBE66 Digital Comparator
different modules which are
(Back End Domains / Low Power VLSI)
comparison evaluation modules
(CEM) and the second module is

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S.No Project Code Project Name Objective

the final module (FM).

This paper presents the area

efficient N-bit digital comparator and
High-Speed and Area-Efficient Scalable N-bit it was designed with the help of two
553 TVPGTO09 Digital Comparator different modules which are
(Tools / Tanner EDA) comparison evaluation modules
(CEM) and the second module is
the final module (FM).

This paper presents the area

efficient N-bit digital comparator and
High-Speed and Area-Efficient Scalable N-bit it was designed with the help of two
554 TVPGTO350 Digital Comparator different modules which are
(Tools / Cadence EDA) comparison evaluation modules
(CEM) and the second module is
the final module (FM).

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
555 TVMATO426 TCAM for Network Packet Routing
addressable memory and it can be
(Tools / Cadence EDA)
reduced by using the continuous
feature of mask data.

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
556 TVMATO427 TCAM for Network Packet Routing
addressable memory and it can be
(Tools / Tanner EDA)
reduced by using the continuous
feature of mask data.

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
557 TVMABE79 TCAM for Network Packet Routing
addressable memory and it can be
(Back End Domains / Core Memories)
reduced by using the continuous
feature of mask data.

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
558 TVMABE80 TCAM for Network Packet Routing
addressable memory and it can be
(Back End Domains / Cadence EDA)
reduced by using the continuous
feature of mask data.

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
559 TVPGBE80 TCAM for Network Packet Routing
addressable memory and it can be
(Back End Domains / Cadence EDA)
reduced by using the continuous
feature of mask data.

Data Retention based Low Leakage Power The main objective of this paper is
560 TVPGBE81 TCAM for Network Packet Routing to reduce the leakage power for
(Back End Domains / Core Memories) data retention based ternary content

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

addressable memory and it can be

reduced by using the continuous
feature of mask data.

The main objective of this paper is

to reduce the leakage power for
Data Retention based Low Leakage Power
data retention based ternary content
561 TVPGTO61 TCAM for Network Packet Routing
addressable memory and it can be
(Tools / Cadence EDA)
reduced by using the continuous
feature of mask data.

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
562 TVPGFE95 Three-Operand Binary Adder operands binary addition for efficient
(Front End Domains / Arithmetic Core) computation of modular arithmetic
used in cryptography and PRBG
applications

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
563 TVPGTO384 Three-Operand Binary Adder operands binary addition for efficient
(Tools / Xilinx Vivado) computation of modular arithmetic
used in cryptography and PRBG
applications

In this project, a high-speed

area-efficient adder technique is
High-Speed Area-Efficient VLSI Architecture of proposed to perform the three
564 TVPGTO385 Three-Operand Binary Adder operands binary addition for efficient
(Tools / Xilinx ISE) computation of modular arithmetic
used in cryptography and PRBG
applications

The main objective of this paper is

to reduce the error rate and power
in encrypted data encoded by the
RandShift: An Energy-Efficient Fault-Tolerant Advanced Encryption Standard.
565 TVPGTO396 Method in Secure Nonvolatile Main Memory This paper is implemented with the
(Tools / Xilinx Vivado) randomness feature of AES
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

The main objective of this paper is

to reduce the error rate and power
in encrypted data encoded by the
RandShift: An Energy-Efficient Fault-Tolerant Advanced Encryption Standard.
566 TVPGTO397 Method in Secure Nonvolatile Main Memory This paper is implemented with the
(Tools / Xilinx ISE) randomness feature of AES
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

567 TVMATO481 RandShift: An Energy-Efficient Fault-Tolerant The main objective of this paper is

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

to reduce the error rate and power

in encrypted data encoded by the
Advanced Encryption Standard.
Method in Secure Nonvolatile Main Memory This paper is implemented with the
(Tools / Xilinx Vivado) randomness feature of AES
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

The main objective of this paper is

to reduce the error rate and power
in encrypted data encoded by the
RandShift: An Energy-Efficient Fault-Tolerant Advanced Encryption Standard.
568 TVMATO482 Method in Secure Nonvolatile Main Memory This paper is implemented with the
(Tools / Xilinx ISE) randomness feature of AES
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

The main objective of this paper is

to reduce the error rate and power
in encrypted data encoded by the
RandShift: An Energy-Efficient Fault-Tolerant
Advanced Encryption Standard.
Method in Secure Nonvolatile Main Memory
569 TVPGFE102 This paper is implemented with the
(Front End Domains / Communications and
randomness feature of AES
Crypto Core)
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

Floating point arithmetic is a

common operation in advance
Digital Signal Processing (DSP)
64-BIT FLOATING POINT SQUARE ROOT IN
570 TVMI103 applications. This paper explains a
VERILOG
64-bit binary Floating Point Multiplier
(FPM) architecture for square root
arithmetic.

This paper explains a 32-bit binary

Design of Low-Area and High Speed Pipelined
Floating Point Multiplier (FPM)
571 TVPGFE328 Single Precision Floating Point Multiplier
architecture using an area efficient
(Front End Domains / Arithmetic Core)
array multiplier.

This project presents a compact

power-efficient CMOS fourth-order
0.3-V Nanopower Biopotential Low-Pass Filter
572 TVMABE216 low-pass filter suitable for
(Back End Domains / Low Power VLSI)
electrocardiogram (ECG) acquisition
systems.

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
573 TVPGBE70 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Back End Domains / Low Power VLSI) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
574 TVMABE70 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Back End Domains / Low Power VLSI) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
575 TVPGTO353 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Tools / Cadence EDA) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
576 TVMATO422 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Tools / Cadence EDA) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
577 TVMATO423 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Tools / Tanner EDA) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

The main objective of this work is to

reduce power for Voltage level
Double Current Limiter High-Performance shifter. The proposed Current limiter
578 TVPGTO06 Voltage-Level Shifter for IoT Applications circuit is designed using 130nm
(Tools / Tanner EDA) CMOS technology to perform the
voltage level shifting from 0.15V to
1.25V.

The main objective of this project is

to implement a MAC architecture
with Low power & reduced delay.
A High-Performance Multiply-Accumulate Unit
The MAC unit was designed with
by Integrating Additions and Accumulations
579 TVMAFE91 mainly partial product generation
into Partial Product Reduction Process
and Accumulation units. Hence the
(Front End Domains / DSP Core)
delay can be reduced by integrating
a part of additions into the partial
product reduction (PPR) process

The main objective of this project is

A High-Performance Multiply-Accumulate Unit to implement a MAC architecture
by Integrating Additions and Accumulations with Low power & reduced delay.
580 TVPGFE117
into Partial Product Reduction Process The MAC unit was designed with
(Front End Domains / DSP Core) mainly partial product generation
and Accumulation units. Hence the

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

delay can be reduced by integrating

a part of additions into the partial
product reduction (PPR) process

The main objective of this project is

to implement a MAC architecture
with Low power & reduced delay.
A High-Performance Multiply-Accumulate Unit
The MAC unit was designed with
by Integrating Additions and Accumulations
581 TVPGTO417 mainly partial product generation
into Partial Product Reduction Process
and Accumulation units. Hence the
(Tools / Xilinx Vivado)
delay can be reduced by integrating
a part of additions into the partial
product reduction (PPR) process

The main objective of this project is

to implement a MAC architecture
with Low power & reduced delay.
A High-Performance Multiply-Accumulate Unit
The MAC unit was designed with
by Integrating Additions and Accumulations
582 TVPGTO418 mainly partial product generation
into Partial Product Reduction Process
and Accumulation units. Hence the
(Tools / Xilinx ISE)
delay can be reduced by integrating
a part of additions into the partial
product reduction (PPR) process

The main objective of this project is

to implement a MAC architecture
with Low power & reduced delay.
A High-Performance Multiply-Accumulate Unit
The MAC unit was designed with
by Integrating Additions and Accumulations
583 TVMATO502 mainly partial product generation
into Partial Product Reduction Process
and Accumulation units. Hence the
(Tools / Xilinx Vivado)
delay can be reduced by integrating
a part of additions into the partial
product reduction (PPR) process

The main objective of this project is

to implement a MAC architecture
with Low power & reduced delay.
A High-Performance Multiply-Accumulate Unit
The MAC unit was designed with
by Integrating Additions and Accumulations
584 TVMATO503 mainly partial product generation
into Partial Product Reduction Process
and Accumulation units. Hence the
(Tools / Xilinx ISE)
delay can be reduced by integrating
a part of additions into the partial
product reduction (PPR) process

Effective Low Leakage 6T and 8T FinFET

SRAMs: Using Cells With Reverse-Biased
585 TVMABE169 FinFETs, Near-Threshold Operation, and
Power Gating
(Back End Domains / Core Memories)

Effective Low Leakage 6T and 8T FinFET

SRAMs: Using Cells With Reverse-Biased
586 TVMATO954 FinFETs, Near-Threshold Operation, and
Power Gating
(Tools / H-Spice)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Fault Tolerant Reversible Full Adder Design

587 TVMABE166 Using Gate Diffusion Input
(Back End Domains / Transistor Logic)

Fault Tolerant Reversible Full Adder Design

588 TVMATO944 Using Gate Diffusion Input
(Tools / Tanner EDA)

Fault Tolerant Reversible Full Adder Design

589 TVPGTO794 Using Gate Diffusion Input
(Tools / Tanner EDA)

A 32-bit Integer Division Algorithm Based on

590 TVMAFE470 Priority Encoder
(Front End Domains / Arithmetic Core)

A 32-bit Integer Division Algorithm Based on

591 TVMAFE471 Priority Encoder
(Front End Domains / Communications)

A 32-bit Integer Division Algorithm Based on

592 TVMATO912 Priority Encoder
(Tools / Xilinx Vivado)

A 32-bit Integer Division Algorithm Based on

593 TVMATO913 Priority Encoder
(Tools / Xilinx ISE)

A 32-bit Integer Division Algorithm Based on

594 TVPGTO771 Priority Encoder
(Tools / Xilinx Vivado)

A 32-bit Integer Division Algorithm Based on

595 TVPGTO772 Priority Encoder
(Tools / Xilinx ISE)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
596 TVMAFE452
Improved Reliability
(Front End Domains / Arithmetic Core)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
597 TVMAFE453
Improved Reliability
(Front End Domains / Communications)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
598 TVMATO890
Improved Reliability
(Tools / Xilinx Vivado)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
599 TVMATO891
Improved Reliability
(Tools / Xilinx ISE)

600 TVMATO892 Design of A Ring Oscillator Based PUF with

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Enhanced Challenge Response pair and

Improved Reliability
(Tools / Cadence EDA)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
601 TVPGTO755
Improved Reliability
(Tools / Xilinx Vivado)

Design of A Ring Oscillator Based PUF with

Enhanced Challenge Response pair and
602 TVPGTO756
Improved Reliability
(Tools / Xilinx ISE)

Efficient Implementation for 3-Parallel

603 TVMAFE442 Linear-Phase FIR Digital Odd Length Filters
(Front End Domains / DSP Core)

Efficient Implementation for 3-Parallel

604 TVMAFE443 Linear-Phase FIR Digital Odd Length Filters
(Front End Domains / Communications)

Efficient Implementation for 3-Parallel

605 TVMATO872 Linear-Phase FIR Digital Odd Length Filters
(Tools / Xilinx Vivado)

Efficient Implementation for 3-Parallel

606 TVMATO873 Linear-Phase FIR Digital Odd Length Filters
(Tools / Xilinx ISE)

Efficient Implementation for 3-Parallel

607 TVPGTO740 Linear-Phase FIR Digital Odd Length Filters
(Tools / Xilinx Vivado)

Efficient Implementation for 3-Parallel

608 TVPGTO741 Linear-Phase FIR Digital Odd Length Filters
(Tools / Xilinx ISE)

High-Density Memristor-CMOS Ternary Logic

609 TVMATO859 Family
(Tools / LT-Spice)

A Sub100mV Ultra Low Voltage Level

ShifterUsing Current Limiting Cross Coupled
610 TVMABE153 Technique for Wide-Range Conversion to IO
Voltage
(Back End Domains / Cadence EDA)

A Sub100mV Ultra Low Voltage Level

ShifterUsing Current Limiting Cross Coupled
611 TVMABE154 Technique for Wide-Range Conversion to IO
Voltage
(Back End Domains / Low Power VLSI)

A Sub100mV Ultra Low Voltage Level

612 TVPGBE140 ShifterUsing Current Limiting Cross Coupled
Technique for Wide-Range Conversion to IO

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Voltage
(Back End Domains / Low Power VLSI)

A Sub100mV Ultra Low Voltage Level

ShifterUsing Current Limiting Cross Coupled
613 TVPGBE141 Technique for Wide-Range Conversion to IO
Voltage
(Back End Domains / Transistor Logic)

A Sub100mV Ultra Low Voltage Level

ShifterUsing Current Limiting Cross Coupled
614 TVPGTO662 Technique for Wide-Range Conversion to IO
Voltage
(Tools / Tanner EDA)

A Sub100mV Ultra Low Voltage Level

ShifterUsing Current Limiting Cross Coupled
615 TVPGTO663 Technique for Wide-Range Conversion to IO
Voltage
(Tools / Cadence EDA)

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
616 TVPGTO30 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Tools / Tanner EDA)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
617 TVMABE51 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Back End Domains / Transistor Logic)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
618 TVMABE52 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Back End Domains / Cadence EDA)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

A Sub-Threshold Differential CMOS Schmitt
to increase the noise immunity with
Trigger with Adjustable Hysteresis Based on
619 TVPGBE61 tunable hysteresis by using
Body Bias Technique
sub-threshold differential CMOS
(Back End Domains / Cadence EDA)
Schmitt trigger. The circuit is

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

designed in a 0.18nm standard

CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
620 TVPGBE62 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Back End Domains / Transistor Logic)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
621 TVPGTO363 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Tools / Cadence EDA)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
622 TVMATO447 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Tools / Cadence EDA)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

The main objective of this paper is

to increase the noise immunity with
tunable hysteresis by using
A Sub-Threshold Differential CMOS Schmitt
sub-threshold differential CMOS
Trigger with Adjustable Hysteresis Based on
623 TVMATO448 Schmitt trigger. The circuit is
Body Bias Technique
designed in a 0.18nm standard
(Tools / Tanner EDA)
CMOS process with a 0.6 V power
supply which makes it a suitable
candidate for low-power applications

One-Sided Schmitt-Trigger-Based 9T SRAM

624 TVMABE145 Cell for NearThreshold Operation
(Back End Domains / Cadence EDA)

One-Sided Schmitt-Trigger-Based 9T SRAM

625 TVMABE146 Cell for NearThreshold Operation
(Back End Domains / Core Memories)

One-Sided Schmitt-Trigger-Based 9T SRAM

626 TVPGTO654 Cell for NearThreshold Operation
(Tools / Cadence EDA)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

One-Sided Schmitt-Trigger-Based 9T SRAM

627 TVPGTO655 Cell for NearThreshold Operation
(Tools / Tanner EDA)

One-Sided Schmitt-Trigger-Based 9T SRAM

628 TVMATO786 Cell for NearThreshold Operation
(Tools / Tanner EDA)

One-Sided Schmitt-Trigger-Based 9T SRAM

629 TVMATO787 Cell for NearThreshold Operation
(Tools / Cadence EDA)

VLSI Architecture for High Performance

630 TVMABE139 Wallace Tree Encoder
(Back End Domains / Cadence EDA)

VLSI Architecture for High Performance

631 TVMABE140 Wallace Tree Encoder
(Back End Domains / Low Power VLSI)

VLSI Architecture for High Performance

632 TVMATO780 Wallace Tree Encoder
(Tools / Tanner EDA)

VLSI Architecture for High Performance

633 TVMATO781 Wallace Tree Encoder
(Tools / Cadence EDA)

VLSI Architecture for High Performance

634 TVPGTO648 Wallace Tree Encoder
(Tools / Cadence EDA)

VLSI Architecture for High Performance

635 TVPGTO649 Wallace Tree Encoder
(Tools / Tanner EDA)

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
636 TVPGTO376 Dual-Stage 4:2 Compressors architectures for reducing area,
(Tools / Xilinx Vivado) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
Approximate Multiplier Design using Novel
This paper presents two novel
637 TVPGTO377 Dual-Stage 4:2 Compressors
approximate 4:2 compressor
(Tools / Xilinx ISE)
architectures for reducing area,
delay and power dissipation in
multipliers in which more than two

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

stages of cascaded compressors

are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
638 TVPGTO378 Dual-Stage 4:2 Compressors architectures for reducing area,
(Tools / Xilinx Vivado) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
639 TVPGTO379 Dual-Stage 4:2 Compressors architectures for reducing area,
(Tools / Xilinx ISE) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
640 TVMATO463 Dual-Stage 4:2 Compressors architectures for reducing area,
(Tools / Xilinx Vivado) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
641 TVMATO464 Dual-Stage 4:2 Compressors architectures for reducing area,
(Tools / Xilinx ISE) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

Approximate Multiplier Design using Novel
improve the speed and reduce the
642 TVMAFE115 Dual-Stage 4:2 Compressors
area for compressor architecture.
(Front End Domains / Arithmetic Core)
This paper presents two novel

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

approximate 4:2 compressor

architectures for reducing area,
delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

The main aim of this paper is to

improve the speed and reduce the
area for compressor architecture.
This paper presents two novel
Approximate Multiplier Design using Novel approximate 4:2 compressor
643 TVPGFE93 Dual-Stage 4:2 Compressors architectures for reducing area,
(Front End Domains / Arithmetic Core) delay and power dissipation in
multipliers in which more than two
stages of cascaded compressors
are required for partial product
accumulation

Reversible logic is increasingly

applied in circuits due to its ability to
reduce energy dissipation by
FPGA Implementation Of Dynamic Power, theoretically minimizing information
Area Optimized Reversible ALU For Various loss, which is a major source of
644 TVMAFE621
DSP Applications power consumption. This ALU aims
(Front End Domains / DSP Core) to leverage reversible gates to
dynamically reduce power usage,
making it suitable for
energy-sensitive DSP applications.

The main objective of this project is

to save energy and improve overall
Approximate Restoring Dividers Using Inexact
circuit performance, approximate
645 TVMAFE570 Cells and Estimation From Partial Remainders
computation can be employed in
(Front End Domains / Arithmetic Core)
applications that can withstand
errors.

In this brief, we propose a novel

PUF-BASED SECURE CHAOTIC RANDOM
physical unclonable function-based
NUMBER GENERATOR DESIGN
646 TVMAFE563 CPRNG (PUF-CPRNG), where the
METHODOLOGY
initial seed is secured by generating
(Front End Domains / Arithmetic Core)
it from PUF.

The paper presents an approach to

Optimization of WiFi Communication System
optimize the performance of WiFi
647 TVMABE222 using Low Power Ring Oscillator Delay Cell
communication systems by using a
(Back End Domains / Transistor Logic)
low power ring oscillator delay cell.

In this paper we are proposing

128-bit AES algorithm is highly
IMPLEMENTATION OF AES ALGORITHM ON
optimized in Key schedule and Sub
648 TVMAFE557 FPGA AND ON SOFTWARE
bytes blocks, for Area and Power.
(Front End Domains / Arithmetic Core)
The optimization has been done by
reusing the S-box block.

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S.No Project Code Project Name Objective

In this paper we are proposing

128-bit AES algorithm is highly
IMPLEMENTATION OF AES ALGORITHM ON
optimized in Key schedule and Sub
649 TVMAFE558 FPGA AND ON SOFTWARE
bytes blocks, for Area and Power.
(Front End Domains / Arithmetic Core)
The optimization has been done by
reusing the S-box block.

In this paper we are proposing

128-bit AES algorithm is highly
IMPLEMENTATION OF AES ALGORITHM ON
optimized in Key schedule and Sub
650 TVMAFE559 FPGA AND ON SOFTWARE
bytes blocks, for Area and Power.
(Front End Domains / Arithmetic Core)
The optimization has been done by
reusing the S-box block.

In this paper we are proposing

128-bit AES algorithm is highly
IMPLEMENTATION OF AES ALGORITHM ON
optimized in Key schedule and Sub
651 TVMAFE560 FPGA AND ON SOFTWARE
bytes blocks, for Area and Power.
(Front End Domains / DSP Core)
The optimization has been done by
reusing the S-box block.

In this paper, we present two

interleaved Double-Adjacent-Error
Design of Two Interleaved Error Detection and
Corrections (DAECs) for Error
652 TVMAFE552 Corrections using Hsiao Code and CRC
Detection and Correction (EDAC),
(Front End Domains / DSP Core)
using the Hsiao Code and Cyclic
Redundancy Code (CRC).

The proposed carry prediction

DESIGN OF APPROXIMATE VLSI
technique can reduce a prediction
ARCHITECTURE FOR ERROR TOLERANT
653 TVMAFE549 error rate compared to existing
IMAGE PROCESSING APPLICATIONS
approximate adders considered in
(Front End Domains / Arithmetic Core)
this paper.

The major objective of this paper is

to design and implement a two
stage complementary
Design and Implementation of Optimized metal-oxide-semiconductor
654 TVMI93 Parameter Based Operational Amplifier for operational amplifier through precise
High Speed Analog Signal Processing specifications and also investigate
the different outcomes concerning
several parameters as well as
process variations.

The primary objective appears to be

analyzing and comparing the
performance of SRAM cells
Performance Analysis of SRAM Cell Designed
designed using two different
655 TVMI117 using MOS and Floating-gate MOS for Ultralow
technologies: MOS
Power Technology
(Metal-Oxide-Semiconductor) and
Floating-gate MOS, with a focus on
ultralow power applications

RandShift: An Energy-Efficient Fault-Tolerant The main objective of this paper is

656 TVMAFE101 Method in Secure Nonvolatile Main Memory to reduce the error rate and power
(Front End Domains / Communications) in encrypted data encoded by the

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Advanced Encryption Standard.

This paper is implemented with the
randomness feature of AES
encryption as well as rotational shift
operation to tolerate hard faults in
nonvolatile memory cells

The paper investigates several

COMPARISON AND PERFORMANCE
important VCO parameters,
ANALYSIS OF RING OSCILLATORS AND
657 TVMI99 including power consumption,
CURRENT-STARVED VCO IN 45-NM CMOS
frequency tuning range, and output
TECHNOLOGY
amplitude.

The main objective of this project is

DESIGN AND IMPLEMENTATION OF to design a high-speed 4-bit R2R
658 TVMI97
HIGH-SPEED 4-BIT R2R DAC DAC using two stage operational
amplifier.

This research work will focuses on

analyzing the delay of a Wallace
tree multiplier and a carry select
Design & Implementation of Wallace Tree
659 TVMI95 Adder by optimizing their circuits to
Multiplier and Kogge Stone Adder
increase the speed of the different
digital circuits which are used in
computations.

In this project
REFLECTED-OUTPUT WILSON
A Power-Delay and Area Efficient Voltage CURRENT MIRROR based level
Level Shifter Based on a Reflected-Output shifter along with current limiters
660 TVMABE203
Wilson Current Mirror Level Shifter and pass transistors split inputs
(Back End Domains / Transistor Logic) inverter with is designed for
enhancing the speed and reducing
the power and area respectively.

In this project
REFLECTED-OUTPUT WILSON
A Power-Delay and Area Efficient Voltage CURRENT MIRROR based level
Level Shifter Based on a Reflected-Output shifter along with current limiters
661 TVMATO1138
Wilson Current Mirror Level Shifter and pass transistors split inputs
(Tools / Tanner EDA) inverter with is designed for
enhancing the speed and reducing
the power and area respectively.

In this project
REFLECTED-OUTPUT WILSON
A Power-Delay and Area Efficient Voltage CURRENT MIRROR based level
Level Shifter Based on a Reflected-Output shifter along with current limiters
662 TVPGTO919
Wilson Current Mirror Level Shifter and pass transistors split inputs
(Tools / Tanner EDA) inverter with is designed for
enhancing the speed and reducing
the power and area respectively.

Tosam: An Energy-efficient Truncation- and A scalable approximate multiplier,

663 TVPGTO474 Rounding-Based Scalable Approximate referred to as truncation- and
Multiplier rounding-based scalable

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

approximate multiplier (TOSAM) is

presented, that reduces the number
(Tools / Xilinx Vivado) of partial products by truncating
every of the input operands based
on their leading one-bit position

A scalable approximate multiplier,

referred to as truncation- and
Tosam: An Energy-efficient Truncation- and rounding-based scalable
Rounding-Based Scalable Approximate approximate multiplier (TOSAM) is
664 TVPGTO475
Multiplier presented, that reduces the number
(Tools / Xilinx ISE) of partial products by truncating
every of the input operands based
on their leading one-bit position

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
665 TVPGTO514
of FFT on Real Data several banks of smaller sizes to
(Tools / Xilinx Vivado) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
666 TVPGTO515
of FFT on Real Data several banks of smaller sizes to
(Tools / Xilinx ISE) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

The objective of this project is to

implement a novel FFT architecture
An Area Efficient 1024-Point Low Power called Radix-22 feed-forward
Radix-22 FFT Processor with Feed-Forward multiple path delay commutator to
667 TVPGTO141
Multiple Delay Commutators enhance the throughput of the
(Tools / Xilinx Vivado) previous topologies and reduce
energy consumption by utilizing
Radix-22 algorithm.

The objective of this project is to

implement a novel FFT architecture
An Area Efficient 1024-Point Low Power called Radix-22 feed-forward
Radix-22 FFT Processor with Feed-Forward multiple path delay commutator to
668 TVPGTO142
Multiple Delay Commutators enhance the throughput of the
(Tools / Xilinx ISE) previous topologies and reduce
energy consumption by utilizing
Radix-22 algorithm.

The objective of this project is to

An Area Efficient 1024-Point Low Power
implement a novel FFT architecture
Radix-22 FFT Processor with Feed-Forward
669 TVMATO98 called Radix-22 feed-forward
Multiple Delay Commutators
multiple path delay commutator to
(Tools / Xilinx Vivado)
enhance the throughput of the

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

previous topologies and reduce

energy consumption by utilizing
Radix-22 algorithm.

The objective of this project is to

implement a novel FFT architecture
An Area Efficient 1024-Point Low Power called Radix-22 feed-forward
Radix-22 FFT Processor with Feed-Forward multiple path delay commutator to
670 TVMATO99
Multiple Delay Commutators enhance the throughput of the
(Tools / Xilinx ISE) previous topologies and reduce
energy consumption by utilizing
Radix-22 algorithm.

A scalable approximate multiplier,

referred to as truncation- and
Tosam: An Energy-efficient Truncation- and rounding-based scalable
Rounding-Based Scalable Approximate approximate multiplier (TOSAM) is
671 TVMATO564
Multiplier presented, that reduces the number
(Tools / Xilinx Vivado) of partial products by truncating
every of the input operands based
on their leading one-bit position

A scalable approximate multiplier,

referred to as truncation- and
Tosam: An Energy-efficient Truncation- and rounding-based scalable
Rounding-Based Scalable Approximate approximate multiplier (TOSAM) is
672 TVMATO565
Multiplier presented, that reduces the number
(Tools / Xilinx ISE) of partial products by truncating
every of the input operands based
on their leading one-bit position

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
673 TVMATO617
of FFT on Real Data several banks of smaller sizes to
(Tools / Xilinx Vivado) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
674 TVMATO618
of FFT on Real Data several banks of smaller sizes to
(Tools / Xilinx ISE) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

This paper proposes a novel

An Area Efficient 1024-point Low Power radix-22 multiple delay commutators
Radix-22 Fft Processor with Feed-forward architecture utilizing the advantages
675 TVMAFE03
Multiple Delay Commutators of the radix-22 algorithm, such as
(Front End Domains / DSP Core) simple butterflies and less memory
requirement.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

This paper proposes a novel

An Area Efficient 1024-point Low Power radix-22 multiple delay commutators
Radix-22 Fft Processor with Feed-forward architecture utilizing the advantages
676 TVMAFE10
Multiple Delay Commutators of the radix-22 algorithm, such as
(Front End Domains / Cadence EDA) simple butterflies and less memory
requirement.

A scalable approximate multiplier,

referred to as truncation- and
rounding-based scalable
Tosam: An Energy-efficient Truncation- and
approximate multiplier (TOSAM) is
677 TVMAFE14 Rounding-Based Scalable Approximate
presented, that reduces the number
Multiplier
of partial products by truncating
every of the input operands based
on their leading one-bit position

A scalable approximate multiplier,

referred to as truncation- and
rounding-based scalable
Tosam: An Energy-efficient Truncation- and
approximate multiplier (TOSAM) is
678 TVREFE19_15 Rounding-Based Scalable Approximate
presented, that reduces the number
Multiplier
of partial products by truncating
every of the input operands based
on their leading one-bit position

The design of approximate

Design and Analysis of Approximate
redundant binary (RB) multipliers
679 TVMAFE26 Redundant Binary Multipliers
has been studied in this
(Front End Domains / Arithmetic Core)
paper.

The Finite Impulse Response Filter

was introduced
in this paper using two separate
Efficient FIR Filter Design using Booth
680 TVMI05 multipliers, namely Array Multiplier
Multiplier for VLSI Applications
and Booth Multiplier, and
the two proposed FIR filters were
compared with different parameters

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
681 TVMAFE38
of FFT on Real Data several banks of smaller sizes to
(Front End Domains / DSP Core) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
682 TVREFE19_43
of FFT on Real Data several banks of smaller sizes to
(Front End Domains / Cadence EDA) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

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S.No Project Code Project Name Objective

This paper proposes a novel

An Area Efficient 1024-point Low Power radix-22 multiple delay commutators
Radix-22 Fft Processor with Feed-forward architecture utilizing the advantages
683 TVREFE19_02
Multiple Delay Commutators of the radix-22 algorithm, such as
(Front End Domains / DSP Core) simple butterflies and less memory
requirement.

The main aim of this work is to

develop the area and delay efficient
Area Delay and Energy Efficient VLSI in place RFFT. This can be achieved
Architecture for Scalable In-Place Computation by partitioning the storage unit into
684 TVREFE19_42
of FFT on Real Data several banks of smaller sizes to
(Front End Domains / DSP Core) resolve the memory access conflicts
by concurrent data-swapping
between the banks.

The proposed method require less

complexity, less hardware, minimum
Optimal Design of Reversible Parity Preserving number of gates, minimum number
685 TVMI11
New Full Adder Full Subtractor of garbage inputs and minimum
number of constant inputs than
existing methods.

In this paper, Carry Select Adder

(CSA) architecture are proposed
using parallel prefix adder. Instead
Design of High Speed Carry Select Adder
686 TVMI13 of using 4-bit Ripple Carry Adder
using Brent Kung Adder
(RCA), parallel prefix adder i.e.,
4-bit Brent Kung (BK) adder is used
to design CSA.

In this paper, an approximate

687 TVMI14 Low-Power Approximate MAC Unit multiply-and-accumulate (MAC) unit
is introduced.

In this paper, we propose a new

design of energy efficient
688 TVMI15 A Low Power Reconfigurable LFSR
reconfigurable Linear Feedback
Shift Registers(LFSRs).

In this paper, we propose an

approximate integer format (AIF)
A Novel Data Format for Approximate and its associated arithmetic
689 TVMI16
Arithmetic Computing operations for energy minimization
with controllable computation
accuracy.

In this paper, we propose a novel

Energy-Efficient Approximate Multiplier Design energy-efficient approximate
690 TVMI17 using Bit Significance-Driven Logic multiplier design using a
Compression significance-driven logic
compression (SDLC) approach.

Scalable Construction of Approximate This is demonstrated by means of a

691 TVMI18 Multipliers with Formally Guaranteed Worst comparative evaluation of
Case Error approximate 16-bit multipliers

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

constructed by the proposed

method and other methods in the
literature.

The proposed magnitude

comparator using the technology of
692 TVMI20 Design of Low Power Magnitude Comparator
coupling has been compared with
the basic comparator circuit.

This paper presents a design which

provides full swing output for logic 1
Low Power 1-Bit Full Adder using Full-Swing
693 TVMI21 and logic 0 for 1-bit full adder cell
Gate Diffusion Input Technique
and reduces power consumption,
delay, and area.

In this brief, efficient solutions to

Efficient Implementations of 4-Bit Burst Error
694 TVMI25 protect memories against 4-bit
Correction for Memories
bursts are presented.

This paper presents a new area and

Area and Power Efficient VLSI Architecture of power efficient VLSI architecture for
695 TVMI26 Distributed Arithmetic Based LMS Adaptive least-mean-square (LMS) adaptive
Filter filterusing distributed arithmetic
(DA).

Here in this paper we proposed

Binary to Gray Code Converter Implementation
696 TVMI28 QCA implementation of binary to
using QCA
gray code converter.

The primary objective appears to be

designing and verifying a 4x4
Design and Verification of 4 X 4 Wallace Tree
697 TVMI116 Wallace tree multiplier circuit
Multiplier
optimized for high performance and
efficiency

Researchers are exploring various

techniques to optimize power
consumption in digital systems,
698 TVMI115 Carry look ahead adder using adiabatic logic including the combination of
advanced logic styles with
specialized arithmetic circuits like
carry look-ahead adders.

Image Enhancement using Edge Spartan 6

699 TVMATO1161 FPGA Board
(Tools / FPGA)

This paper introduces the structure

and working principle of SPI
communication bus, analyzes its
DESIGN OF SPI AND I2C PROTOCOL IN timing structure and four working
700 TVMAFE566 VERILOG HDL modes, and uses this state machine
(Front End Domains / Communications) method to realize its SPI bus
communication function & also this
paper focuses on the design of I2C
single master which consists of a

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

bidirectional data line i.e. serial data

line (sda) and serial clock line (scl).

A LOW-POWER HIGH-SPEED DYNAMIC

This work introduces an innovative
COMPARATOR WITH A
low-power, high-speed dynamic
701 TVMABE219 TRANSCONDUCTANCE-ENHANCED
comparator with a new latching
LATCHING STAGE
step.
(Back End Domains / Transistor Logic)

Image and Video Processing Using Xilinx

702 TMMAIN23 System Generator
(Front End Domains / Matlab Interfacing)

Minimizes power consumption

Design of test pattern generator (TPG) by an
during testing
optimized low power design for testability
Reduces test time
703 TVMABE269 (DFT) for scan BIST circuits using transmission
Improves fault coverage
gates
Uses transmission gates for efficient
(Back End Domains / Cadence EDA)
switching

Minimizes power consumption

Design of test pattern generator (TPG) by an
during testing
optimized low power design for testability
Reduces test time
704 TVMABE270 (DFT) for scan BIST circuits using transmission
Improves fault coverage
gates
Uses transmission gates for efficient
(Back End Domains / Core Memories)
switching

Minimizes power consumption

Design of test pattern generator (TPG) by an
during testing
optimized low power design for testability
Reduces test time
705 TVMABE271 (DFT) for scan BIST circuits using transmission
Improves fault coverage
gates
Uses transmission gates for efficient
(Back End Domains / Low Power VLSI)
switching

Minimizes power consumption

Design of test pattern generator (TPG) by an
during testing
optimized low power design for testability
Reduces test time
706 TVMABE272 (DFT) for scan BIST circuits using transmission
Improves fault coverage
gates
Uses transmission gates for efficient
(Back End Domains / Transistor Logic)
switching

The primary goal is to achieve

high-speed multiplication by
reducing the critical path delay. The
Wallace tree architecture inherently
supports parallel processing of
partial products, which significantly
Design and Analysis of Wallace Tree Multiplier
707 TVMI113 reduces the time taken for
for CMOS and CPL Logic
multiplication compared to serial
methods. Implementing this
architecture in CMOS and CPL aims
to further enhance speed by
leveraging the fast switching
capabilities of these technologies.

708 TVMABE239 Design of DRAM Sense Amplifier using 45nm In this proposed technique, we are

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

utilising the DRAM

sense amplifier along with the
Technology
FSPA-VLSA (Foot Switch
(Back End Domains / Transistor Logic)
PMOS Access Voltage Latch Type
Sense Amplifier).

In this brief, we propose a power

efficient design of synchronous
Power efficient synchronous counter design counters that reduces the power
709 TVMABE233
(Back End Domains / Low Power VLSI) consumption due to clock
distribution for different flip-flops and
offers high reliability

A high-performance capacitance
multiplier able to operate
±0.25-V Class-AB CMOS Capacitance with supplies as low as ±0.25 V is
710 TVPGBE151 multiplier and precision rectifiers presented. It is based on
(Back End Domains / Transistor Logic) adaptively biased class-AB current
mirrors which provide high
current efficiency.

The main aim of this project is to

DESIGN AND ANALYSIS OF ENHANCED
reduce partial products and
711 TVMI94 DADDA MULTIPLIER USING 5:2
minimize logic gates using
COMPRESSORS
enhanced dadda multiplier.

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
712 TVMABE141
Pull-Up Network
(Back End Domains / Cadence EDA)

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
713 TVMABE142
Pull-Up Network
(Back End Domains / Low Power VLSI)

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
714 TVMATO782
Pull-Up Network
(Tools / Tanner EDA)

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
715 TVMATO783
Pull-Up Network
(Tools / Cadence EDA)

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
716 TVPGTO650
Pull-Up Network
(Tools / Cadence EDA)

A Low-Power and High-Speed Voltage Level

Shifter Based on a Regulated Cross-Coupled
717 TVPGTO651
Pull-Up Network
(Tools / Tanner EDA)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Design of ALU using Dual Mode Logic with

718 TVMATO28 Optimized Power and Speed
(Tools / Cadence EDA)

Design of ALU using Dual Mode Logic with

719 TVMATO29 Optimized Power and Speed
(Tools / Tanner EDA)

Exploration of Approximate Multipliers Design

Space using Carry Propagation Free
720 TVMAFE323
Compressors
(Front End Domains / Arithmetic Core)

The main aim of this project is to

Design a novel architecture of flash ADC using implement the architecture of flash
721 TVMI104
Memristor based encoder ADC for lower power consumption
and optimization of area.

VLSI Implementation of Image Fusion using

722 TVPGOT01 PCA Algorithm with Maximum Selector Rule
(Others / Matlab Interfacing)

VLSI Implementation of Image Fusion using

723 TVMAOT01 PCA Algorithm with Maximum Selector Rule
(Others / Matlab Interfacing)

A Novel Five Input Multiple Function QCA

724 TVPGFE240 Threshold Gate
(Front End Domains / Nano Technology)

A Novel Five Input Multiple Function QCA

725 TVMAFE293 Threshold Gate
(Front End Domains / Nano Technology)

VLSI Implementation of Image Fusion using

726 TVMAFE345 PCA Algorithm with Maximum Selector Rule
(Front End Domains / Matlab Interfacing)

VLSI Implementation of decoding algorithms The main objective in this paper is

727 TVMAFE599 using EG-LDPC Codes to creating of three different decoder
(Front End Domains / Testing) algorithms for LDPC Codes.

In this paper, design of Vedic

multiplier is presented using carry
Design and Implementation of vedic Multiplier
728 TVMI100 increment adder (CIA) logic for
an Improved Carry Increment Adder
addition of partial product terms in
partial product lines.

The main aim of this project is to

implement the floating point
A Binary High Speed Floating Point Multiplier multiplier with reduced delay. The
729 TVMAFE354
(Front End Domains / Arithmetic Core) high performance can be achieved
in this work by using Carry save
multiplier

A Binary High Speed Floating Point Multiplier The main aim of this project is to
730 TVPGFE289
(Front End Domains / Arithmetic Core) implement the floating point

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

multiplier with reduced delay. The

high performance can be achieved
in this work by using Carry save
multiplier

The main aim of this project is to

implement the floating point
A Binary High Speed Floating Point Multiplier multiplier with reduced delay. The
731 TVMATO663
(Tools / Xilinx Vivado) high performance can be achieved
in this work by using Carry save
multiplier

The main aim of this project is to

implement the floating point
A Binary High Speed Floating Point Multiplier multiplier with reduced delay. The
732 TVMATO664
(Tools / Xilinx ISE) high performance can be achieved
in this work by using Carry save
multiplier

Design of ALU using Dual Mode Logic with

733 TVPGTO20 Optimized Power and Speed
(Tools / Tanner EDA)

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
734 TVPGTO139 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Tools / Xilinx Vivado)
Manager blocks which is available in
the FPGA.

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
735 TVPGTO140 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Tools / Xilinx ISE)
Manager blocks which is available in
the FPGA.

A Serial Commutator Fast Fourier Transform

736 TVPGTO143 Architecture for Real-Valued Signals
(Tools / Xilinx Vivado)

A Serial Commutator Fast Fourier Transform

737 TVPGTO144 Architecture for Real-Valued Signals
(Tools / Xilinx ISE)

RoBA Multiplier:A Rounding-Based

Approximate Multiplier for High-Speed yet
738 TVPGTO166
Energy-Efficient Digital Signal Processing
(Tools / Xilinx Vivado)

RoBA Multiplier:A Rounding-Based

Approximate Multiplier for High-Speed yet
739 TVPGTO167
Energy-Efficient Digital Signal Processing
(Tools / Xilinx ISE)

740 TVPGTO172 Low Power Scan based Built in Self Test based The main aim of this project is to

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

implement the low power BIST by

on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
Generation & Reseeding pattern generation phase and LP
(Tools / Xilinx Vivado) deterministic BIST with reseeding
phase.

The main aim of this project is to

Low Power Scan based Built in Self Test based implement the low power BIST by
on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
741 TVPGTO173
Generation & Reseeding pattern generation phase and LP
(Tools / Xilinx ISE) deterministic BIST with reseeding
phase.

LFSR-based Generation of Multicycle Tests

742 TVPGTO176
(Tools / Xilinx Vivado)

LFSR-based Generation of Multicycle Tests

743 TVPGTO177
(Tools / Xilinx ISE)

Design of High Speed ALU using Vedic

744 TVPGTO199 Mathematics Based Multiplication Unit
(Tools / Xilinx Vivado)

Design of High Speed ALU using Vedic

745 TVPGTO200 Mathematics Based Multiplication Unit
(Tools / Xilinx ISE)

ALU with Reversible Decoder Logic and Parity

746 TVPGTO224 Preserve Logic Based Full Adder Subtractor
(Tools / Xilinx Vivado)

ALU with Reversible Decoder Logic and Parity

747 TVPGTO225 Preserve Logic Based Full Adder Subtractor
(Tools / Xilinx ISE)

ALU with Reversible Decoder Logic and Parity

748 TVPGTO226 Preserve Logic Based Full Adder Subtractor
(Tools / Xilinx Vivado)

ALU with Reversible Decoder Logic and Parity

749 TVPGTO227 Preserve Logic Based Full Adder Subtractor
(Tools / Xilinx ISE)

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
750 TVMATO96 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Tools / Xilinx Vivado)
Manager blocks which is available in
the FPGA.

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
751 TVMATO97 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Tools / Xilinx ISE)
Manager blocks which is available in
the FPGA.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

A Serial Commutator Fast Fourier Transform

752 TVMATO100 Architecture for Real-Valued Signals
(Tools / Xilinx Vivado)

A Serial Commutator Fast Fourier Transform

753 TVMATO101 Architecture for Real-Valued Signals
(Tools / Xilinx ISE)

RoBA Multiplier:A Rounding-Based

Approximate Multiplier for High-Speed yet
754 TVMATO138
Energy-Efficient Digital Signal Processing
(Tools / Xilinx Vivado)

RoBA Multiplier:A Rounding-Based

Approximate Multiplier for High-Speed yet
755 TVMATO139
Energy-Efficient Digital Signal Processing
(Tools / Xilinx ISE)

The main aim of this project is to

Low Power Scan based Built in Self Test based implement the low power BIST by
on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
756 TVMATO146
Generation & Reseeding pattern generation phase and LP
(Tools / Xilinx Vivado) deterministic BIST with reseeding
phase.

The main aim of this project is to

Low Power Scan based Built in Self Test based implement the low power BIST by
on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
757 TVMATO147
Generation & Reseeding pattern generation phase and LP
(Tools / Xilinx ISE) deterministic BIST with reseeding
phase.

LFSR-based Generation of Multicycle Tests

758 TVMATO150
(Tools / Xilinx Vivado)

LFSR-based Generation of Multicycle Tests

759 TVMATO151
(Tools / Xilinx ISE)

Design of High Speed ALU using Vedic

760 TVMATO178 Mathematics Based Multiplication Unit
(Tools / Xilinx Vivado)

Design of High Speed ALU using Vedic

761 TVMATO179 Mathematics Based Multiplication Unit
(Tools / Xilinx ISE)

ALU with Reversible Decoder Logic and Parity

762 TVPGFE198 Preserve Logic Based Full Adder Subtractor
(Front End Domains / Design for Testability)

ALU with Reversible Decoder Logic and Parity

763 TVMAFE247 Preserve Logic Based Full Adder Subtractor
(Front End Domains / Testing)

RoBA Multiplier:A Rounding-Based

764 TVPGFE205 Approximate Multiplier for High-Speed yet
Energy-Efficient Digital Signal Processing

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(Front End Domains / Arithmetic Core)

RoBA Multiplier:A Rounding-Based

Approximate Multiplier for High-Speed yet
765 TVMAFE255
Energy-Efficient Digital Signal Processing
(Front End Domains / Arithmetic Core)

Design of High Speed ALU using Vedic

766 TVPGFE216 Mathematics Based Multiplication Unit
(Front End Domains / Arithmetic Core)

Design of High Speed ALU using Vedic

767 TVMAFE270 Mathematics Based Multiplication Unit
(Front End Domains / Arithmetic Core)

LFSR-based Generation of Multicycle Tests

768 TVPGFE229
(Front End Domains / Design for Testability)

LFSR-based Generation of Multicycle Tests

769 TVMAFE284
(Front End Domains / Testing)

The main aim of this project is to

Low Power Scan based Built in Self Test based implement the low power BIST by
on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
770 TVPGFE231
Generation & Reseeding pattern generation phase and LP
(Front End Domains / Design for Testability) deterministic BIST with reseeding
phase.

The main aim of this project is to

Low Power Scan based Built in Self Test based implement the low power BIST by
on Weighted Pseudo Random Test Pattern using LP weighted pseudo random
771 TVMAFE286
Generation & Reseeding pattern generation phase and LP
(Front End Domains / Testing) deterministic BIST with reseeding
phase.

A Serial Commutator Fast Fourier Transform

772 TVPGFE242 Architecture for Real-Valued Signals
(Front End Domains / DSP Core)

A Serial Commutator Fast Fourier Transform

773 TVMAFE295 Architecture for Real-Valued Signals
(Front End Domains / DSP Core)

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
774 TVPGFE243 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Front End Domains / Design for Testability)
Manager blocks which is available in
the FPGA.

In this project, a novel

implementation of True Random
An Improved DCM-based Tunable True
Number Generator was designed
775 TVMAFE297 Random Number Generator for Xilinx FPGA
with the help of the Digital Clock
(Front End Domains / Testing)
Manager blocks which is available in
the FPGA.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Novel Designs of a Carry Borrow Look-ahead

776 TVPGFE255 Adder Subtractor using Reversible Gates
(Front End Domains / Arithmetic Core)

Novel Designs of a Carry Borrow Look-ahead

777 TVMAFE307 Adder Subtractor using Reversible Gates
(Front End Domains / Arithmetic Core)

Design of ALU using Dual Mode Logic with

778 TVPGBE100 Optimized Power and Speed
(Back End Domains / Low Power VLSI)

Design of ALU using Dual Mode Logic with

779 TVMABE99 Optimized Power and Speed
(Back End Domains / Low Power VLSI)

Low Power Approximate MAC unit

780 TVPGFE276
(Front End Domains / DSP Core)

In this project, here proposed a

Design and Implementation of High Speed
novel technique to multiply two
781 TVMATO1146 Radix-2 CSD Based Floating Point Multiplier
unsigned binary numbers through a
(Tools / Xilinx Vivado)
radix-2 CSD based approach.

A Low Power, Low Noise Amplifier for

782 TVPGTO21 Recording Neural Signals
(Tools / Tanner EDA)

Novel Designs of a Carry Borrow Look-ahead

783 TVPGTO94 Adder Subtractor using Reversible Gates
(Tools / Xilinx Vivado)

Novel Designs of a Carry Borrow Look-ahead

784 TVPGTO95 Adder Subtractor using Reversible Gates
(Tools / Xilinx ISE)

Design of Reliable SoCs with BIST Hardware

785 TVPGTO121 and Machine Learning
(Tools / Xilinx Vivado)

Design of Reliable SoCs with BIST Hardware

786 TVPGTO122 and Machine Learning
(Tools / Xilinx ISE)

Design of Reconfigurable LFSR for VLSI IC

787 TVPGTO123 Testing in ASIC and FPGA
(Tools / Xilinx Vivado)

Design of Reconfigurable LFSR for VLSI IC

788 TVPGTO124 Testing in ASIC and FPGA
(Tools / Xilinx ISE)

Area-Efficient Architecture for Dual-Mode

789 TVPGTO219 Double Precision Floating Point Division
(Tools / Xilinx Vivado)

790 TVPGTO220 Area-Efficient Architecture for Dual-Mode

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Double Precision Floating Point Division

(Tools / Xilinx ISE)

A Low-Power Low-Cost Design of Primary

791 TVPGTO232 Synchronization Signal Detection
(Tools / Xilinx Vivado)

A Low-Power Low-Cost Design of Primary

792 TVPGTO233 Synchronization Signal Detection
(Tools / Xilinx ISE)

A Low Power, Low Noise Amplifier for

793 TVPGTO234 Recording Neural Signals
(Tools / Cadence EDA)

A Low-Power Low-Cost Design of Primary

794 TVMATO213 Synchronization Signal Detection
(Tools / Xilinx Vivado)

A Low-Power Low-Cost Design of Primary

795 TVMATO214 Synchronization Signal Detection
(Tools / Xilinx ISE)

A Low Power, Low Noise Amplifier for

796 TVMATO215 Recording Neural Signals
(Tools / Cadence EDA)

A Low Power, Low Noise Amplifier for

797 TVMATO216 Recording Neural Signals
(Tools / Tanner EDA)

Design and Implementation of PAL and PLA

798 TVMATO12 using Reversible gates
(Tools / Xilinx Vivado)

Design and Implementation of PAL and PLA

799 TVMATO13 using Reversible gates
(Tools / Xilinx ISE)

Novel Designs of a Carry Borrow Look-ahead

800 TVMATO42 Adder Subtractor using Reversible Gates
(Tools / Xilinx Vivado)

Novel Designs of a Carry Borrow Look-ahead

801 TVMATO43 Adder Subtractor using Reversible Gates
(Tools / Xilinx ISE)

Design of Reliable SoCs with BIST Hardware

802 TVMATO74 and Machine Learning
(Tools / Xilinx Vivado)

Design of Reliable SoCs with BIST Hardware

803 TVMATO75 and Machine Learning
(Tools / Xilinx ISE)

Design of Reconfigurable LFSR for VLSI IC

804 TVMATO76
Testing in ASIC and FPGA

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

(Tools / Xilinx Vivado)

Design of Reconfigurable LFSR for VLSI IC

805 TVMATO77 Testing in ASIC and FPGA
(Tools / Xilinx ISE)

Design and Implementation of BCD Adders

806 TVMATO83 with QCA Majority Logic Gates
(Tools / QCA)

Approximate Belief Propagation Decoder for

807 TVMATO94 Polar Codes
(Tools / Xilinx Vivado)

Approximate Belief Propagation Decoder for

808 TVMATO95 Polar Codes
(Tools / Xilinx ISE)

Area-Efficient Architecture for Dual-Mode

809 TVMATO201 Double Precision Floating Point Division
(Tools / Xilinx Vivado)

Area-Efficient Architecture for Dual-Mode

810 TVMATO202 Double Precision Floating Point Division
(Tools / Xilinx ISE)

A Low Power, Low Noise Amplifier for

811 TVPGBE89 Recording Neural Signals
(Back End Domains / Low Power VLSI)

A Low Power, Low Noise Amplifier for

812 TVMABE89 Recording Neural Signals
(Back End Domains / Low Power VLSI)

A Low-Power Low-Cost Design of Primary

Synchronization Signal Detection
813 TVPGFE195
(Front End Domains / Communications and
Crypto Core)

A Low-Power Low-Cost Design of Primary

814 TVMAFE244 Synchronization Signal Detection
(Front End Domains / Communications)

Area-Efficient Architecture for Dual-Mode

815 TVPGFE200 Double Precision Floating Point Division
(Front End Domains / Arithmetic Core)

Area-Efficient Architecture for Dual-Mode

816 TVMAFE250 Double Precision Floating Point Division
(Front End Domains / Arithmetic Core)

Approximate Belief Propagation Decoder for

Polar Codes
817 TVPGFE245
(Front End Domains / Communications and
Crypto Core)

818 TVMAFE298 Approximate Belief Propagation Decoder for

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Polar Codes
(Front End Domains / Communications)

Design and Implementation of BCD Adders

819 TVPGFE253 with QCA Majority Logic Gates
(Front End Domains / Nano Technology)

Design and Implementation of BCD Adders

820 TVMAFE305 with QCA Majority Logic Gates
(Front End Domains / Nano Technology)

Design of Reconfigurable LFSR for VLSI IC

821 TVPGFE265 Testing in ASIC and FPGA
(Front End Domains / Design for Testability)

Design of Reconfigurable LFSR for VLSI IC

822 TVMAFE319 Testing in ASIC and FPGA
(Front End Domains / Testing)

Design of Reliable SoCs with BIST Hardware

823 TVPGFE266 and Machine Learning
(Front End Domains / Design for Testability)

Design of Reliable SoCs with BIST Hardware

824 TVMAFE320 and Machine Learning
(Front End Domains / Testing)

Design and Implementation of PAL and PLA

825 TVMAFE339 using Reversible gates
(Front End Domains / FPGA)

Design and Implementation of PAL and PLA

826 TVMAFE340 using Reversible gates
(Front End Domains / Arithmetic Core)

Design and Implementation of PAL and PLA

827 TVMAFE341 using Reversible gates
(Front End Domains / Arithmetic Core)

The main objective of this project is

Design of Flipflops and LFSR using Reversible
to reduce the power for LFSR and
828 TVMAFE385 Logic Gate
flipflop design by using reversible
(Front End Domains / Arithmetic Core)
logic

Switching Mode based 4:2 Compressors for

829 TVPGTO160 Dynamic Accurate Reconfigurable Multipliers
(Tools / Xilinx Vivado)

Switching Mode based 4:2 Compressors for

830 TVPGTO161 Dynamic Accurate Reconfigurable Multipliers
(Tools / Xilinx ISE)

Switching Mode based 4:2 Compressors for

831 TVMATO132 Dynamic Accurate Reconfigurable Multipliers
(Tools / Xilinx Vivado)

832 TVMATO133 Switching Mode based 4:2 Compressors for

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Dynamic Accurate Reconfigurable Multipliers

(Tools / Xilinx ISE)

Switching Mode based 4:2 Compressors for

833 TVPGFE202 Dynamic Accurate Reconfigurable Multipliers
(Front End Domains / Arithmetic Core)

Switching Mode based 4:2 Compressors for

834 TVMAFE252 Dynamic Accurate Reconfigurable Multipliers
(Front End Domains / Arithmetic Core)

The objective of "A Novel Low

Power, Low Area Array Multiplier
Design for DSP Applications" is
likely focused on developing a new,
innovative array multiplier that
consumes less power and occupies
a smaller physical space,
specifically tailored for use in Digital
A Novel Low Power, Low Area Array Multiplier
835 TVMI112 Signal Processing (DSP)
Design for DSP Applications
applications. This design aims to
enhance the efficiency and
performance of DSP systems by
providing a more energy-efficient
and compact solution for
multiplication operations, which are
fundamental in digital signal
processing algorithms.

CMOS-Memristor Inverter Circuit Design and This paper investigates the benefits
836 TVMABE234 Analysis Using Cadence Virtuoso of combining CMOS logic along with
(Back End Domains / Core Memories) memristors

This paper presents a novel

mixed-signal low-power dual-band
Dual-Band Waveform Generator With square/triangular waveform
837 TVPGBE153 Ultra-Wide Low-Frequency Tuning-Range generator (WFG) chip with a wide
(Back End Domains / Transistor Logic) low-frequency tuning range for
medical bio-electric stimulation
therapy.

In this
work, we address the issue of
leakage power that arises with the
device channel length scaling to
A Circuit Technique for Leakage Power
838 TVMI105 sub-100nm. We present a circuit
reduction in CMOS VLSI Circuits
technique to mitigate the leakage
currents of MOSFET through
controlling the voltage at the source
terminal of the MOSFET.

The main objective of this project is

Analysis of 6T SRAM on Different CMOS also to justify the advantageous of
839 TVMI98
Technologies lower technology nodes by
designing 6T SRAM.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

This paper proposes the design of a

low power and high-speed 4-bit
Design of Low Power and High Speed 4-Bit
840 TVMI96 ripple carry adder (RCA) using the
Ripple Carry Adder Using GDI Multiplexer
Gate Diffusion Input (GDI)
multiplexer.

Integration of Optimized GDI Logic based NOR This paper focuses on circuit level
841 TVMI92 Gate and Half Adder into PASTA for Low optimization to reduce the area and
Power & Low Area Applications power consumption.

The main aim of this work is to

implement the MAC unit which is
Design of MAC Unit in Artificial Neural Network used in Neural Network
842 TVMAFE356 Architecture using Verilog HDL applications. The MAC architecture
(Front End Domains / Arithmetic Core) was designed by using vedic
multiplier with reduced delay
architecture

The main aim of this work is to

implement the MAC unit which is
Design of MAC Unit in Artificial Neural Network used in Neural Network
843 TVMATO666 Architecture using Verilog HDL applications. The MAC architecture
(Tools / Xilinx Vivado) was designed by using vedic
multiplier with reduced delay
architecture

The main aim of this work is to

implement the MAC unit which is
Design of MAC Unit in Artificial Neural Network used in Neural Network
844 TVMATO667 Architecture using Verilog HDL applications. The MAC architecture
(Tools / Xilinx ISE) was designed by using vedic
multiplier with reduced delay
architecture

The main of this work is to

implement the adders with minimal
Reversible Adder Design for Ripple Carry and power reduction. In this project, the
845 TVMAFE350 Carry Look Ahead (4, 8, 16, 32-Bit) ripple carry adder and carry look
(Front End Domains / Arithmetic Core) adder are designed with Reversible
logic gates like Fredkin and Peres
gate

The main of this work is to

implement the adders with minimal
Reversible Adder Design for Ripple Carry and power reduction. In this project, the
846 TVMATO656 Carry Look Ahead (4, 8, 16, 32-Bit) ripple carry adder and carry look
(Tools / Xilinx Vivado) adder are designed with Reversible
logic gates like Fredkin and Peres
gate

The main of this work is to

implement the adders with minimal
Reversible Adder Design for Ripple Carry and
power reduction. In this project, the
847 TVMATO657 Carry Look Ahead (4, 8, 16, 32-Bit)
ripple carry adder and carry look
(Tools / Xilinx ISE)
adder are designed with Reversible
logic gates like Fredkin and Peres

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

gate

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
848 TVMAFE349 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Front End Domains / Arithmetic Core)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
849 TVPGFE287 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Front End Domains / Arithmetic Core)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
850 TVMATO654 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Tools / Xilinx Vivado)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
851 TVMATO655 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Tools / Xilinx ISE)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
852 TVPGTO547 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Tools / Xilinx Vivado)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

The main aim of this project is to

implement a high speed low-power
multiplier adopting the new SPST
implementing approach. This
Design of High Performance and Low Power
multiplier is designed by using the
853 TVPGTO548 Multiplier using Modified Booth Encoder
Spurious Power Suppression
(Tools / Xilinx ISE)
Technique (SPST) on a modified
Booth encoder which is controlled
by a detection unit using an AND
gate.

A Single-Ended with Dynamic Feedback

854 TVPGTO71 Control 8T Subthreshold SRAM Cell
(Tools / Cadence EDA)

A Single-Ended with Dynamic Feedback

855 TVPGTO72 Control 8T Subthreshold SRAM Cell
(Tools / Tanner EDA)

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
856 TVPGTO129
Network-On-Chip
(Tools / Xilinx Vivado)

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
857 TVPGTO130
Network-On-Chip
(Tools / Xilinx ISE)

Efficient Designs of Multiported Memory on

858 TVPGTO187 FPGA
(Tools / Xilinx Vivado)

Efficient Designs of Multiported Memory on

859 TVPGTO188 FPGA
(Tools / Xilinx ISE)

DLAU a Scalable Deep Learning Accelerator

860 TVPGTO193 Unit on FPGA
(Tools / Xilinx Vivado)

DLAU a Scalable Deep Learning Accelerator

861 TVPGTO194 Unit on FPGA
(Tools / Xilinx ISE)

Design and Analysis of Approximate

862 TVPGTO209 Compressors for Multiplication
(Tools / Xilinx Vivado)

Design and Analysis of Approximate

863 TVPGTO210 Compressors for Multiplication
(Tools / Xilinx ISE)

Low-Power Split-Radix FFT Processors using

864 TVPGTO320 Radix-2 Butterfly Units
(Tools / Cadence EDA)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Low-Power Split-Radix FFT Processors using

865 TVPGTO321 Radix-2 Butterfly Units
(Tools / Tanner EDA)

Low-Power Split-Radix FFT Processors using

866 TVMATO364 Radix-2 Butterfly Units
(Tools / Cadence EDA)

Low-Power Split-Radix FFT Processors using

867 TVMATO365 Radix-2 Butterfly Units
(Tools / Tanner EDA)

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
868 TVMATO84
Network-On-Chip
(Tools / Xilinx Vivado)

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
869 TVMATO85
Network-On-Chip
(Tools / Xilinx ISE)

Design of a High Speed Adder

870 TVMATO126
(Tools / Xilinx Vivado)

Design of a High Speed Adder

871 TVMATO127
(Tools / Xilinx ISE)

Efficient Designs of Multiported Memory on

872 TVMATO162 FPGA
(Tools / Xilinx Vivado)

Efficient Designs of Multiported Memory on

873 TVMATO163 FPGA
(Tools / Xilinx ISE)

DLAU a Scalable Deep Learning Accelerator

874 TVMATO168 Unit on FPGA
(Tools / Xilinx Vivado)

DLAU a Scalable Deep Learning Accelerator

875 TVMATO169 Unit on FPGA
(Tools / Xilinx ISE)

Design and Analysis of Approximate

876 TVMATO188 Compressors for Multiplication
(Tools / Xilinx Vivado)

Design and Analysis of Approximate

877 TVMATO189 Compressors for Multiplication
(Tools / Xilinx ISE)

A Single-Ended with Dynamic Feedback

878 TVMATO209 Control 8T Subthreshold SRAM Cell
(Tools / Cadence EDA)

879 TVMATO210 A Single-Ended with Dynamic Feedback

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Control 8T Subthreshold SRAM Cell

(Tools / Tanner EDA)

A Single-Ended with Dynamic Feedback

880 TVPGBE91 Control 8T Subthreshold SRAM Cell
(Back End Domains / Cadence EDA)

881 TVMIFE91 Logic Synthesis in Reversible PLA

Low-Power Split-Radix FFT Processors using

882 TVPGFE185 Radix-2 Butterfly Units
(Front End Domains / DSP Core)

Low-Power Split-Radix FFT Processors using

883 TVMAFE229 Radix-2 Butterfly Units
(Front End Domains / DSP Core)

A Single-Ended with Dynamic Feedback

884 TVPGBE90 Control 8T Subthreshold SRAM Cell
(Back End Domains / Core Memories)

A Single-Ended with Dynamic Feedback

885 TVMABE90 Control 8T Subthreshold SRAM Cell
(Back End Domains / Core Memories)

Design and Analysis of Approximate

886 TVPGFE211 Compressors for Multiplication
(Front End Domains / Arithmetic Core)

Design and Analysis of Approximate

887 TVMAFE262 Compressors for Multiplication
(Front End Domains / Arithmetic Core)

DLAU a Scalable Deep Learning Accelerator

888 TVPGFE220 Unit on FPGA
(Front End Domains / FPGA)

DLAU a Scalable Deep Learning Accelerator

889 TVPGFE221 Unit on FPGA
(Front End Domains / Arithmetic Core)

DLAU a Scalable Deep Learning Accelerator

890 TVMAFE276 Unit on FPGA
(Front End Domains / Arithmetic Core)

Efficient Designs of Multiported Memory on

891 TVPGFE223 FPGA
(Front End Domains / DSP Core)

Efficient Designs of Multiported Memory on

892 TVPGFE224 FPGA
(Front End Domains / FPGA)

Efficient Designs of Multiported Memory on

893 TVMAFE279 FPGA
(Front End Domains / DSP Core)

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S.No Project Code Project Name Objective

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
894 TVPGFE262 Network-On-Chip
(Front End Domains / Communications and
Crypto Core)

Design and Implementation of a Hybrid

Switching Router for the Reconfigurable
895 TVMAFE315
Network-On-Chip
(Front End Domains / Communications)

This paper proposes a novel

VLSI Design of High Speed Vedic Multiplier for architecture for implementation of
896 TVPGFE191 FPGA Implementation signed
(Front End Domains / Arithmetic Core) multiplication using the vedic
algorithm.

In this paper a high performance

64x64 bit redundant binary (RB)
multiplier have been designed by
using recently proposed redundant
VLSI Design of 64bit × 64bit High Performance
binary encoding approach to
897 TVMAFE238 Multiplier with Redundant Binary Encoding
eliminate the error correcting word
(Front End Domains / Arithmetic Core)
and a delay efficient parallel prefix
Ling adder for final redundant binary
to normal binary (RB-NB)
conversion.

This paper proposes a novel

VLSI Design of High Speed Vedic Multiplier for architecture for implementation of
898 TVPGTO308 FPGA Implementation signed
(Tools / Xilinx Vivado) multiplication using the vedic
algorithm.

This paper proposes a novel

VLSI Design of High Speed Vedic Multiplier for architecture for implementation of
899 TVPGTO309 FPGA Implementation signed
(Tools / Xilinx ISE) multiplication using the vedic
algorithm.

This paper proposes a novel

VLSI Design of High Speed Vedic Multiplier for architecture for implementation of
900 TVMATO348 FPGA Implementation signed
(Tools / Xilinx Vivado) multiplication using the vedic
algorithm.

This paper proposes a novel

VLSI Design of High Speed Vedic Multiplier for architecture for implementation of
901 TVMATO349 FPGA Implementation signed
(Tools / Xilinx ISE) multiplication using the vedic
algorithm.

Reliable Low-Latency Viterbi Algorithm

902 TVPGTO90 Architecture Bench marked on ASIC & FPGA
(Tools / Xilinx Vivado)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Reliable Low-Latency Viterbi Algorithm

903 TVPGTO91 Architecture Bench marked on ASIC & FPGA
(Tools / Xilinx ISE)

Sign-Magnitude Encoding for Efficient VLSI

904 TVPGTO164 Realization of Decimal Multiplication
(Tools / Xilinx ISE)

Sign-Magnitude Encoding for Efficient VLSI

905 TVPGTO165 Realization of Decimal Multiplication
(Tools / Tanner EDA)

Lightweight Hardware Architectures for the

906 TVPGTO174 Present Cipher in FPGA
(Tools / Xilinx Vivado)

Lightweight Hardware Architectures for the

907 TVPGTO175 Present Cipher in FPGA
(Tools / Xilinx ISE)

High Performance Parallel Decimal Multipliers

908 TVPGTO180 using Hybrid BCD Codes
(Tools / Xilinx Vivado)

High Performance Parallel Decimal Multipliers

909 TVPGTO181 using Hybrid BCD Codes
(Tools / Xilinx ISE)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
910 TVPGTO324
Compressors
(Tools / Xilinx Vivado)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
911 TVPGTO325
Compressors
(Tools / Xilinx ISE)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
912 TVMATO380
Compressors
(Tools / Xilinx Vivado)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
913 TVMATO381
Compressors
(Tools / Xilinx ISE)

Reliable Low-Latency Viterbi Algorithm

914 TVMATO38 Architecture Bench marked on ASIC & FPGA
(Tools / Xilinx Vivado)

Reliable Low-Latency Viterbi Algorithm

915 TVMATO39 Architecture Bench marked on ASIC & FPGA
(Tools / Xilinx ISE)

916 TVMATO136 Sign-Magnitude Encoding for Efficient VLSI

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Realization of Decimal Multiplication

(Tools / Xilinx Vivado)

Sign-Magnitude Encoding for Efficient VLSI

917 TVMATO137 Realization of Decimal Multiplication
(Tools / Xilinx ISE)

Lightweight Hardware Architectures for the

918 TVMATO148 Present Cipher in FPGA
(Tools / Xilinx Vivado)

Lightweight Hardware Architectures for the

919 TVMATO149 Present Cipher in FPGA
(Tools / Xilinx ISE)

High Performance Parallel Decimal Multipliers

920 TVMATO154 using Hybrid BCD Codes
(Tools / Xilinx Vivado)

High Performance Parallel Decimal Multipliers

921 TVMATO155 using Hybrid BCD Codes
(Tools / Xilinx ISE)

Fault Tolerant Parallel Filters with Efficient

922 TVPGFE179 Addition Structure
(Front End Domains / Arithmetic Core)

Fault Tolerant Parallel Filters with Efficient

923 TVMAFE217 Addition Structure
(Front End Domains / Arithmetic Core)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
924 TVPGFE182
Compressors
(Front End Domains / Arithmetic Core)

FPGA Implementation of Single Precision

Floating Point Multiplier using High Speed
925 TVMAFE220
Compressors
(Front End Domains / Arithmetic Core)

Sign-Magnitude Encoding for Efficient VLSI

926 TVPGFE204 Realization of Decimal Multiplication
(Front End Domains / Arithmetic Core)

Sign-Magnitude Encoding for Efficient VLSI

927 TVMAFE254 Realization of Decimal Multiplication
(Front End Domains / Arithmetic Core)

High Performance Parallel Decimal Multipliers

928 TVPGFE227 using Hybrid BCD Codes
(Front End Domains / Arithmetic Core)

High Performance Parallel Decimal Multipliers

929 TVMAFE282 using Hybrid BCD Codes
(Front End Domains / Arithmetic Core)

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

Lightweight Hardware Architectures for the

Present Cipher in FPGA
930 TVPGFE230
(Front End Domains / Communications and
Crypto Core)

Lightweight Hardware Architectures for the

931 TVMAFE285 Present Cipher in FPGA
(Front End Domains / Communications)

Reliable Low-Latency Viterbi Algorithm

932 TVPGFE250 Architecture Bench marked on ASIC & FPGA
(Front End Domains / FPGA)

Reliable Low-Latency Viterbi Algorithm

Architecture Bench marked on ASIC & FPGA
933 TVPGFE251
(Front End Domains / Communications and
Crypto Core)

Reliable Low-Latency Viterbi Algorithm

934 TVMAFE303 Architecture Bench marked on ASIC & FPGA
(Front End Domains / Communications)

Unequal Error Protection Code Derived from

935 TVPGTO158 Orthogonal Latin Square Code
(Tools / Xilinx Vivado)

Unequal Error Protection Code Derived from

936 TVPGTO159 Orthogonal Latin Square Code
(Tools / Xilinx ISE)

Unequal Error Protection Code Derived from

937 TVMATO128 Orthogonal Latin Square Code
(Tools / Xilinx Vivado)

Unequal Error Protection Code Derived from

938 TVMATO129 Orthogonal Latin Square Code
(Tools / Xilinx ISE)

Unequal Error Protection Code Derived from

939 TVMAFE242 Orthogonal Latin Square Code
(Front End Domains / Communications)

Unequal Error Protection Code Derived from

Orthogonal Latin Square Code
940 TVPGFE194
(Front End Domains / Communications and
Crypto Core)

In this paper, cascode topology with

Design and Analysis of a 2.4 GHz Fully inductively degenerated
Integrated 1.8V Power Amplifier in TSMC common-source CMOS power
941 TVMABE240 l80nm CMOS RF Process for Wireless amplifier is suggested with
Communication improved gain, isolation, better
(Back End Domains / Transistor Logic) stability and sufficient linearity over
the operating range

An Improved Low Power Sigma Delta ADC The main objective of this paper is
942 TVMABE225
Implemented in 0.25µm CMOS Process to design a power efficient sigma

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S.No Project Code Project Name Objective

delta ADC using telescopic op-amp

(Back End Domains / Low Power VLSI) as a integrator in this proposed
design of ADC.

In this paper, the Hamming code

encoder and decoder circuit is
implemented using transmission
Design of Hamming Code Encoding and
gate logic. The architecture is
Decoding Circuit Using Transmission Gate
943 TVMAFE353 simulated with different technologies
Logic
(16nm, 22nm, 32nm, and 45nm)
(Front End Domains / Communications)
with the help of TANNER EDA Tool
for the study of total power
dissipation of the circuit.

In this paper, the Hamming code

encoder and decoder circuit is
implemented using transmission
Design of Hamming Code Encoding and
gate logic. The architecture is
Decoding Circuit Using Transmission Gate
944 TVMABE108 simulated with different technologies
Logic
(16nm, 22nm, 32nm, and 45nm)
(Back End Domains / Transistor Logic)
with the help of TANNER EDA Tool
for the study of total power
dissipation of the circuit.

In this paper, the Hamming code

encoder and decoder circuit is
implemented using transmission
Design of Hamming Code Encoding and
gate logic. The architecture is
Decoding Circuit Using Transmission Gate
945 TVMATO662 simulated with different technologies
Logic
(16nm, 22nm, 32nm, and 45nm)
(Tools / Tanner EDA)
with the help of TANNER EDA Tool
for the study of total power
dissipation of the circuit.

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
946 TVPGTO268
using Wallace Tree and Vedic Multipliers
(Tools / Xilinx Vivado)

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
947 TVPGTO269
using Wallace Tree and Vedic Multipliers
(Tools / Xilinx ISE)

A Novel Realization of Reversible LFSR for its

948 TVPGTO296 Application in Cryptography
(Tools / Xilinx Vivado)

A Novel Realization of Reversible LFSR for its

949 TVPGTO297 Application in Cryptography
(Tools / Xilinx ISE)

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
950 TVMATO271
using Wallace Tree and Vedic Multipliers
(Tools / Xilinx Vivado)

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S.No Project Code Project Name Objective

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
951 TVMATO272
using Wallace Tree and Vedic Multipliers
(Tools / Xilinx ISE)

A Novel Realization of Reversible LFSR for its

952 TVMATO326 Application in Cryptography
(Tools / Xilinx Vivado)

A Novel Realization of Reversible LFSR for its

953 TVMATO327 Application in Cryptography
(Tools / Xilinx ISE)

A Class of SEC-DED-DAEC Codes Derived

954 TVMAFE135 from Orthogonal Latin Square Codes
(Front End Domains / Communications)

A Novel Realization of Reversible LFSR for its

955 TVMAFE144 Application in Cryptography
(Front End Domains / Testing)

A Novel Realization of Reversible LFSR for its

956 TVPGFE142 Application in Cryptography
(Front End Domains / Design for Testability)

This brief proposes a two-step

optimization technique for designing
An Efficient VLSI Architecture of a
a reconfigurable VLSI architecture
Reconfigurable Pulse-Shaping FIR
957 TVPGFE145 of an interpolation filter for multi
Interpolation Filter for Multistandard DUC
standard digital up converter (DUC)
(Front End Domains / DSP Core)
to reduce the power and area
consumption.

This brief proposes a two-step

optimization technique for designing
An Efficient VLSI Architecture of a
a reconfigurable VLSI architecture
Reconfigurable Pulse-Shaping FIR
958 TVMAFE151 of an interpolation filter for multi
Interpolation Filter for Multistandard DUC
standard digital up converter (DUC)
(Front End Domains / DSP Core)
to reduce the power and area
consumption.

959 TVMIFE89 Area-Delay Efficient Binary Adders in QCA

Area–Delay–Power Efficient Carry-Select

960 TVMI90
Adder

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
961 TVPGFE181
using Wallace Tree and Vedic Multipliers
(Front End Domains / DSP Core)

FPGA Implementation of Scalable

Microprogrammed FIR Filter Architectures
962 TVMAFE219
using Wallace Tree and Vedic Multipliers
(Front End Domains / DSP Core)

963 TVMI107 IMPLEMENTATION OF ALU USING VERILOG The objective of this project is to

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S.No Project Code Project Name Objective

follow a modular approach, where

each functional unit is implemented
HDL as a separate module, allowing for
easy testing, reusability, and future
enhancements.

A Combined SDC-SDF Architecture for Normal

964 TVPGFE119 IO Pipelined Radix-2 FFT
(Front End Domains / DSP Core)

A Combined SDC-SDF Architecture for Normal

965 TVMAFE136 IO Pipelined Radix-2 FFT
(Front End Domains / DSP Core)

A Combined SDC-SDF Architecture for Normal

966 TVPGTO302 IO Pipelined Radix-2 FFT
(Tools / Xilinx Vivado)

A Combined SDC-SDF Architecture for Normal

967 TVPGTO303 IO Pipelined Radix-2 FFT
(Tools / Xilinx ISE)

A Combined SDC-SDF Architecture for Normal

968 TVMATO342 IO Pipelined Radix-2 FFT
(Tools / Xilinx Vivado)

A Combined SDC-SDF Architecture for Normal

969 TVMATO343 IO Pipelined Radix-2 FFT
(Tools / Xilinx ISE)

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
970 TVPGTO25
Recording Systems
(Tools / Tanner EDA)

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
971 TVPGTO147
Recording Systems
(Tools / Cadence EDA)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
972 TVPGTO170
Scan-Based Logic BIST
(Tools / Xilinx Vivado)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
973 TVPGTO171
Scan-Based Logic BIST
(Tools / Xilinx ISE)

The main objective of this project is

A Novel Approach for Parallel CRC Generation to improve the speed of the CRC
974 TVPGTO298 for High Speed Applications generation by using f-matrix which is
(Tools / Xilinx Vivado) generated from the polynomial
equation

975 TVPGTO299 A Novel Approach for Parallel CRC Generation The main objective of this project is

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VLSI-Trendy Titles

S.No Project Code Project Name Objective

to improve the speed of the CRC

for High Speed Applications generation by using f-matrix which is
(Tools / Xilinx ISE) generated from the polynomial
equation

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
976 TVMATO231
System
(Tools / Xilinx Vivado)

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
977 TVMATO232
System
(Tools / Xilinx ISE)

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
978 TVMATO233
System
(Tools / Xilinx Vivado)

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
979 TVMATO234
System
(Tools / Xilinx ISE)

Test Versus Security Past and Present

980 TVMATO235
(Tools / Xilinx Vivado)

Test Versus Security Past and Present

981 TVMATO236
(Tools / Xilinx ISE)

This paper proposes novel

Reversible logic design for code
Energy Efficient Code Converters using
conversion such as Binary to Gray
982 TVMATO283 Reversible Logic Gates
code, Gray to Binary code, BCD to
(Tools / Xilinx Vivado)
Excess 3 code, Excess 3 to BCD
code.

This paper proposes novel

Reversible logic design for code
Energy Efficient Code Converters using
conversion such as Binary to Gray
983 TVMATO284 Reversible Logic Gates
code, Gray to Binary code, BCD to
(Tools / Xilinx ISE)
Excess 3 code, Excess 3 to BCD
code.

The main objective of this project is

A Novel Approach for Parallel CRC Generation to improve the speed of the CRC
984 TVMATO330 for High Speed Applications generation by using f-matrix which is
(Tools / Xilinx Vivado) generated from the polynomial
equation

The main objective of this project is

A Novel Approach for Parallel CRC Generation to improve the speed of the CRC
985 TVMATO331 for High Speed Applications generation by using f-matrix which is
(Tools / Xilinx ISE) generated from the polynomial
equation

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S.No Project Code Project Name Objective

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
986 TVMATO104
Recording Systems
(Tools / Xilinx Vivado)

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
987 TVMATO105
Recording Systems
(Tools / Xilinx ISE)

A Novel Five Input Multiple Function QCA

988 TVMATO106 Threshold Gate
(Tools / QCA)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
989 TVMATO144
Scan-Based Logic BIST
(Tools / Xilinx Vivado)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
990 TVMATO145
Scan-Based Logic BIST
(Tools / Xilinx ISE)

The main objective of this project is

A Novel Approach for Parallel CRC Generation
to improve the speed of the CRC
for High Speed Applications
991 TVPGFE141 generation by using f-matrix which is
(Front End Domains / Communications and
generated from the polynomial
Crypto Core)
equation

The main objective of this project is

A Novel Approach for Parallel CRC Generation to improve the speed of the CRC
992 TVMAFE142 for High Speed Applications generation by using f-matrix which is
(Front End Domains / Communications) generated from the polynomial
equation

The design of an Error Tolerant (ET)

Shift-and Add Multiplier is done. It
Design of Reversible MAC Unit, Shift and Add utilizes the concept
993 TVPGFE153 Multiplier using PSDRM Technique of error tolerant addition for
(Front End Domains / DSP Core) accumulation of partial products and
a ring counter for shifting of
multiplier bits and partial product.

The design of an Error Tolerant (ET)

Shift-and Add Multiplier is done. It
Design of Reversible MAC Unit, Shift and Add utilizes the concept
994 TVMAFE170 Multiplier using PSDRM Technique of error tolerant addition for
(Front End Domains / DSP Core) accumulation of partial products and
a ring counter for shifting of
multiplier bits and partial product.

This paper proposes novel

Energy Efficient Code Converters using
Reversible logic design for code
995 TVMAFE171 Reversible Logic Gates
conversion such as Binary to Gray
(Front End Domains / Arithmetic Core)
code, Gray to Binary code, BCD to

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S.No Project Code Project Name Objective

Excess 3 code, Excess 3 to BCD

code.

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
996 TVPGFE168 System
(Front End Domains / Communications and
Crypto Core)

VLSI Implementation of a Key Distribution

Server Based Data Security Scheme for RFID
997 TVMAFE202
System
(Front End Domains / Communications)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
998 TVPGFE232
Scan-Based Logic BIST
(Front End Domains / Design for Testability)

Low-Cost and High-Reduction Approaches for

Power Droop During Launch-On-Shift
999 TVMAFE287
Scan-Based Logic BIST
(Front End Domains / Testing)

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
1000 TVPGBE99
Recording Systems
(Back End Domains / Low Power VLSI)

A Power-Efficient Continuous-Time
Incremental Sigma-Delta ADC for Neural
1001 TVMABE98
Recording Systems
(Back End Domains / Low Power VLSI)

The main objective of this work is to

use Binary to Excess-1 Converter
Carry select adder using BEC and RCA
1002 TVPGFE286 (BEC) instead of RCA in the regular
(Front End Domains / Arithmetic Core)
CSLA to achieve high speed and
low power consumption.

In this project recursive approach

(Pipelined Adder Using Single-Rail
Recursive Approach to the Design of a Parallel Data Encoding) based PASTA Adder
1003 TVMABE210 Self-Timed Adder along mux and half- adder designed
(Back End Domains / Low Power VLSI) for enhancing the speed and
reducing the power and area
respectively.

In this project recursive approach

(Pipelined Adder Using Single-Rail
Recursive Approach to the Design of a Parallel Data Encoding) based PASTA Adder
1004 TVMABE211 Self-Timed Adder along mux and half- adder designed
(Back End Domains / Transistor Logic) for enhancing the speed and
reducing the power and area
respectively.

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S.No Project Code Project Name Objective

In this project recursive approach

(Pipelined Adder Using Single-Rail
Recursive Approach to the Design of a Parallel Data Encoding) based PASTA Adder
1005 TVPGTO925 Self-Timed Adder along mux and half- adder designed
(Tools / Tanner EDA) for enhancing the speed and
reducing the power and area
respectively.

Design of High Performance 64 Bit MAC Unit

1006 TVPGTO274
(Tools / Xilinx Vivado)

Design of High Performance 64 Bit MAC Unit

1007 TVPGTO275
(Tools / Xilinx ISE)

Design of High Performance 64 Bit MAC Unit

1008 TVMATO287
(Tools / Xilinx Vivado)

Design of High Performance 64 Bit MAC Unit

1009 TVMATO288
(Tools / Xilinx ISE)

Design of High Performance 64 Bit MAC Unit

1010 TVPGFE152
(Front End Domains / DSP Core)

Design of High Performance 64 Bit MAC Unit

1011 TVMAFE168
(Front End Domains / DSP Core)

Design of a Parallel Self-Timed Adder by Using

1012 TVMAFE235 Transmission Gate Logic Style
(Front End Domains / Testing)

Design of a Parallel Self-Timed Adder by Using

1013 TVMATO225 Transmission Gate Logic Style
(Tools / Xilinx Vivado)

Design of a Parallel Self-Timed Adder by Using

1014 TVMATO226 Transmission Gate Logic Style
(Tools / Xilinx ISE)

Test Versus Security Past and Present

1015 TVPGTO242
(Tools / Xilinx Vivado)

Test Versus Security Past and Present

1016 TVPGTO243
(Tools / Xilinx ISE)

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1017 TVPGTO244
Implementations
(Tools / Xilinx Vivado)

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1018 TVPGTO245
Implementations
(Tools / Xilinx ISE)

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1019 TVPGTO258 Coverage additionally uses LFSR reseeding to
(Tools / Xilinx Vivado) lower the amount of specified bits.

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S.No Project Code Project Name Objective

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1020 TVPGTO259 Coverage additionally uses LFSR reseeding to
(Tools / Xilinx ISE) lower the amount of specified bits.

This paper suggests three

topologies for the LMS adaptive
filter in light of these findings:
Critical-Path Analysis and Low-Complexity
1021 TVPGTO286 Implementation of the LMS Adaptive Algorithm There are three different designs: (i)
(Tools / Xilinx Vivado) Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

This paper suggests three

topologies for the LMS adaptive
filter in light of these findings:
Critical-Path Analysis and Low-Complexity
1022 TVPGTO287 Implementation of the LMS Adaptive Algorithm There are three different designs: (i)
(Tools / Xilinx ISE) Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1023 TVMATO237
Implementations
(Tools / Xilinx Vivado)

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1024 TVMATO238
Implementations
(Tools / Xilinx ISE)

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1025 TVMATO261 Coverage additionally uses LFSR reseeding to
(Tools / Xilinx Vivado) lower the amount of specified bits.

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1026 TVMATO262 Coverage additionally uses LFSR reseeding to
(Tools / Xilinx ISE) lower the amount of specified bits.

This paper suggests three

topologies for the LMS adaptive
filter in light of these findings:
Critical-Path Analysis and Low-Complexity
1027 TVMATO307 Implementation of the LMS Adaptive Algorithm There are three different designs: (i)
(Tools / Xilinx Vivado) Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

This paper suggests three

Critical-Path Analysis and Low-Complexity
topologies for the LMS adaptive
1028 TVMATO308 Implementation of the LMS Adaptive Algorithm
filter in light of these findings:
(Tools / Xilinx ISE)

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There are three different designs: (i)

Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

This paper suggests three

topologies for the LMS adaptive
filter in light of these findings:
Critical-Path Analysis and Low-Complexity
1029 TVPGFE147 Implementation of the LMS Adaptive Algorithm There are three different designs: (i)
(Front End Domains / DSP Core) Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

This paper suggests three

topologies for the LMS adaptive
filter in light of these findings:
Critical-Path Analysis and Low-Complexity
1030 TVMAFE155 Implementation of the LMS Adaptive Algorithm There are three different designs: (i)
(Front End Domains / DSP Core) Design 1 has no adaptation delays,
(ii) Design 2 has just one adaptation
delay, and (iii) Design 3 has two
adaptation delays.

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1031 TVPGFE159 Coverage additionally uses LFSR reseeding to
(Front End Domains / Design for Testability) lower the amount of specified bits.

LFSR-Reseeding Scheme for Achieving Test To improve encoding performance, it

1032 TVMAFE185 Coverage additionally uses LFSR reseeding to
(Front End Domains / Testing) lower the amount of specified bits.

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1033 TVPGFE166
Implementations
(Front End Domains / Arithmetic Core)

Reverse Converter Design Via Parallel-Prefix

Adders Novel Components, Methodology and
1034 TVMAFE200
Implementations
(Front End Domains / Arithmetic Core)

Test Versus Security Past and Present

1035 TVMAFE201
(Front End Domains / Testing)

Test Versus Security Past and Present

1036 TVPGFE167
(Front End Domains / Design for Testability)

Low-Cost FIR Filter Designs based on

Faithfully Rounded Truncated Multiplier
1037 TVMATO255
Constant Multiplication or Accumulation
(Tools / Xilinx Vivado)

1038 TVMATO256 Low-Cost FIR Filter Designs based on

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Faithfully Rounded Truncated Multiplier

Constant Multiplication or Accumulation
(Tools / Xilinx ISE)

the proposed 64-bit hybrid adder is

superior to other referenced adders,
Low Voltage and Low Power 64-Bit Hybrid
and has 203 ps delay time, 9.58 mw
Adder Design Based on Radix-4 Prefix Tree
1039 TVMATO257 average power, and 96×76 [1]m2
Structure
area.
(Tools / Xilinx Vivado)

the proposed 64-bit hybrid adder is

superior to other referenced adders,
Low Voltage and Low Power 64-Bit Hybrid
and has 203 ps delay time, 9.58 mw
Adder Design Based on Radix-4 Prefix Tree
1040 TVMATO258 average power, and 96×76 [1]m2
Structure
area.
(Tools / Xilinx ISE)

In this paper, Carry Select Adder

(CSA) architectures are proposed
Design of Low power and High Speed Carry using parallel prefix adders. Instead
1041 TVMATO285 Select Adder using Brent Kung Adder of using dual Ripple Carry Adders
(Tools / Xilinx Vivado) (RCA), parallel prefix adder i.e.,
Brent Kung (BK) adder is used to
design Regular Linear CSA.

In this paper, Carry Select Adder

(CSA) architectures are proposed
Design of Low power and High Speed Carry using parallel prefix adders. Instead
1042 TVMATO286 Select Adder using Brent Kung Adder of using dual Ripple Carry Adders
(Tools / Xilinx ISE) (RCA), parallel prefix adder i.e.,
Brent Kung (BK) adder is used to
design Regular Linear CSA.

In this paper, Carry Select Adder

(CSA) architectures are proposed
Design of Low power and High Speed Carry using parallel prefix adders. Instead
1043 TVMAFE169 Select Adder using Brent Kung Adder of using dual Ripple Carry Adders
(Front End Domains / Arithmetic Core) (RCA), parallel prefix adder i.e.,
Brent Kung (BK) adder is used to
design Regular Linear CSA.

the proposed 64-bit hybrid adder is

superior to other referenced adders,
Low Voltage and Low Power 64-Bit Hybrid
and has 203 ps delay time, 9.58 mw
Adder Design Based on Radix-4 Prefix Tree
1044 TVMAFE188 average power, and 96×76 [1]m2
Structure
area.
(Front End Domains / Arithmetic Core)

Low-Cost FIR Filter Designs based on

Faithfully Rounded Truncated Multiplier
1045 TVMAFE189
Constant Multiplication or Accumulation
(Front End Domains / DSP Core)

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The ultra-low power consumption

makes this amplifier suitable for
A 430nW 64nV Current-Reuse Telescopic
potential use in implantable neuro
1046 TVMABE257 Amplifier for Neural Recording Applications
technologies, where minimizing
(Back End Domains / Cadence EDA)
power consumption is critical for
long-term operation

The main aim of this project is to

implement the multiplier design with
Analysis of Leakage Power Reduction
different leakage power reduction
1047 TVPGTO49 Techniques for Low Power VLSI Design
techniques. Lector, Dual VT,
(Tools / Tanner EDA)
MTCMOS techniques are used to
implement the multiplier circuit.

The main aim of this project is to

implement the multiplier design with
Analysis of Leakage Power Reduction
different leakage power reduction
1048 TVPGTO73 Techniques for Low Power VLSI Design
techniques. Lector, Dual VT,
(Tools / Cadence EDA)
MTCMOS techniques are used to
implement the multiplier circuit.

Design and Implementation of High Speed

1049 TVPGTO127 Carry Select Adder
(Tools / Xilinx Vivado)

Design and Implementation of High Speed

1050 TVPGTO128 Carry Select Adder
(Tools / Xilinx ISE)

Design and Implementation of 32 -bit RISC

1051 TVPGTO205 Processor using Xilinx
(Tools / Xilinx Vivado)

Design and Implementation of 32 -bit RISC

1052 TVPGTO206 Processor using Xilinx
(Tools / Xilinx ISE)

Design and Implementation of 32 -bit RISC

1053 TVPGTO207 Processor using Xilinx
(Tools / Xilinx Vivado)

Design and Implementation of 32 -bit RISC

1054 TVPGTO208 Processor using Xilinx
(Tools / Xilinx ISE)

Design and Implementation of High Speed

1055 TVMATO81 Carry Select Adder
(Tools / Xilinx Vivado)

Design and Implementation of High Speed

1056 TVMATO82 Carry Select Adder
(Tools / Xilinx ISE)

Design and Implementation of 32 -bit RISC

1057 TVMATO184 Processor using Xilinx
(Tools / Xilinx Vivado)

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Design and Implementation of 32 -bit RISC

1058 TVMATO185 Processor using Xilinx
(Tools / Xilinx ISE)

Design and Implementation of 32 -bit RISC

1059 TVPGFE213 Processor using Xilinx
(Front End Domains / DSP Core)

Design and Implementation of 32 -bit RISC

1060 TVMAFE265 Processor using Xilinx
(Front End Domains / DSP Core)

Design and Implementation of High Speed

1061 TVPGFE263 Carry Select Adder
(Front End Domains / Arithmetic Core)

Design and Implementation of High Speed

1062 TVMAFE316 Carry Select Adder
(Front End Domains / Arithmetic Core)

The main aim of this project is to

implement the multiplier design with
Analysis of Leakage Power Reduction
different leakage power reduction
1063 TVPGBE106 Techniques for Low Power VLSI Design
techniques. Lector, Dual VT,
(Back End Domains / Transistor Logic)
MTCMOS techniques are used to
implement the multiplier circuit.

Design of Reversible Multiplier Architecture

1064 TVPGTO197 using Vedic Mathematics
(Tools / Xilinx Vivado)

Design of Reversible Multiplier Architecture

1065 TVPGTO198 using Vedic Mathematics
(Tools / Xilinx ISE)

Design of Reversible Multiplier Architecture

1066 TVMATO172 using Vedic Mathematics
(Tools / Xilinx Vivado)

Design of Reversible Multiplier Architecture

1067 TVMATO173 using Vedic Mathematics
(Tools / Xilinx ISE)

Design of Reversible Multiplier Architecture

1068 TVPGFE218 using Vedic Mathematics
(Front End Domains / Arithmetic Core)

Design of Reversible Multiplier Architecture

1069 TVMAFE274 using Vedic Mathematics
(Front End Domains / Arithmetic Core)

Minimizing Dynamic Power: The

primary goal is to reduce the
A New Design of XOR-XNOR gates for low dynamic power consumption, which
1070 TVMI114
power application is a significant component of total
power dissipation in digital circuits.
XOR and XNOR gates are

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Website: www.takeoffprojects.com Phone: +91 9030333433, +91 8776681444

VLSI-Trendy Titles

S.No Project Code Project Name Objective

fundamental components in many

digital systems, including arithmetic
circuits, encoders, decoders, and
error detection/correction schemes.
Optimizing these gates for low
power can have a broad impact on
the overall power efficiency of these
systems.

This article primarily focuses on the

novel design of full adders at the
logic level and also highlights a
High Speed Gate Level Synchronous Full
1071 TVMI111 comparison with many other existing
Adder Designs
gate level
solutions, from performance and
area perspectives.

( Page 130 ) Email: [email protected]

Website: www.takeoffprojects.com Phone: +91 9030333433, +91 8776681444