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System Verilog - 1-15

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28 views15 pages

System Verilog - 1-15

Uploaded by

23el308
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Verification Using

System Verilog
(IEEE standard1800)
System on Chip
VLSI/Chip Design Flow
What is SystemVerilog ?
 Hardware Description Language (HDL) like Verilog and
VHDL are used to describe hardware behavior so that it
can be converted to digital blocks made up of
combinational gates and sequential elements.

 In order to verify that the hardware description in HDL is


correct, there is a need for a language with more
features in OOP that will support complicated testing
procedures and is often called a Hardware Verification
Language.

 SystemVerilog is an extension of Verilog with many such


verification features that allow engineers to verify the
design using complex testbench structures and random
stimuli in simulation.
Why is Verilog not preferred ?
Back in the 1990's, Verilog was the primary
language to verify functionality of designs that
were small, not very complex and had less
features.
As design complexity increases, so does the
requirement of better tools to design and verify
it.
SystemVerilog is far superior to Verilog because
of its ability to perform constrained random
stimuli, use OOP features in testbench
construction, functional coverage, assertions
among many others.
What is verification ?
 Verification is the process of ensuring that a given hardware
design works as expected.

 Chip design is a very extensive and time consuming process


and costs millions to fabricate.

 Functional defects in the design if caught at an earlier stage in


the design process will help save costs.

 If a bug is found later on in the design flow, then all of the


design steps have to be repeated again which will use up
more resources, money and time.

 If the entire design flow has to be repeated, then its called


a respin of the chip.
What is the purpose of a testbench ?
 A testbench allows us to verify the functionality of a
design through simulations. It is a container where the
design is placed and driven with different input
stimulus.
 Generate different types of input stimulus
 Drive the design inputs with the generated stimulus
 Allow the design to process input and provide an
output
 Check the output with expected behavior to find
functional defects
 If a functional bug is found, then change the design to
fix the bug
 Perform the above steps until there are no more
functional defects
Components of a testbench
What is DUT ?

DUT stands for Design Under Test and is the


hardware design written in Verilog or VHDL.

DUT is a term typically used in post validation


of the silicon once the chip is fabricated.

In pre validation, it is also called


as Design Under Verification, DUV in short.
What is an
interface ?

If the design contained hundreds of port


signals it would be cumbersome to connect,
maintain and re-use those signals.
Instead, we can place all the design input-
output ports into a container which becomes
an interface to the DUT.
The design can then be driven with values
through this interface.
What is a driver ?

The driver is the verification component that


does the pin-wiggling of the DUT, through a
task defined in the interface.
When the driver has to drive some input
values to the design, it simply has to call this
pre-defined task in the interface, without
actually knowing the timing relation between
these signals.
What is a generator

 The generator is a verification component that can


create valid data transactions and send them to the
driver.
 The driver can then simply drive the data provided to it
by the generator through the interface.
 Data transactions are implemented as class objects
shown by the blue squares in the image above.
 It is the job of the driver to get the data object and
translate it into something the DUT can understand.
Why is a monitor
required?

Until now, how data is driven to the DUT was


discussed. But that's only half way through,
because our primary aim is to verify the design.
The DUT processes input data and sends the
result to the output pins.
The monitor picks up the processed data,
converts it into a data object and sends it to the
scoreboard.
What is the purpose
of a scoreboard?

 The Scoreboard can have a reference model that behaves


the same way as the DUT.
 This model reflects the expected behavior of the DUT.
 Input sent to the DUT is also sent to this reference model.
 So if the DUT has a functional problem, then the output
from the DUT will not match the output from our reference
model.
 Comparison of outputs from the design and the reference
model will tell us if there is a functional defect in the
design.
Why is an environment required and
What does the test do ?
 It makes the verification more flexible and scalable because more
components can be plugged into the same environment for a future
project.
 The test will instantiate an object of the environment and configure it
the way the test wants to.
 Remember that we will most probably have thousands of tests and it is
not feasible to make direct changes to the environment for each test.
 Instead we want certain knobs/parameters in the environment that
can be tweaked for each test. That way, the test will have a higher
control over stimulus generation and will be more effective.
 Here, we have talked about how a simple testbench looks like. In real
projects, there'll be many such components plugged in to do various
tasks at higher levels of abstraction.
 If we had to verify a simple digital counter with maximum 50 lines of
RTL code, yea, this would suffice. But, when complexity increases,
there will be a need to deal with more abstraction.

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