Computer Organization (PC402CS) 1

UNIT-IV
Syllabus: Stacks and subroutines, interfacing peripherals - Basic interfacing concepts, interfacing output displays,
Interfacing input keyboards. Interrupts - 8085 Interrupts, Programmable Interrupt Controller (8259A). Direct Memory
Access (DMA) - DMA Controller (Intel 8257), Interfacing 8085 with Digital to Analog and Analog to Digital converters.
CO4: Describe the interrupts of 8085 processor and analyse it’s interfacing with I/O devices and other micro controllers
like 8259,8257 and A/D and D/A converters.
Lecture Notes
STACK
Stack is the upper part of the memory used for storing temporary information. It is a Last In First Out Memory (LIFO). In
8085, it is accessed using PUSH and POP instructions. During pushing, the stack operates in a decrement then store style.
The stack pointer is decremented first, then the information is placed on the stack. During poping, the stack operates in a
use then increment style. The information is retrieved from the top of the the stack and then the pointer is incremented. The
SP pointer always points to the top of the stack.
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PROGRAM STATUS WORD (PSW)

The 8085 recognizes one additional register pair called the PSW (Program Status Word). This register pair is made up of
the Accumulator and the Flags registers. It is possible to push the PSW onto the stack, do whatever operations are needed,
then POP it off of the stack. The result is that the contents of the Accumulator and the status of the Flags are returned to
what they were before the operations were executed.
SUBROUTINES
A subroutine is a group of instructions that will be used repeatedly in different locations of the program. Rather than repeat
the same instructions several times, they can be grouped into a subroutine that is called from the different locations. In
Assembly language, a subroutine can exist anywhere in the code. However, it is customary to place subroutines separately
from the main program. The 8085 has two instructions for dealing with subroutines. The CALL instruction is used to
redirect program execution to the subroutine. The RET instruction is used to return the execution to the calling routine.
CALL
CALL 4000H (3 byte instruction)
When CALL instruction is fetched, the MP knows that the next two Memory location contains 16bit subroutine address in
the memory.

Work flow of CALL instruction

MP Reads the subroutine address from the next two memory location and stores the higher order 8bit of the address in the
W register and stores the lower order 8bit of the address in the Z register. Push the address of the instruction immediately
following the CALL onto the stack [Return address]. Loads the program counter with the 16-bit address supplied with the
CALL instruction from WZ register as shown in fig.
RET (1 byte instruction)
Retrieve the return address from the top of the stack. Load the program counter with the return address as seen in fig
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Fig Work flow of RET instruction

The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data,
RD, WR, and IO/M lines are stated.
For Example:

8085 INTERRUPT:
An interrupt is a signal initiated by an external device to the microprocessor. Once this signal is received, the microprocessor
completes the execution of the current instruction and responds to the interrupt.
SOFTWARE INTERRUPTS OF 8085
The software interrupts are program instructions. When the instruction is executed, the processor executes an interrupt
service routine stored in the vector address of the software interrupt instruction. The software interrupts of 8085 are RST 0,
RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.
The vector addresses of software interrupts are given in table below
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The software interrupt instructions are included at the appropriate (or required) place in the main program. When the
processor encounters the software instruction, it pushes the content of PC (Program Counter) to stack. Then loads the Vector
address in PC and starts executing the Interrupt Service Routine (ISR) stored in this vector address. At the end of ISR, a
return instruction - RET will be placed. When the RET instruction is executed, the processor POP the content of stack to
PC. Hence the processor control returns to the main program after servicing the interrupt. Execution of ISR is referred to
as servicing of interrupt. All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked
and they cannot be disabled. The software interrupts are RST0, RST1, … RST7 (8 Nos).

HARDWARE INTERRUPTS OF 8085

These are the interrupts provided as signals to the microprocessor. There are five interrupt signals in 8085. They are Trap,
RST 7.5, RST 6.5, RST 5.5 and INTR. The priority of the interrupts is from TRAP to INTR. The program executed for the
service of the interrupting device is called the service routine.
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TRAP
1. This interrupt is a Non-Maskable interrupt (NMI). It is unaffected by any mask or interrupt enable.
2. TRAP is the highest priority and vectored interrupt(as vector address is fixed i.e. memory location where to transfer
control).
3. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is
acknowledged.
4. In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
5. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same
time then HOLD is recognized first and then TRAP is recognized).
6. There are two ways to clear TRAP interrupt. • By resetting microprocessor (External signal)
• By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5
• The RST 7.5 interrupt is a Maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. i.e. Input goes to high and no need to maintain high state until it recognized.
• Maskable interrupt
It is disabled by,
• DI, SIM instruction
• System or processor reset.
• After reorganization of interrupt.
RST 6.5 and 5.5
• The RST 6.5 and RST 5.5 both are level triggered (i.e.) Input goes to high and stay high until it recognized.
• Maskable interrupt
It is disabled by,
• DI, SIM instruction
• System or processor reset.
• After reorganization of interrupt.
• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
These interrupts are classified further into two classes based on the destination address and response. Based on the service
routine address, interrupts are classified in to vectored and nonvectored interrupt.
VECTORED INTERRUPT:
If the address of the service routine is known to the microprocessor, i.e. if the service routine begins at a predefined address,
then the interrupts are called vectored interrupts. The vectored address is calculated as (nx8)16 where n is the number of
RST.
For example:
The vectored address of RST 7.5 is 7.5 x 8=60.0
60 in hexadecimal number system is 003C. Therefore the branching address of RST 7.5 is 003C.
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NON VECTORED INTERRUPT:

The address of the service routine is not known in prior to the microprocessor. It is sent by the interrupting device. When
the interrupt flipflop is enabled and INTR is high, microprocessor executes the current instruction and makes INTA low.
Based on the flexibility to enable or disable interrupt, the interrupts are classified as maskable interrupt and non maskable
interrupt.
Maskable Interrupt: Even if the interrupt signals are high, microprocessor will respond to these signals only when
interrupt flip flop is enabled. Example RST 7.5, RST 6.5, RST 5.5, INTR
Non-Maskable Interrupt: Once the signal is enabled, the microprocessor immediately responds to this interrupt. Example:
TRAP

INTEL 8259A Programmable Interrupt Controller

The 8259A is a programmable interrupt controller specially designed to work with Intel microprocessor 8080, 8085A, 8086,
8088. The main features of 8259A programmable interrupt controller are given below:
1)It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the processor in place of one
INTR (in 8085A)/INT(in 8086) pin.
2)The chip can vector an interrupt request anywhere in the memory map from 0000H to FFFFH in 8085A microprocessor.
However, all the eight interrupts are spaced at an interval of either four or eight locations. This eliminates the major
drawback of 8085A interrupts in which all interrupts are vectored to memory location on page 00H i.e., TRAP, RST7.5,
RST6.5 and RST5.5 are vectored to memory locations 0024H, 003CH, 0034H and 002CH respectively.
3)It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of interrupts can be changed under
running condition. Some of the desired lower priority interrupts may be allowed to be acknowledged during the service of
higher priority interrupts.
4)Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5 and RST5.5 interrupts of 8085A.
5)The status of pending interrupts, in service interrupts, and masked interrupts can be read at any time similar to RST
interrupts of 8085A.
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6)The chip can be programmed to accept interrupt requests either as level triggered or edge triggered interrupt request
unlike your RST interrupts where some are edge triggered and some are level triggered. However, all interrupts must be
either level triggered or edge triggered.
7)If required, nine 8259As can be cascaded in a master-slave configuration mode to handle 64 interrupt inputs. In this case,
the interrupting devices send their interrupt requests either to slave 8259A or to master 8259A directly. The slave 8259As
send their interrupt to master interrupt request inputs and the master will send a single interrupt to microprocessor interrupt
pin INTR/INT.

The 8259 A is contained in a 28 dual-in-line package that requires only +5V supply voltage. The 8259A is upward
compatible with 8259. The main difference between the two is that the 8259A can be used with Intel 8086/8088 processor.
It also includes additional features such as level triggered mode, buffered mode and automatic end of interrupt mode.
The pin diagram and internal block diagram of PIC is shown in figure. The pins are defined as follows:
C̅̅̅̅̅̅ S̅̅̅ (Chip Select signal): To access this chip, chip select signal ̅C̅S̅ is made low. A LOW on this pin enables R̅D̅ &
W̅ R̅ communication between the CPU and the 8259A. This signal is made LOW by decoding the addresses assigned to
this chip. Therefore, this pin is connected to address bus through the decoder logic circuit. Interrupt acknowledge functions
to transfer the control to interrupt service subroutine are independent of ̅C̅S̅.
W̅̅̅̅̅̅ R̅̅̅ (Write signal): A low on this pin. When C̅S̅ is low enables the 8259 A to accept command words from CPU.
̅̅̅R̅̅̅D̅̅̅ (Read signal): A low on this pin when C̅S̅ is low enables this 8259A to release status (pending interrupts or
in-service interrupts or masked interrupts) on to the data bus for the CPU. The status includes the contents of IMR (interrupt
mask register) or ISR (interrupt service register) or IRR (interrupt request register) or a priority level.
D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information is transferred via this data bus.
This bus is connected to BDB of 8085A.
CAS2-CAS0 (Cascade lines): The CAS2-0 lines form a local 8259A bus to control multiple 8259As in master-slave
configuration, i.e., to identify a particular slave 8259A to be accessed for transfer of vector information. These pins are
automatically set as output pins for master 8259A and input pins for a slave 8259A once the chips are programmed as
master or slave.
S̅̅̅̅̅̅ P̅̅̅/E̅̅̅̅̅̅ N̅̅̅ (Salve Program/Enable Buffer): This is a dual function pin.
When the chip is programmed in buffered mode, the pin can be used as an output and when not in the buffered mode it is
used as an input. In non-buffered mode it is used as an input pin to determine whether the 8259A is to be used as a master
(S̅P̅/ ̅E̅N̅ = 1) or as a slave (S̅P̅/ ̅E̅N̅ = 0). In buffered mode, normally data bus buffers are used. These buffers need to be
enabled or disabled during transfer of vector information depending upon whether 80259A is connected before the buffer
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or after the buffer. To disable/enable the data bus transceivers (buffers) when data are being transferred from the 8259A to
the CPU, this pin is made low or high.
INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,
thus it is connected to the CPU’s interrupt pin (INTR). In case of master-slave configuration, the interrupt pin of slave
8259A is connected to interrupt request input of master 8259A.
I̅̅̅ N̅̅̅̅̅̅ T̅̅̅A̅̅̅ (Interrupt Acknowledge): This pin is used to enable 8259A interrupt vector data on the data bus by a sequence
of interrupt acknowledge pulses issued by the CPU.
IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt request input pins. An interrupt request is executed
by raising an IR input (low to high), and holding it high until it is acknowledged. (Edge triggered mode) or just by a high
level on an interrupt request input (Level triggered mode).
A0 (A0 address line): This pin acts in conjunction with the R̅D̅ , ̅W̅R̅ & C̅S̅ pins. It is used by the 8259A to
send various command words from the CPU and to read the status. It is normally connected to the CPU A0 address line.
Two addresses are assigned/ reserved in the I/O address space for each 8259A in the system- one with A0 =0 is called even
address and other with A0 = 1 is called odd address.
Functional Description:
The 8259A (PIC) has eight interrupt request inputs – IR7 - IR0. The 8259A uses its INT output to interrupt the 8085A via
INTR pin. The 8259A receives interrupt acknowledge pulses from the 𝜇𝑝 at its I̅ N̅T̅A̅ input. Vector address, used by the
8085A to transfer control to the service subroutine of the interrupting device, is provided by the 8259A on the data bus. The
8259A is a programmable device that must be initialized by command words sent by the microprocessor. After initialization
the 8259A mode of operation can be changed by operation command words from the microprocessor.

The descriptions of various blocks are given below:

Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control
words and status information from the microprocessor to PIC and from PIC to microprocessor respectively, are transferred
through the data bus buffer.
Read/Write & Control Logic: The function of this block is to accept output commands sent from the CPU. It contains the
initialization command word (ICW) registers and operation command word (OCW) registers which store the various control
formats for device operation. This function block also allows the status of 8259A to be transferred to the data bus.
Interrupt Request Register (IRR): Interrupt request register (IRR) stores all the interrupt inputs that are requesting
service. It is an 8-bit register – one bit for each interrupt request. Basically, it keeps track of which interrupt inputs are
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asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR
will be set. The content of this register can be read to know the status of pending interrupts.
Interrupt Mask Register (IMR): The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request
inputs. This is also an 8-bit register. Each bit in this register corresponds to the interrupt input with the same number. The
IMR operates on the IRR. Masking of higher priority input will not affect the interrupt request lines of lower priority. To
unmask any interrupt the corresponding bit is set ‘0’.
In-service Register (ISR): The in-service register keeps track of which interrupt inputs are currently being serviced. For
each input that is currently being serviced the corresponding bit of in-service register (ISR) will be set. In 8259A, during
the service of an interrupt request, if another higher priority interrupt becomes active, it will be acknowledged and the
control will be transferred from lower priority interrupt service subroutine (ISS) to higher priority ISS. Thus, more than one
bit of ISR will be set indicating the number of interrupts being serviced.
Each of these 3-registers can be read as status register.
Priority Resolver: This logic block determines the priorities of the interrupts set in the IRR. It takes the information from
IRR, IMR and ISR to determine whether the new interrupt request is having highest priority or not. If the new interrupt
request is having the highest priority, it is selected and processed. The corresponding bit of ISR will be set during interrupt
acknowledge machine cycle.
Cascade Buffer/Comparator: This function block stores and compares the IDs of all 8259A’s in the system. The
associated 3-I/O lines (CAS2-CAS0) are outputs when 8259A is used as a master and are inputs when 8259A is used as a
slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS2-0 lines. The slave 8259As
compare this ID with their own programmed ID. Thus selected 8259A will send its pre-programmed subroutine address on
to the data bus during the next one or two successive IN̅ T̅ A̅ pulses.
DMA CONTROLLER 8257
In microprocessor based system, data transfer can be controlled by either software or hardware. To transfer data
microprocessor has to do the following tasks:
Fetch the instruction Decode the instruction Execution of the instruction

 Microprocessor needs some amount of time to complete these tasks. But this data transfer is not suitable for large
data transfer such as data transfer from magnetic disk or optical disk to memory. In this situation hardware
controlled data transfer technique is required.
 The Direct Memory Access or DMA mode of data transfer is the fastest amongst all the modes of data transfer.
 In this mode, the device may transfer data directly to/from memory without any interference from the CPU.
 Intel‘s 8257 is a four channel DMA controller designed to be interfaced with their family of microprocessors. Each
channel can be independently programmable to transfer up to 64kb of data by DMA. Each channel can be
independently perform read transfer, write transfer and verify transfer.
 In maximum mode of the microprocessor RQ/GT pin is used as bus request input.
 On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum mode) from the CPU, the
requesting devices gets the access of the bus, and it completes the required number of DMA cycles for the data
transfer and then hands over the control of the bus back to the CPU.
Direct Memory Access (DMA)
• During any given bus cycle, one of the system components connected to the system bus is given control of the bus.
This component is said to be the master during that cycle and the component it is communicating with is said to be
the slave.
• The CPU with its bus control logic is normally the master, but other specially designed components can gain control
of the bus by sending a bus request to the CPU.
 After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the
request will become the master.
 Taking control of the bus for a bus cycle is called cycle stealing.
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 The DMA data transfer is initiated only after receiving HLDA signal from the CPU.
 The 8257, on behalf of the devices, requests the CPU for bus access using local bus request input i.e. HOLD in
minimum mode.
Internal Architecture of 8257

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA .
• Initially, when any device has to send data between the device and the memory, the device has to send
DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control
over bus and acknowledges the HOLD request through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses between
the CPU, memory, and I/O devices.
• The chip support four DMA channels, i.e. four peripheral devices can independently request for DMA data
transfer through these channels at a time.
The DMA controller has
• 8-bit internal data buffer,
• a read/write unit,
• a control unit,
• a priority resolving unit along with a set of registers.
The 8257 performs the DMA operation over four independent DMA channels.
•Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal count register.
•There are two common registers for all the channels, namely, mode set register and status register. Thus there are a total
of ten registers.
The CPU selects one of these ten registers using address lines Ao-A3. Table shows how the Ao-A3 bits may be used for
selecting one of these registers.
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Mode Set Register

• The mode set register is used for programming the 8257 as per the requirements of the system.
• The function of the mode set register is to enable the DMA channels individually and also to set the
various mode of operation.
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• The DMA channel should not be enabled till the DMA address register and the terminal count register
contain valid information; otherwise, an unwanted DMA request may initiate a DMA cycle, probably
destroying the valid memory data.
• The bits Do -D3 enable one of the four DMA channels of 8257. For example, if Do is = ‘1‘, channel 0 is
enabled. If bit 4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is enabled.
• The DMA channel should not be enabled till the DMA address register and the terminal count register
contain valid information; otherwise, an unwanted DMA request may initiate a DMA cycle, probably
destroying the valid memory data.
• The bits Do -D3 enable one of the four DMA channels of 8257. For example, if Do is = ‘1‘, channel 0 is
enabled. If bit 4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is enabled.
• The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without immediate
software intervention between the two successive blocks.
• The channel 2 registers are used as usual, while the channel 3 registers are used to store the block
initialisation parameters, i.e. the DMA starting address and terminal count.

Status Register
• The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the terminal
count status for the four individual channels.
• If any of these bits is set, it indicates that the specific channel has reached the terminal count condition.
These bits remain set till either the status is read by the CPU or the 8257 is reset.

If the update flag is set, the contents of the channel 3 registers are reloaded to the corresponding registers of channel 2
whenever the channel 2 reaches a terminal count condition, after transferring one block and the next block is to be
transferred using the auto load feature of 8257.
The update flag is set every time; the channel 2 registers are loaded with contents of the channel 3 registers. It is cleared by
the completion of the first DMA cycle of the new block. This register can only read.
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Signal Description of 8257 DRQo-DRQ3:

These are the four individual channel DMA request inputs, used by the peripheral devices for requesting the DMA services.
The DRQo has the highest priority while DRQ3 has the lowest one, if the fixed priority mode is selected.
DACKo-DACK3: These are the active-low DMA acknowledge output lines which inform the requesting peripheral that
the request has been honoured and the bus is relinquished by the CPU. These lines may act as strobe lines for the requesting
devices.

Do-D7:
• These are bidirectional, data lines used to interface the system bus with the internal data bus of 8257. These lines carry
command words to 8257 and status word from 8257, inslave mode, i.e. under the control of CPU. The data over these
lines may be transferred in both the directions. When the 8257 is the bus master (master mode, i.e. not under CPU
control), it uses Do-D7 lines to send higher byte of the generated address to the latch. This address is further latched
using ADSTB signal. the address is transferred over Do- D7 during the first clock cycle of the DMA cycle. During the
rest of the period, data is available on the data bus.
IOR:
• This is an active-low bidirectional tristate input line that acts as an input in the slave mode. In slave mode, this input
signal is used by the CPU to read internal registers of 8257.This line acts output in master mode. In master mode, this
signal is used to read data from a peripheral during a memory write cycle.

IOW:
• This is an active low bidirectional tristate line that acts as input in slave mode to load the contents of the data bus to
the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master
mode, it is a control output that loads the data to a peripheral during DMA memory read cycle (write to peripheral).
CLK:
• This is a clock frequency input required to derive basic system timings for the internal operation of 8257.
RESET:
• This active-high asynchronous input is disables all the DMA channels by clearing the mode register and tri states all
the control lines.

Ao-A3:
• These are the four least significant address lines. In slave mode, they act as input which selects one of the registers to
be read or written. In the master mode, they are the four least significant memory address output lines generated by
8257.

CS:
• This is an active-low chip select line that enables the read/write operations from/to 8257, in slave mode. In the master
mode, it is automatically disabled to prevent the chip from getting selected (by CPU) while performing the DMA
operation.
A4-A7:
• This is the higher nibble of the lower byte address generated by 8257 during the master mode of DMA operation.
READY:
• This is an active-high asynchronous input used to stretch memory read and write cycles of 8257 by inserting wait
states. This is used while interfacing slower peripherals..
HRQ:
The hold request output requests the access of the system bus.
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HLDA:
The CPU drives this input to the DMA controller high, while granting the bus to the device. This pin is connected to the
HLDA output of the CPU. This input, if high, indicates to the DMA controller that the bus has been granted to the requesting
peripheral by the CPU.

MEMR:
This active –low memory read output is used to read data from the addressed memory locations during DMA read cycles.
MEMW:
This active-low three state output is used to write data to the addressed memory location during DMA write operation.
ADST:
This output from 8257 strobes the higher byte of the memory address generated by the DMA controller into the latches.
AEN:
This output is used to disable the system data bus and the control the bus driven by the CPU, this may be used to disable
the system address and data bus by using the enable input of the bus drivers to inhibit the non-DMA devices from responding
during DMA operations. If the 8257 is I/O mapped, this should be used to disable the other I/O devices, when the DMA
controller addresses is on the address bus.
TC:
If the TC STOP bit in the mode set register is set, the selected channel will be disabled at the end of the DMA cycle. The
TC pin is activated when the 14-bit content of the terminal count register of the selected channel becomes equal to zero.
The lower order 14 bits of the terminal count register are to be programmed with a 14-bit equivalent of (n-1), if n is the
desired number of DMA cycles.
Vcc:
This is a +5v supply pin required for operation of the circuit.
GND:
This is a return line for the supply (ground pin of the IC).
Interfacing 8257 with 8086
• Once a DMA controller is initialized by a CPU property, it is ready to take control of the system bus on a DMA request,
either from a peripheral or itself (in case of memory-to memory transfer).
• The DMA controller sends a HOLD request to the CPU and waits for the CPU to assert the HLDA signal. The CPU
relinquishes the control of the bus before asserting the HLDA signal
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Once the HLDA signal goes high, the DMA controller activates the DACK signal to the requesting peripheral and gains
the control of the system bus.
The DMA controller is the sole master of the bus, till the DMA operation is over.
The CPU remains in the HOLD status (all of its signals are tristate except HOLD and HLDA), till the DMA controller is
the master of the bus.
In other words, the DMA controller interfacing circuit implements a switching arrangement for the address, data and control
busses of the memory and peripheral subsystem from/to the CPU to/from the DMA controller.
Direct Memory Access Controller (DMAC) options for data transfer
The DMA Controller has several options available for the transfer of data. They are:
1) Cycle Steal:
• A read or write signal is generated by the DMAC, and the I/O device either generates or latches the data. The
DMAC effectively steals cycles from the processor in order to transfer the byte, so single byte transfer is also known as
cycle stealing.
2) Burst Transfer:
• To achieve block transfers, some DMAC's incorporate an automatic sequencing of the value presented on the
address bus. A register is used as a byte count, being decremented for each byte transfer, and upon the byte count reaching
zero, the DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the
data transfer.
3) Hidden DMA:
• It is possible to perform hidden DMA, which is transparent to the normal operation of the CPU. In other words, the
bus is grabbed by the DMAC when the processor is not using it. The DMAC monitors the execution of the processor, and
when it recognises the processor executing an instruction which has sufficient empty clock cycles to perform a byte transfer;
it waits till the processor is decoding the op code, then grabs the bus during this time.

ADC and DAC Interfacing:

The Analog to Digital Conversion is a quantizing process. Here the analog signal is represented by equivalent binary states.
The A/D converters can be classified into two groups based on their conversion techniques.
In the first technique it compares given analog signal with the initially generated equivalent signal. In this technique, it
includes successive approximation, counter and flash type converters. In another technique it determines the changing of
analog signals into time or frequency. This process includes integrator-converters and voltage-to- frequency converters.
The first process is faster but less accurate, the second one is more accurate. As the first process uses flash type, so it is
expensive and difficult to design for high accuracy.
ADC 0808/0809 Chip
The ADC 0808/0809 is an 8-bit analog to digital converter. It has 8 channel multiplexer to interface with the microprocessor.
This chip is popular and widely used ADC. ADC 0808/0809 is a monolithic CMOS device. This device uses successive
approximation technique to convert analog signal to digital form. One of the main advantage of this chip is that it does not
require any external zero and full scale adjustment, only +5V DC supply is sufficient.
Let us see some good features of ADC 0808/0809:
• The conversion speed is much higher
• The accuracy is also high
• It has minimal temperature dependence
• Excellent long term accuracy and repeatability
• Less power consumption
 Computer Organization (PC402CS) 16

Architecture of ADC
Interfacing ADC with 8085 Microprocessor
To interface the ADC with 8085, we need 8255 Programmable Peripheral Interface chip with it. Let us see the circuit
diagram of connecting 8085, 8255 and the ADC converter.

Interfacing ADC with 8085 Microprocessor

The PortA of 8255 chip is used as the input port. The PC7 pin of Port Cupper is connected to the End of Conversion (EOC)
Pin of the analog to digital converter. This port is also used as input port. The Clower port is used as output port. The PC2-
0 lines are connected to three address pins of this chip to select input channels. The PC3 pin is connected to the Start of
Conversion (SOC) pin and ALE pin of ADC 0808/0809.
Now let us see a program to generate digital signal from analog data. We are using IN0 as input pin, so the pin selection
value will be 00H

MVI A, 98H ; Set Port A and Cupper as input, CLower as output OUT 03H ; Write control word 8255-I to control
Wordregister XRA A ; Clear the accumulator
OUT 02H ; Send the content of Acc to Port Clower to select IN0
MVI A, 08H ; Load the accumulator with 08H OUT 02H ; ALE and SOC will be 0
XRA A ; Clear the accumulator
 Computer Organization (PC402CS) 17

OUT 02H ; ALE and SOC will be low. READ: IN 02H ; Read from EOC (PC7)
RAL ; Rotate left to check C7 is 1.
JNC READ ; If C7 is not 1, go to READ IN 00H ; Read digital output of ADC STA 8000H ; Save result at 8000H
HLT ; Stop the program
DAC Interfacing with 8085 Microprocessor
• DAC 0800 Features
• To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be employed.
• The DAC will accept a digital (binary) input and convert to analog voltage or current.
• Every DAC will have "n" input lines and an analog output.
• The DAC require a reference analog voltage (Vref) or current (Iref) source.
• The smallest possible analog value that can be represented by the n-bit binary code is called resolution.
• The resolution of DAC with n-bit binary input is 1/2nof reference analog value.
• The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time (conversion time) of 100 ns.
• It produces complementary current output, which can be converted to voltage by using simple resistor load.
• The DAC0800 require a positive and a negative supply voltage in the range of ± 5V to ±18V.

Circuit diagram of DAC 0800

• It can be directly interfaced with TTL, CMOS, PMOS and other logic families.
• For TTL input, the threshold pin should be tied to ground (VLC = 0V).
• The reference voltage and the digital input will decide the analog output current, which can be converted to a voltage by
simply connecting a resistor to output terminal or by using an op-amp I to V converter.
• The DAC0800 is available as a 16-pin IC in DIP.