IEEE

SOLID STATE
WINTER 2009
VOL. 1 • NO. 1
www.ieee.org/sscs-news

MAGAZINE

features
8 The Making of the First Microprocessor
The Intel 4004 CPU-on-a-chip was developed under
pressure on an extremely tight schedule—and it worked.
By Federico Faggin
22 Designing the First Microprocessor
How rethinking a customer’s specifications led to
IEEE
simplifications that made the first microprocessor possible.
By Marcian E. Hoff
29
SOLID STATE
Moore’s Law, Microcomputers, and Me
A confluence of skills made the microcomputer
revolution possible: device design, process design,
applications, and marketing.
By Stanley Mazor about this image:
39 The 4004 CPU of My Youth MAGAZINE
A portion of the 4004 chip layout.
See page 8 for more details.
Developing the world’s first microprocessor.
By Masatoshi Shima
46 United States Patent 3,821,715
By Hoff, Jr. et al.
55The MCS-4—An LSI Micro
Computer System columns/
By F. Faggin, M. Shima, M.E. Hoff, Jr., H. Feeney, and S. Mazor departments
61 Impact of LSI on Future Minicomputers 3 Contributors
By Marcian E. Hoff, Jr. 4 Editor’s Note
63 Intel MCS-4 Micro Computer Set 5 President’s Corner
By Intel 6 Associate Editor’s
69 From Mechanism to Monolith View
The path to the microprocessor. 7 From the Executive
By Thomas H. Lee Director
90 People
76Microprocessors of the Future:
97 Conference Reports
Commodity or Engine of Growth?
To avoid relegation to commodity status, new 100 Chapters
approaches to improvement must be found. 105 Society News
By Sam Naffziger 108 IEEE News
83 The Dawn of Terascale Computing CVR3 Footer
Applications may be the edge of science fiction, but
they are starting to happen, although the challenges
are formidable.
By Justin Rattner

Digital Object Identifier 10.1109/MSSC.2008.930933

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 1

 Administrator, Katherine Olstein Terms to 31 Dec. 2011
IEEE solid-state IEEE SSCS, 445 Hoes Lane Ali Hajimiri, Paul J. Hurst,
circuits magazine Piscataway, NJ 08854 USA Domine Leenaerts, Kenneth O, Ian Young
Tel: +1 732 981 3410
Editor-in-Chief Fax: +1 732 981 3401 Region 8 Representative
Mary Y. Lanzerotti Jan Sevenhans
IBM T. J. Watson Research Center Region 10 Representatives
[email protected], Fax: +1 914 945 1358 SSC Administrative committee C.K. Wang, Tohru Furuyama
President, Willy Sansen
Technology Editor K. U. Leuven, Belgium Chairs of Standing Committees
Richard C. Jaeger [email protected]
Alabama Microelectronics Center Awards—John J. Corcoran
Fax: +32 16 321975 Chapters—Jan Van der Spiegel
Auburn University, Alabama, USA
[email protected] Vice-President, Bernhard Boser Education—C.K. Ken Yang
University of California, Berkeley, USA Meetings—Bill Bidermann
Secretary, David A. Johns Nominations—Richard C. Jaeger
Tutorials Editor
University of Toronto, Ontario, Canada Publications—Glenn Gulak
Rakesh Kumar
Technology Connexions Treasurer, Rakesh Kumar For contact information, see the
Poway, CA, [email protected] Technology Connexions, Poway, “Contact Us” page on SSCS Web site:
California, USA http://ewh.ieee.org/soc/sscs/index.php?
Associate Editor for option=com_content&task=view&id=
Past President, Richard C. Jaeger
Europe/Africa 10&Itemid=3
Alabama Microelectronics Center,
Tony Harker
Auburn University, Alabama, USA
Alba Centre Alba Campus
Livingston EH54 7EG Scotland
[email protected]
Other Representatives IEEE Periodicals/
Representative to Sensors Council Magazines Department
Associate Editor for
the far east Darrin Young Senior Managing Editor
Pengfei Zhang Representative to CAS from SSCS Geraldine Krolin-Taylor
Beken Corporation Tony Chan Carusone senior Art Director
Shanghai, China Representative to SSCS from CAS Janet Dudar
[email protected] Michael Flynn Assistant Art Director
Gail A. Schnitzer
News Editor Representatives to EDA Council
Katherine Olstein Bryan Ackland, Jan Rabaey production coordinator
Theresa L. Smith
IEEE SSCS Representatives to ISSCC
[email protected] Staff Director, Publishing Operations
Bryan Ackland, Jan Van der Spiegel Fran Zappulla
Editorial Director
Dawn M. Melley
IEEE solid-state Elected AdCom Members at Large Production Director
circuits society Terms to 31 Dec. 2009 Peter M. Tuohy
Executive Director, Anne O’Neill John J. Corcoran, Kevin Kornegay, Advertising Production Manager
IEEE SSCS-West Hae-Seung (Harry) Lee, Thomas H. Lee, Felicia Spagnoli
1500 SW 11th Avenue #1801 Jan Van der Spiegel Business Development Manager
Portland, OR 97201 USA Terms to 31 Dec. 2010 Susan Schneiderman
Tel: +1 732 981 3400 Terri S. Fiez, Tadahiro Kuroda, +1 732 562 3946 Fax: +1 732 981 1855
Fax: +1 732 981 3401 Bram Nauta, Jan Sevenhans, [email protected]
E-Mail: [email protected] Mehmet Soyuer www.ieee.org/ieeemedia

SCOPE: Each issue of IEEE Solid-State Circuits Magazine is envisioned as a self-contained

resource for fundamental theories and practical advances within the field of integrated
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IEEE Solid-State Circuits Magazine (ISSN 1943-0582) is published quarterly by The Insti-
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about the cover:

The 4004 microprocessor and four of the individuals
important in its creation.
© photo F/X2

2 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 contributors

Feature Authors

Federico Faggin is Marcian E. “Ted” Hoff Stanley Mazor re-

president, chief ex- is named as inven- cently published
ecutive officer, and tor or coinventor Design an Expand-
a director of Foveon on 17 U.S. patents. able House as well
Inc. He is one of the He is one of the cre- as Stock Market
creators of the 4004 ators of the 4004 Gambling. He is
microprocessor. microprocessor. one of the creators of the 4004
microprocessor.
Masatoshi Shima is
a former professor
at Aizu University Columnists
in Japan. He is one
of the creators of EIC Mary Lanzerotti SSCS President Will
the 4004 micro- has been involved Sansen is with the
processor. with the IEEE Solid- Katholieke Univer-
State Circuits So­ siteit Leuven. He
Thomas H. Lee has ciety since 2005 has published more
been a professor and serves as this than 580 papers in
of electrical engi- magazine’s first editor-in-chief. international journals and confer-
neering at Stanford ence proceedings. He is a Fellow of
University since Anne O’Neill keeps the IEEE.
1994. the Society on
track as its execu- Associate Editor
Sam Naffziger is tive director. She Peng-fei Zhang was
with the Mile High has held that posi- a postdoctoral sci-
Design Center of Ad- tion for 12 years. entist in the Electri-
vanced Micro Devic- cal Engineering De-
es in Fort Collins. DR. Kandala Chari partment of UCLA
is a senior direc- from 1994 to 1996 and cofounded
tor in the Minis- Beken Corporation in Shanghai in
Justin Rattner was try of Information 2005.
named scientist of Technology, Gov-
the year by R&D ernment of India,
Magazine in 1989 New Delhi, associated with mi-
for his leadership croelectronics R&D activities for
in parallel and dis- over three decades, and a Senior
tributed computer architecture. Member of the IEEE with service
on many IEEE global committees.

Digital Object Identifier 10.1109/MSSC.2009.931848

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 3

 editor’s note

Welcome to Our First Issue of

IEEE Solid-State Circuits Magazine!

W
With this Winter 2009 issue, the SSCS
Newsletter transforms into IEEE Solid-
State Circuits Magazine, thanks to the
initiative of ­E xecutive Director Anne
O’Neill, IEEE Solid-State Circuits Soci-
time to work with us on each issue
to arrive at a design that comple-
mented the technical content. We
hope that you will send a thank you
message to Paul at his e-mail ad-
■■ “The MCS-4—An LSI Micro Compu­
ter System,” a paper, by F. Faggin,
M. Shima, M.E. Hoff, H. Feeney, and
S. Mazor (1972)
■■ “Impact of LSI on Future Minicom-

ety (SSCS) Past President Dick Jaeger, dress: [email protected]. puters,” by M.E. Hoff (1970)
and SSCS Treasurer Rakesh Kumar. ■■ U.S. Patent 3,821,715, by Messrs.

The transition process during the This Issue Faggin, Hoff, and Mazor (1971).
past months involved presentations As the successor of SSCS News, each We also offer two new essays on
to the SSCS AdCom and IEEE TAB by issue of this magazine aims to be microprocessors by experts at AMD
Prof. Jaeger and Dr. Kumar a self-contained re- and Intel, under the auspices of our
and required the approval source, with origi- Technology Editor Prof. Jaeger and our
of both groups. The de- nal sources and new Tutorials Editor Dr. Kumar, respective-
sign of the magazine was As the successor contributions by ex- ly, as well as a third piece by Stanford
executed by the IEEE of SSCS News, perts describing the Professor Thomas Lee:
Magazines Department, each issue of this current state of affairs ■■ “Microprocessors of the Future:

whose goal was to magazine aims in technology in view Commodity or Engine of Growth?”
bring it into line with to be a self- of the influence of the by Sam Naffziger, AMD
other IEEE magazine contained resource. original papers and/or ■■ “The Dawn of Terascale Comput-

offerings. patents. ing,” by Justin Rattner, Intel

In this issue, we feature ■■ “From Mechanism to Monolith,” by

Thank You Paul Doto! the work of Federico Faggin, Marcian Tom Lee, Stanford University.
We want take the opportunity to E. Hoff, Stanley Mazor, and Masa- We would like to thank George
thank IEEE Publications Newslet- toshi Shima, who invented the 4004 Alfs of Intel Public Relations (george.
ter Coordinator Paul Doto for his ­microprocessor. We are delighted to [email protected]) for allowing us to
fabulous designs for the SSCS News, have the opportunity to present orig- reprint the following:
especially the full-color covers and inal articles by each of them: ■■ the Intel data sheet (1971) for

interior designs that differentiated ■■ “The Making of the First Micropro- these microprocessors
technical content, careers, confer- cessor,” by Federico Faggin ■■ a photo of Intel staff (circa early

ences and news. It has been a plea- ■■ “Designing the First Microproces- 1970s)
sure to work with Paul, who rou- sor,” by Marcian E. Hoff ■■ a photo of Faggin, Hoff, and ­Mazor

tinely went above and beyond his ■■ “Moore’s Law, Microcomputers, (1996) celebrating the 25th anni-
responsibilities in preparing our and Me,” by Stanley Mazor versary of the 4004.
magazine-length newsletter and ■■ “The 4004 CPU of My Youth,” by Thank you for reading IEEE Solid-
designing the covers that focused Masatoshi Shima. State Circuits Magazine. Please send
on our feature authors and their In addition, we reprint two clas- comments and feedback to me at
contributions. Paul always took the sic articles by these four inventors [email protected].
along with a ground-breaking 1971 —Mary Y. Lanzerotti
Digital Object Identifier 10.1109/MSSC.2008.930940 patent by Faggin, Hoff, and Mazor:

4 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 president’s corn er

Volume 1, Number 1!

V
“Volume 1, number 1” sounds full of
ambition! It shows that the IEEE Solid-
State Circuits Society has commit-
ted to something new, a new mis-
sion. It shows that the Society is
ket value of professionals to both
companies and universities.
The magazine will provide
first-hand information on where
­solid-state circuits are heading, not
precision? Have we really reached
the point that a chip makes a differ-
ence in a biomedical product? These
are just a sample of the questions
we have to be able to answer if we
committed to a new ­journal —one through specialized monographs but want to make a difference, as soon
that aims for at least the same with tutorials and overview papers. as the economy veers up.
quality as the IEEE Journal of Solid The magazine will provide full cover-
­State-Circuits. Why? age of courses within Answer the Call
This is a time of econom- your country, across Given the Society’s mission to pro-
ic uncertainty The value The magazine will your continent, and vide better means for networking and
of stock is ­uncertain. provide first-hand all over the world. The education to really impact the life of
The value of a house information on magazine will provide a solid-state engineer, this is a call
is uncertain. Are you where s­ olid-state details on the tours and for more volunteers on all fronts!
afraid of getting fired? circuits are heading. presentations of SSCS IEEE Solid-State Circuits Maga-
What is the value of and IEEE Distinguished zine can only provide the same
knowledge? Lecturers. It will explain quality as the IEEE Journal of Solid-
The first conse- why we must still attend State Circuits if more people are
quence of uncertain times is that the ISSCC and the VLSI Circuits Sym- committed. Editor-in-Chief Mary
travel is cut. The second is that posium and other conferences. We Lanzerotti has taken the first bur-
courses are cut. Is this justified? still want to know how many 32-nm den and is to be complimented for
Travel is a negligible cost to a CMOS papers will be presented at the it. However, a larger crew is needed.
company; however, it is of high psy- next ISSCC and how many 100-GHz Past-President Dick Jaeger will head
chological value. There is no better circuits, and how few femtoJoules/ the Magazine Advisory committee.
way to demonstrate to an engineer conversions, the ADCs have reached More volunteers are needed.
that times are bad than to cut trav- today. Moreover, we want to know The Society is also discussing
el, as if it is a leisure product like about the four satellite ISSCC con- the future format of conferences
after-shave each morning! Educa- ferences that will bring ISSCC in- and of journals, such as the ISSCC
tion also can be dispensed with, as formation to the Far East in 2009, and the IEEE Journal of Solid-State
if ­k nowledge only serves production barely two weeks after the San Circuits. Should they go more vir-
and has no other purpose. Francisco conference! tual? Will this evolution change the
We have to broaden our scope as format? These plans are all under
Investing in Education well. The programs of the Distin- discussion in our AdCom meetings,
Our new magazine will show the guished Lecturers will be multiplied held in February and in August.
opposite. Its goal is to assist the and better supported. How far have More volunteers for the AdCom are
solid-state engineer in building solid-state circuits invaded the sen- looked for as well.
up knowledge to help him or her sor world, the automotive applica- This is a time for all SSCS Mem-
through difficult times like these, tions? Do we have to be more aware bers to react and to play a role.
when education is probably the best of solid-state technologies to do
investment for enhancing the mar- better solid-state circuit design? Do —Willy Sansen
we have to understand how FinFETs SSCS President
Digital Object Identifier 10.1109/MSSC.2008.930939 work? Is variability a threat to high

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 5

 a ssoc iate editor’s vie w

Going to Wall Street or Across the Strait?

I
If the CEOs of the China IC design
houses were asked three years ago
about their company’s exit strategy,
to be listed on NASDAQ through a
glamorous IPO would no doubt ­occur
200%

150%

to them as the ultimate success. 100%

And so it came to be. Zhonghan
Deng, the founder and CEO of ­Vimicro 50%
International Corporation, a Beijing-
0%
based fabless design company, rang
the NASDAQ stock market closing Vimicro Int’l Corp ADR
Actions Semiconductor Co. Ltd. ADR –50%
bell on 17 November 2005. Within
Spreadtrum Communications Inc. ADR
days, Actions Semiconductor, another
China IC design company located in 2004 2005 2006 2007 2008
Zhuhai, announced its initial public
offering on 30 November and started Figure 1: Stocks performance of three Chinese IC design houses since their IPO relative to
trading on NASDAQ. Spreadtrum, a NASDAQ composite index.
company that designs the chip sets
for TD-SCDMA, China’s home-grown significantly more mature competi- electronics, Inc., Chipsbank Micro-
3G mobile standard and widely con- tors, fare poorly in the eyes of Wall electronics Co., Ltd., and Hangzhou
sidered one of the flagship companies Street. Both Vimicro and Actions, and National Chip Science & Technology
in China IC design business, went Spreadtrum, have seen their stocks Co., Ltd. are all in the pipeline for IPOs
public on NASDAQ in 2007. plunge on NASDAQ. It is hard for U.S. on China’s domestic stock market.”
No sooner had their stocks started investors to see the unique merit that This strategy may sound espe-
trading than these companies came these China IC design companies pos- cially wise today, as China’s exports
to realize that U.S. investors were not sess.” Vincent Gu, an analyst from have accelerated and retail sales
quite so excited about the China IC Isuppli, said, “Observing these com- continue to boom. Overall, China’s
design business. Concerns over intel- panies being beaten up so badly on economy is cooling down, although
lectual property and core competen- Wall Street, many Chinese IC design it’s still growing vigorously consider-
cies plagued their stock performance. companies start to consider seriously ing the economic malaise in much of
In time it became progressively clear about going public on the domestic
that it is difficult to get a decent re- stock market. In fact, Huaya Micro- (continued on page 99)
turn for their investors. Even the rep-
utation and brand name established Table 1. China ic design houses planning to go public on domestic
stock market.
and reinforced in connection with
their IPOs did not help expand busi- Year
Company Headquarters Products
Founded
ness as much as expected.
According to Shoulei Jiang, the Huaya Microelectronics Inc. 2001 Shanghai Video production IC
secretary-general of the Shanghai IC Chipsbank Microelectronics Co., 2003 Shenzhen Memory card controller
Industry Association (SIA), “China Ltd.
IC design companies, shadowed by Hangzhou National Chip Science 2001 Hangzhou Digital TV demodulator,
& Technology Co., Ltd. decoder and video
processing IC
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6 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

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■■ Special sessions will be presented ■■ Two industrial sessions will pres-
on green devices and on next gen- ent up-to date research results:
eration lithography. building the next-generation high-
■■ There will be invited talks on performance CPU and breaking
FEOL, memory, BEOL, and CMOS. through the chip-to-chip intercon-
■■ Two parallel in-depth short cours- nect wall.
es on SIP & 3D IC and nonvolatile ■■ There will be four half-day in-

memory will be presented. depth tutorials.

■■ There are approximately 50 con- Keynote speakers at VLSI-TSA 2009 will ■■ There are approximately 70 contrib-

tributed ­papers. be Dr. Mark Pinto, chief technology officer, uted papers.
senior vice president and general manager
For more details about the con-
of the energy and environmental solutions
VLSI-DAT Industry Sessions on division of Applied Materials, USA (left) and ference agenda, please visit our con-
High Performance CPUs and Prof. Ken Uchida of the Tokyo Institute of ference Web sites at vlsitsa.itri.org.
Chip-to-Chip Interconnection Technology, Japan. tw (for VLSI-TSA) or vlsidat.itri.org.
Under the leadership of Confer- tw (for VLSI-DAT).
ence Cochairs General Director VLSI-DAT will cover all aspects of For registration, please register
Cheng-Wen Wu and Prof. Tzi-Dar VLSI design, automation, and test. at vlsitsa.itri.org.tw (for VLSI-TSA)
Chiueh, Technical Program Chair Pertinent facts include the following: or vlsidat.itri.org.tw (for VLSI-DAT)
Prof. Kuen-Jong Lee, and Cochair ■■ Keynote addresses will be given by upon your preference. Should you
Prof. Tim Cheng, 2009 VLSI-DAT Dr. Fang-Churng Tseng, vice chair have any further questions about
will feature an exciting program of Taiwan Semiconductor Manufac­ registration, please contact the con-
with special sessions on electron- turing Co., Ltd. and Prof. Jan Ra- ference registrar, Ms. Yvonne Chen
ic system level design, high-fre- baey, director of Gigascale Systems at +886-3-5913003 or e-mail HRD@
quency/very low power RF/analog Research Center at the University of itri.org.tw for assistance.
circuits and silicon debugging/ California, Berkeley.
design validation. Industry ses- ■■ There will be three special ses- —Clara Wu and Elodie Ho
sions include “Building the next- sions: high-frequency/very-low Symposia Secretariat
­­Generation High-Performance CPU” voltage RF/analog circuits, silicon [email protected]
and “Breaking Through the Chip-to- debugging/design validation, and [email protected]
Chip Interconnect Wall.” electronic system level.

Associate Editor’s View (continued from page 6)

the world. But China’s stock market of the Taiwan electronics industry. we—at the moment—we still have re-
often moves to its own beat, without However, Taiwan regulates finan- strictions on our people purchasing
regard for broader economic condi- cial activities by setting limits that overseas mutual funds. If the fund has
tions, reflecting the fact that it is still make it impossible for a mainland more than 0.4% invested in the main-
relatively immature. enterprise to go public in Taiwan. land, then it is not supposed to be sold
According to Ping Ko, the presi- However, Eric Chu, vice president in Taiwan. That [has] actually forced
dent and CEO of Silicon Federation of WK Technology Fund, one of the billions, hundreds of billions, out of
International, Inc., a Shanghai-based largest venture capital firms in Tai- Taiwan. We hope to call them back. If
venture capital firm specializing in wan said, “Things are changing and I we change the current rules, I’m sure
the China IC industry, “All factors con- won’t be surprised if a Camen or a BVI many of them [investors] would like
sidered, including investors’ interests company with most operations on the to do the transaction right in Taiwan.
and maturity, stock market regula- mainland can go public in Taiwan in That is why we think if we are able to
tion and management, listing and the foreseeable future.” do that, we may become the assets
maintenance costs, the Taiwan stock Eric could very well be right, if the management center of Asia.”
market is no doubt the best place for newly elected leader of Taiwan, Ma Ambitious as this is, let’s remain
China IC design houses to go public.” Ying-jeou, can actually achieve what hopeful that another exit option
Indeed, most Taiwanese IC compa- he promised during his campaign. In could eventually be made available
nies went public on the Taiwan Stock interviews published by The New York to China IC design companies.
Market, and investors there embraced Times and The International Herald Tri-
these companies, large or small, with bune on 18 June 2008, Mr. Ma said, “We —Pengfei Zhang
great enthusiasm. As a result, the certainly will deregulate our financial Beken Corporation, Shanghai
Taiwan domestic stock market has services industry, and to attract back [email protected]
been a cornerstone of the prosperity the capital that flew out, you know,

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 99

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 from th e executive director

Becoming a Part of IEEE Xplore

T
This launch issue of IEEE Solid-State
Circuits Magazine marks a new fo-
cus on more accessible information
about ICs for our members. Since
the fall of 2006, our (then new news-
Did You See It Online?
As we go to press, some important news is still breaking. Keep on top of all SSCS news by
checking our Web site: www.ieee.org/sscs.
We posted the following news bites on our Web site in January and sent members an early
letter) coeditor, Mary Lanzerotti, be- January e-mail alert:
gan acquiring some great articles •• AdCom elected: Find out the leaders of the Society Administrative Committee elected

from authors who wrote about the last fall who take office January 2009.
development of integrated circuits •• New IEEE Fellows: 16 SSCS members are elevated to IEEE Fellow grade. The six recog-

technology. Recognizing this, the nized at ISSCC are Shekhar Borkar, Joe Jensen, Shoji Kawahito, Rudolph Koch, Un-Ku Moo,
IEEE Solid-State Circuits Society and Robert Staszewski.
(SSCS) leadership from the Publica- Check out more news mid February
tions Committee and AdCom want- •• ISSCC Highlights: A number of Asian countries are setting aside a day or two for select

ed to see the material available in highlights of the February 2009 ISSCC. The day’s agenda will include original presenta-
IEEE Xplore. That way when mem- tion slides and the recorded voice of the original presenter. Some locations will have local
bers of the IC community search experts to lead discussions and answer questions. Find out online where and when these
in IEEE Xplore, they could come ISSCC highlight events are scheduled.
across this information. In a few
years when a student or historian
wanted to look at them, they’d be ­ ordon Bell. We’ve carried more than
G pate that by early 2009 posting of this
archived in IEEE Xplore, the online 60 articles on CMOS trends, scaling, low work will be complete and ready for
database with 1.3 million other ar- power circuits and timing applications, your use.
ticles on electro technology. the incredible shrinking integrated —Anne O’Neill
We anticipate that the IEEE Xplore circuit, DRAMS, analog ICs, and reach- [email protected]
staff will have this issue up about ing students about circuits. We antici-
the same time you receive it in your
postal box. Once the magazine’s
Xplore home page is operational
you’ll be able to request an RSS feed
In 1996, The National Inven-
to your desktop to see the table of
tors Hall of Fame honored
contents as soon as it is posted.
Ted Hoff, Federico Faggin,
The issues of News articles since Sep-
and Stan Mazor (left to right)
tember 2006, when Mary joined the SSCS
during the microprocessor’s
newsletter as coeditor, is on a schedule to
silver anniversary year. Ted
be posted in IEEE Xplore. Starting with
Hoff, Stan Mazor, and Fed-
the first fall 2006 article by Gordon
erico Faggin were inducted
Moore, the SSCS News featured these
into the National Inventors
other industry giants: Brian Kernigahn,
Hall of Fame for their roles in
Robert Dennard, Robert Noyce and Jack
developing the microproces-
Kilby, Gene Amdahl, Barrie Gilbert, Ki-
sor at Intel 25 years earlier.
yoo Itoh, Mitsumasa Koyanagi, Hideo
(Photo courtesy of Intel.)
Sunami, Randy Isaac, Dick Foss, and

Digital Object Identifier 10.1109/MSSC.2008.930941

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 7

by Federico Faggin

The Intel 4004 CPU-on-a-chip was developed under

pressure on an extremely tight schedule—and it worked.

A
lthough I didn’t know
it at the time, my
early work experience
turned out to be abso-
lutely invaluable, set-
ting the stage for my future career. Born,
raised, and educated in northern Italy, I
graduated in radio technology from the
A. Rossi Technical Institute in Vicenza
in 1960. My first job was assistant en-
gineer at the Olivetti Electronic R&D
Laboratory near Milan, where Olivetti
was developing its early electronic com-
puters. By a series of fortunate coinci-
dences, in 1961 I ended up codesigning
and building a small experimental elec-
tronic computer with 4K words of mag-
netic core memory. I was only 19 years
old, and I had four technicians working
for me, helping with the construction
of that computer. The computer used
approximately 1,000 logic gates, made
with germanium transistors (fabricated
in Italy by SGS-Fairchild), housed in a
couple of hundred small printed circuit
boards. Silicon transistors would have
been faster, but they were too expen-
sive, and integrated circuits (ICs) had

Digital Object Identifier 10.1109/MSSC.2008.930938

8 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/09/$25©2009IEEE

just been invented and were not yet ruary 1968, SGS sent me to the R&D oxide semiconductor) technology,
commercially available. Laboratory of Fairchild Semiconduc- considered by some, including my-
At the end of that project I de- tor in Palo Alto, California, as part of self, to be the future of ICs. The
cided to go back to school and study an engineer exchange program be- working principles of MOS transis-
physics at Padua University, where I tween the two companies. I was sup- tors were quite different from those
received a doctorate in physics, sum- posed to stay in the United States for of bipolar transistors, relying on
ma cum laude, with an experimental six months and then return to Italy. I surface phenomena at the interface
thesis in flying-spot scanners. In never went back except as a visitor! between silicon and silicon dioxide
1967 I joined SGS-Fairchild in Agrate rather than the bulk semiconductor
Brianza, where I became MOS group The Early Years properties exploited in the bipolar
leader, developed SGS’s first manu- In 1968, the vast majority of inte- devices. This fundamental differ-
facturing process for high-thresh- grated circuits sold in the world used ence made MOS integrated circuits
old-voltage MOS ICs, and designed bipolar technology. They were all physically smaller and simpler to
the company’s first two MOS inte- made with the revolutionary planar fabricate than bipolar ICs, although
grated circuits. SGS-Fairchild was process, pioneered by Fairchild in their operating speed was far slower
then the only Italian semiconductor the late 1950s to batch-fabricate sili- than bipolar.
company, 30% owned by Fairchild con transistors. Competing with bi- For the same cost and the same
Semiconductor, and a licensee of polar technology was another emer- power dissipation, MOS technology
Fairchild bipolar technology. In Feb- gent technology, called MOS (metal promised digital ICs with about ten
times more logic gates than bipolar
technology, although operating at a
much slower speed. MOS technology
was still controversial, however, with
many people still skeptical about
its viability, given its major speed
limitations and its poor reliability
record. Nonetheless, a few start-up
companies had already sprouted in
Silicon Valley to take advantage of
MOS technology to make either se-
rial memory, using dynamic shift
registers, or to make emergent ap-
plications where high complexity at
modest speed would be adequate—
for example, desktop calculators,
which at that point were still built
with electromechanical technology.
In 1968, the only MOS technology
in production was high-threshold-
voltage p-channel MOS, and R&D
work was being carried out around
the world to develop a low–threshold-
voltage technology that could more
easily be made TTL compatible.
(TTL, or transistor-transistor logic,
had become the standard logic fam-
ily of the industry and required 5-V
operation. Standard MOS required
24 V, and low-threshold MOS was ex-
pected to use a supply voltage of 12
© photo f/X2 & imagestate

to 17 V.)

The Holy Grail

The holy grail of MOS technology
was already recognized by many
MOS experts. It was called MOS

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 9

self-aligned gate, and it promised large speed variations from wafer was required to have a technology
to greatly improve the speed of MOS to wafer. suitable for mass production of sili-
ICs by eliminating a major ­parasitic The cure for this problem was to con gate ICs.
effect plaguing the technology: form the gate first, rather than last, During the first few weeks on the
overlap capacitance. In conventional and use the gate to define both the project, I invented the process ar-
MOS transistors, the source and source and drain regions, thus cre- chitecture, followed by the design
drain regions of the transistor were ating perfect alignment every time. of the detailed process flow, suc-
made first, and formation of the Unfortunately, the aluminum used ceeding in fabricating self-aligned
thin-oxide gate region followed. for the gate electrode was not suit- gate p-channel, low-threshold volt-
The gate region overlapped the able for such a purpose because it age MOS devices a few months later.
source and drain junctions by an could not withstand the high tem- These low-threshold-voltage devices
amount sufficient to compensate perature required to create the were built with amorphous silicon
for the misalignment introduced by source and drain junctions; a dif- gates, using <111> silicon wafers, in-
the lithographic equipment and still ferent, more refractory material, stead of the <100> silicon required
guarantee a minimum overlap under was required. for low-threshold-voltage transis-
worst-case conditions. tors with metal gates. The transis-
This requirement meant that Silicon Gate Technology tors achieved low threshold voltage
much more overlap was necessary My first assignment at Fairchild was by taking advantage of the reduced
than the minimum required for the to develop a low-threshold-voltage, work function (by about 1.1 V)
proper operation of the transistor. A self-aligned gate MOS technology between a properly doped silicon
particularly adverse effect occurred using a gate electrode made of amor- gate and the silicon substrate—an
when the gate misalignment was in phous silicon, following the work of observation made by Tom Klein at
the direction to increase the over- J.C. Sarace and collaborators who, at Fairchild. In the following months I
lap with the drain junction. In this Bell Labs, had succeeded in building also designed an integrated circuit
case the overlap capacitance, multi- self-aligned gate MOS transistors us- to prove that the new process tech-
plied by the gain of the stage (due to ing amorphous silicon. The struc- nology was indeed manufacturable.
the so-called Miller effect), would tures built by Sarace, however, were This chip became the world’s first
appear as an additional gate capaci- adequate only to prove the working commercial IC to use self-aligned
tance. This substantial increase in principle; they were not suitable for gates. It was an 8-b analog multi-
gate capacitance not only reduced fabrication of integrated circuits. plexer with decoding logic, called
the circuit speed but also induced Much more work and innovation the Fairchild 3708 (Figure 1), replac-
ing the Fairchild 3705, a function-
ally equivalent chip built with metal
gates and difficult to consistently
manufacture within specifications.
During the development of the
3708, it became apparent that vac-
uum-deposited amorphous silicon
was unreliable, tending to break or
crack at oxide steps. Soon Tom Klein
and I found a way to replace it with
polycrystalline silicon produced
by vapor deposition. By the end of
1968, the 3708 could be reliably
manufactured and became commer-
cially available. Compared with the
Fairchild 3705, the 3708 was about
four times faster, the on resistance
of its large multiplexing transistors
was two and one-half times smaller,
and the junction leakage was at least
ten times smaller.
With silicon gate came also the
ability to do phosphorus gettering
Figure 1: The Fairchild 3708, the world’s first commercial self-aligned gate MOS IC, (a method to reduce metal contami-
employing silicon gate technology and available in the market at the end of 1968. nants) after the completion of the

10 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

MOS structure, leading to a major to make with metal gate technol- of the incumbent technology—for
improvement in both junction leak- ogy, but impossible with silicon gate the same power dissipation and
age and device reliability compared technology without the use of an ad- two-phase clock design (then called
to metal gate, and opening up the ditional masking step, which would quasi-static design).
path to the fabrication of dynamic add significant cost to the process. Silicon gate technology with bur-
random-access memories (DRAMs). In those days the p-channel MOS ied contacts and bootstrap loads
This method was also first imple- process required just five mask- became one of the essential ingre-
mented in 1968 at Fairchild by the ing steps, compared with the 20–40 dients required to make the mi-
author. The unique ability to encase masking steps of contemporary ICs. croprocessor feasible in 1970. The
the silicon gate in thermal oxide—
one of the best electrical insulators
known—allowed also the creation
of the first commercial nonvolatile There are two other inventions I made while
memories (by Dov Frohman at Intel at Fairchild that proved essential to the
in 1971) and the first commercial
image sensors made with charge-
microprocessor realization: the buried contact
coupled devices (at Fairchild in and the bootstrap load.
1973). Metal gate was unsuitable for
such applications.
This limitation was considered only other viable method to make
Essential Inventions very serious by the Fairchild chip complex random-logic circuits with
There are two other inventions I designers and was delaying the high-threshold-voltage metal gate
made while at Fairchild that proved adoption of silicon gate technology technology was to use fully dynamic
essential to the microprocessor re- by the MOS division—a source of circuits with four-phase clocks. This
alization: the buried contact and major frustration for me. For some was a relatively complex technique,
the bootstrap load. The buried time I also believed that this limita- requiring computer-assisted design,
contact was a method to make a tion was insurmountable as I strug- successfully used by Rockwell Semi-
direct contact between polysilicon gled to find a solution. Eventually conductor and Four-Phase Systems
and junctions that did not involve I realized that, under the normal to produce calculator and computer
the use of aluminum—therefore it operating conditions of a bootstrap chips. Silicon gate technology, how-
was buried under a layer of silicon load, there would always be a vir- ever, using simpler, quasi-static
dioxide—and required only an ad- tual junction under the polysilicon two-phase design, was superior in
ditional masking step. This innova- that could be used for one of the both speed and circuit density to
tion made possible smaller contacts, two electrodes of the capacitor, thus the best four-phase designs. Low-
but more important, it provided two eliminating the need for a real junc- threshold-voltage metal gate MOS
layers of interconnections, one with tion and an extra masking step. The technology was eventually devel-
polysilicon and one with aluminum, virtual junction was created by the oped with the help of ion implanta-
significantly increasing the circuit inversion layer induced by the spe- tion in 1970–1971, allowing metal
density, particularly for random- cific biasing conditions of the boot- gate MOS to narrow the performance
logic designs. strap capacitor. I then successfully gap and better compete with silicon
The bootstrap load was a very designed and fabricated a number gate technology for a short period
popular circuit design trick used in of bootstrap load structures to veri- of time before succumbing to it. By
just about all MOS dynamic circuits fy and optimize their operation, just 1974–1975, the entire MOS industry
of that time. It made possible an out- months before joining Intel, where had switched to silicon gate for all
put signal swing that was not only Intel engineers were still convinced new MOS designs, and it is still in
equal to the power supply voltage, that bootstrap loads could not be use today.
but was also faster than possible made with silicon gate.
with normal MOS loads for the same With the addition of the buried Intel Corporation
power dissipation. In normal loads, contact and the bootstrap load, the In the summer of 1968 I was shocked
the output swing was equal to the silicon gate technology was now in when I heard that Bob Noyce and
supply voltage minus the threshold all respects better than the incum- Gordon Moore had left Fairchild
voltage of the load transistor, which bent metal gate technology. It al- Semiconductor to start another
was significantly augmented by the lowed a designer to integrate in the company. Soon Andy Grove and Les
“body effect.” To make bootstrap same chip size about twice the num- Vadasz, my boss, also left the Fair­
loads, however, it was necessary to ber of random-logic transistors and child lab to join what later became
fabricate isolated capacitors, trivial achieve five to ten times the speed known as Intel.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 11

 Only weeks prior to Noyce’s and new frontier, and I wanted to return When I saw the project sched-
Moore’s departure I had decided to to my first love, building systems, ules that were promised to Busicom,
accept an offer to remain at Fairchild but this time in a chip instead of in my jaw dropped: I had less than six
and not return to Italy, and now I a rack of printed circuit boards as I months to design four chips, one of
was baffled by this start-up phe- had done at Olivetti. which, the CPU, was at the boundary
nomenon that I had never witnessed In April, 1970 I joined Intel, work- of what was possible; a chip of that
in Italy. When my boss left, I imme- ing for my very first boss in the complexity had never been done be-
diately felt that Intel was going to United States, Les Vadasz, who now fore. I had nobody working for me to
use the silicon gate technology I was heading the Intel MOS Design share the workload; Intel had never
had almost finished developing. In department. During my interview done random-logic custom chips be-
little more than a year, my hunch process, Les had been purposefully fore, and, unlike other companies in
proved true. very vague in describing the proj- that business, had no methodology
In time the Intel mission became ect I was supposed to lead, but he and no design tools for speedy and
clear as well: it was to profit from the assured me that it would satisfy error-free design. Furthermore, my
emergent market for semi­conductor my hunger for a challenging chip- boss was consumed with the key
memories, particularly random-ac- ­design project. project going on at that time, the
cess memories (RAMs), by replacing 1103, and made it clear to me that
the incumbent magnetic core mem- The Busicom Project he had little time for me. The Intel
ory with semiconductor memory. On my first day of work, I met Stan 1103 was the first dynamic 1024-b
Intel intended also to sell semicon- Mazor, an engineer working for Ted RAM, the product that was intended
ductor components to build small Hoff, the manager of the Applica- to make Intel successful in the semi-
memory systems for which magnetic tion Research department, who de- conductor memory market, after a
core memories were not well suited, scribed the “Busicom Project.” He lukewarm market response to the
because their large fixed overhead told me the story of how it evolved 1101 and to the 3101 (64-b static bi-
polar RAM). Both Vadasz and Grove,
my boss’s boss, considered my
project a diversion dreamed up by
In the case of the 4000 family, this first step the marketing guys to make some
was led by Hoff with the assistance of Mazor money while waiting for the mem-
and the Busicom team, Shima in particular. ory business—the real mission of
Intel—to mature.
The Busicom project schedule
had been clearly put together with-
cost was independent from the num- from a Busicom proposal of seven out much thought, since it had a CPU
ber of bits. For such small memory custom LSI chips, three of which layout time of seven weeks, only two
systems, the only practical solution were dedicated to make a special- weeks more than a simple memory
was to use serial memory made with purpose CPU, to an Intel proposal chip. A memory chip is a repetitive
either magnetostrictive materials or (spearheaded by Ted Hoff) of a set design whose layout is substantially
with MOS shift registers. of four chips where the CPU was faster to plan and draw than random
Toward the end of 1969, Fairch- general-purpose and entirely inte- logic, where almost every circuit is
ild had become a slow-moving com- grated in one chip. Stan also gave unique and has to be custom fitted.
pany, crippled by the defection of me the basic specifications of the Therefore, not only was the project
many key people to Intel and other four chips, developed over a pe- starting about five months later than
start-up companies and by its own riod of a few months between In- promised to the customer, but also
success. I was frustrated by the slow tel’s Hoff and Mazor and Busicom the duration of each project phase
adoption of silicon gate technology engineers, Masatoshi Shima being had been underestimated, particu-
by the Fairchild MOS division, and the lead engineer. Stan also told larly for the CPU.
soon after Intel announced its first me that Shima was arriving in a Fortunately I was young and ea-
silicon gate MOS product—a 256-b few days to check on the progress, ger to prove myself in my newly
static RAM (the Intel 1101) —I decid- expecting to find the logic design chosen field. I understood comput-
ed to start looking for another job. of the CPU completed and the other ers, I could design both logic and
My desire was to become a large- chips in an advanced state of de- circuits, and I had a lot of experi-
scale integration (LSI) chip designer sign. The problem was that since ence in developing MOS processes
using the very technology that was late 1969 no work had been done and MOS ICs—a very rare combina-
empowering this new trend; silicon on the project, and Busicom was tion indeed, even in those days—
gate technology. I felt this was the not told about it. therefore I felt that if I couldn’t do

12 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

it, nobody could. In particular, my up for the delay. I also told Shima tion by Hoff and Mazor. The design
intimate knowledge of silicon gate that if he would help me there was and development steps followed the
technology gave me an opportunity a chance to meet the new schedule, sequence:
to develop a new methodology for since it would take time to hire the 1) logic design
random logic design that could take people I needed. Finally the difficul- 2) circuit design
advantage of the strengths of that ties were resolved; Busicom accepted 3) composite layout design
new technology. The methodology the new schedule; Shima got permis- 4) r uby cutting (see “The Ruby-
was indeed very successful and was sion to stay for six months to help me; ­Cutting Procedure”)
used for all the early microproces- and I could concentrate on designing 5) mask generation
sors from Intel and Zilog, the micro- what I now called the 4000 family. 6) wafer processing
processor company of which I later 7) first silicon
was cofounder and CEO. The 4000 Family Takes Shape 8) chip verification
Designing a production integrated 9) debugging and characterization
Shima Arrives circuit required many steps, start- 10) production test-pattern
Within a few days of joining Intel, ing with the definition of the chip development
Stan Mazor and I met Shima at the architecture and its basic specifica- 11) transfer to manufacturing.
San Francisco airport on his arrival tions. In the case of the 4000 fam- Steps 5 and 6 were usually done by
from Tokyo. Shima was eager to ily, this first step was led by Hoff groups outside the Design group. Gen-
check the progress made since his with the assistance of Mazor and erally the steps from specifications com-
last visit in December 1969. In par- the Busicom team, Shima in partic- pleted to first silicon, would take at least
ticular, he wanted to check the logic ular, who verified the suitability six months for a simple chip, longer for
design of the CPU and make sure that of the specifications for Busicom’s a complex chip. From specifications to
it would perform according to the several applications. The task of transfer to production—at which point
agreed-on specification. When we the Application group was fin- the responsibility for the product would
arrived at the company, I gave Shi- ished with the completion of the move from the MOS Design department
ma the material I was given by Stan specifications. to Manufacturing—would normally take
a couple of days earlier. Shima was The actual design and develop- from ten to 18 months.
furious when he found out that no ment of the chips was done in an- Since Intel had designed only
work had been done in the last five other department, the MOS Design memories up to that point, it had
months and became very angry at department, and was entirely led not yet developed a methodology
me, the project leader, literally call- by me without any further contribu- for random-logic design as it existed
ing me names. I could not convince
him that, having joined Intel only
a few days before, I could not have The Ruby-Cutting Procedure
done the work he expected. He said, A few words about composite drawing and ruby cutting are in order, since the terms may sound
“I came here to check, and there is foreign to today’s chip designers, who do everything sitting in front of a workstation screen. The
nothing to check! This is just idea!” chip composite layout was drawn by hand with a straightedge and colored lead pencils at 400
He said that his project was ir- to 500 times the actual scale, in a large, reclining drafting table over a Mylar quadrille sheet—
reparably compromised and that he Mylar was used for dimensional stability. The composite layout included all the masking layers
had to call his management to find of the chip superimposed with their proper registration.
out what to do. It took almost one Since the composite could not be used directly to generate the masks necessary for the manu-
week for Shima to calm down and facturing process, it was necessary to prepare a separate layer for each mask, to be photore-
accept what happened. During that duced into a “reticle,” a ten-times-larger version of one of the masks for the chip. The artwork
time I resolved the remaining archi- used for generating a reticle was called rubylith, or ruby for short, and was obtained by first
tectural issues, I started working on laying a sheet of Mylar covered by a thin red film over the composite drawing—which served
the design methodology, and I pre- as a guide—on a precision cutting table. The red film on the Mylar was cut and peeled off with
pared a new schedule that would tweezers in correspondence with the areas to be etched on the chip, thus producing a rubylith
give Busicom “first silicon” (the first of the same size as the composite drawing, but showing only one of its layers.
chip to actually be fabricated from a The large ruby would then be photographed in a gigantic camera and reduced to a black-
design) of all four chips by the end and-white reticle at ten times magnification. The reticle would then be mounted on a special
of December, assuming I could get “step-and-repeat” camera, which reduced the image to actual size and repeatedly exposed it
one engineer and a couple of drafts- onto a photographic glass plate until the plate’s entire surface was covered with an array of
men on time to help me. patterns. This process produced the “master,” out of which “submasters” and then “working
This new schedule was extremely plates” would be produced by contact photography. The working plates were then mounted in
ambitious and would require me to the lithographic equipment that transferred the pattern to the silicon wafers.
work 70–80 hours per week to make

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 13

in companies like Fairchild, Texas architecture, but since the Busicom application of the 4000 family. Just
Instruments, AMI, and others in the proposal had been rejected, I had to like Hoff and Mazor, Shima was not a
business of designing custom chips. do the logic design and verification chip designer and didn’t know much
Such companies had extensive li- of the Busicom chips as well. Most about MOS technology, but he was
braries of circuits and circuit blocks; important, I had to figure out and eager to learn and was very detail
working layouts for various struc- create a ­random-logic design meth- oriented—a highly valuable quality
tures; computer simulation tools odology for silicon gate technology given the lack of verification tools
for logic, circuit design, and test that didn’t yet exist. I also had to at Intel.
program generation; characteriza- design and build a characterization One of the early challenges en-
tion tools; random-logic testers; and, tester, and finally design and build countered during the 4001 design
most important, random logic de- a production wafer-sort tester for was to invent a flip-flop that was
signers expert in the entire process. the 4004 to supplement the expen- guaranteed to come up in a known
state after turning the power supply
on, since there were no extra pins
in the 4001 to dedicate to a reset
Although I didn’t know it at the time, my early signal (each chip was packaged in a
work experience turned out to be absolutely 16-pin dual in-line package, or DIP!).
This flip-flop was to be used in the
invaluable, setting the stage for my future critical control of the tristate exter-
career. nal bus that connected all the chips,
to avoid contention after the power
supply was turned on. I came up
Furthermore, silicon gate tech- sive final-test equipment that was with a circuit that I later patented
nology was new and required quite purchased only toward the end of for Intel.
a different layout style than the one the project. The 4001 layout started the day
used with metal gate, particularly Since I had promised the cus- my first layout drafter, Rod Sayre,
with buried contacts. In fact, several tomer, under duress, to deliver showed up for work. He was hired
Fairchild MOS chip design engineers samples of all four chips by Decem- from Lockheed, where he was a me-
had complained to me that using sil- ber, 1970—less than nine months chanical drafter, and he had never
icon gate they always ended up with from start—and since the CPU alone seen a chip, never mind laid one
larger circuits than with metal gate, would take almost eight months, I out—in those days it was hard to
rather than the smaller ones I had had to work practically on all four find layout draftsmen. All the expe-
promised. When I checked their lay- chips in parallel, staggering them rienced Intel draftsmen were busy
outs, I found out that they were try- a bit so that the critical layout re- with memory projects, and I could
ing to copy exactly the layout they sources would be kept continually not use any of them. I trained Sayre,
had done with metal gate, instead of busy. I decided to design the 4001 and in time he became a very good
figuring out the natural way silicon first, followed by the 4003, 4002, drafter, but at the beginning, and
gate needed to be laid out. Sure and 4004—the last being the CPU. for the duration of the 4001 and
enough, when I showed them how to This sequence allowed me to incre- 4003 layouts, for which he was the
do the layout properly, the resulting mentally develop the methodology only drafter, I had to draw myself
silicon area was quite a bit smaller. and the building blocks I needed to all the building blocks freehand and
I was hired to design and lead the use for the most complex chip, the Sayre would copy them properly in
development of the four Busicom 4004, and also to regain Busicom’s the composite layout.
chips, and take them all the way confidence by showing early suc- After the 4001 layout was com-
through to the transfer to manufac- cess with chips working first time. pleted (Figure 2), Rod Sayre laid out
turing. However, since Intel was new The 4001 was a state-of-the-art the 4003, which was the only really
to random-logic custom circuits, I 2048-b metal-mask-programmable simple chip of the 4000 family and
needed to carry out many more tasks read-only memory (ROM) with four only took two to three weeks to lay
than a typical project engineer work- metal-mask-programmable I/O lines. out. The 4003 was a 10-b static shift
ing for a company already in the cus- I did the logic and circuit design of register with serial input, serial out-
tom chip business had to do. For ex- the 4001 in a couple of weeks and put, and gated parallel ­outputs. For
ample, the logic design was normally gave it to Shima to check. Shima was its design I used a novel flip-flop
done and verified by the customer. an excellent logic designer and was that I had coinvented and patented
In fact, Busicom originally had come also the engineer slated to develop in Italy while working for SGS. I also
to Intel with the complete and veri- the firmware of the Busicom desk- used the same circuit for many of the
fied logic design of their seven-chip top calculator—the first intended counters in the 4002 and 4004. The

14 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

next chip to start was the 4002, the After I had designed a good por- the methodology, particularly the
data RAM of the family. The 4002 was tion of the logic of the 4004, Shima method of combining logic and cir-
organized as four registers of 16 + offered to complete the logic design, cuit design in a single document
4 nibbles each, for a total of 320 b, particularly the control section of the that also contained the notion of
and in addition it had a 4-b output CPU. At this point I felt very comfort- how the chip would be naturally laid
port. Again, I did the logic and cir- able that he could do that task after out. This method avoided the poten-
cuit design in a couple of weeks, and the learning he acquired by assist- tial translation errors in going from
Shima checked my work. It was good ing me with the design of the prior the logic diagram to the circuit dia-
to have somebody else check my three chips. By now I had ­perfected gram; it allowed the designer to focus
work, given that there was no time
to do any logic or circuit simulation,
and Shima was very thorough.
In the 4002 design I used a
three-transistor dynamic RAM cell,
similar to the one that was being
designed in the 1103. The chip in-
cluded also a fair amount of logic
for the memory refresh; the decod-
ing of some instruction, timing,
and control circuitry; and a 4-b
output register. The layout of the
4002 was done by a new drafter just
hired from Intel, Julie Hendricks,
the same person who had laid
out the Fairchild 3708 a few years
before, when she was a trainee.
Fortunately Hendricks was expe-
rienced, though mostly in bipolar
layouts, helping me considerably. Figure 2: The Intel 4001. This chip was a 2048-b, metal-mask-programmable ROM, used to
store the computer program. The chip also contained a section of metal-mask-programmable
When Sayre was finished with the
logic for its four input/output (I/O) lines.
4003 layout, he joined Hendricks
to help speed up the 4002 layout
(Figure 3).
Finally I could start the logic
design of the 4004, though I was
slowed down considerably by hav-
ing to keep the other three chips
moving, all at different phases of
the design process. I also needed
a debugging and characterization
tester in a couple of months when
I expected to receive the first sili-
con of the 4001. Fortunately Hal
Feeney, a design engineer, and Paul
Metrovich, an electronic techni-
cian, were assigned to me to help
with the design and construction
of such a tester. We started with a
discarded memory system, and we
built a programmable pattern gen-
erator by adding electronics to it.
We also designed adjustable-pin
electronics and added a paper tape
reader. The entire contraption was
ready only days before I received Figure 3: The Intel 4002. This chip was a 320-b DRAM used to store data for the computer.
the first 4001 wafers. It contained its own memory refresh circuitry and four output lines with relative control logic.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 15

on the critical circuits, estimating streamlining the translation from cir- Pressed for time, I had to start
the layout capacitances, and thus the cuit design to layout, again reducing and closely supervise the 4004
transistor sizing, from the same doc- the potential for mistakes. Figure 4 layout before the design was com-
ument; and speeded up the layout by shows the resulting chip. pleted, therefore I was coordinat-
ing with Shima so that I could keep
the three drafters busy all the time
while maintaining an excellent lay-
out density, despite the fact that
the design was not yet complet-
ed. For a chip at the limit of what
could be economically produced, I
could not afford to waste any pre-
cious silicon real estate. Joining
Julie Hendricks and Rod Sayre in
the 4004 layout team was Barbara
Manness, an experienced memory
layout drafter who had been at In-
tel nearly from the beginning. How-
ever, no Intel drafter had ever laid
out complex random-logic circuits
before, so the 4004 layout required
close supervision on my part. The
Figure 4: The Intel 4003. This chip was the only medium-scale integration (MSI) component 4004 layout lasted about 14 weeks
of the 4000 family, containing a 10-b static shift register with parallel outputs to be used (42 worker-weeks) compared with
for I/O line expansion. The 4003 was quite helpful because each 4000 family chip was the five worker-weeks of the 4001
packaged in a 16-pin DIP package, severely limiting the number of I/O lines available in
the LSI components.
layout. The original 4004 schedule
prepared by Vadasz had predicted
seven weeks with two drafters, for a
total of 14 worker-weeks. Since each
drafter had to work on a separate
sheet of Mylar (using colored lead
pencils), it was particularly chal-
lenging to maintain a good sense of
the total chip.
When the 4004 layout was com-
pleted, I followed my impulse to
sign my initials, F.F., on the metal
mask, as artists autograph their cre-
ations. I felt it was a true work of art,
where each stroke was not only aes-
thetic but also function-specific and
meaningful. Figure 5 shows a por-
tion of the 4004 chip (Figure 6, later
in this article, shows the complete
chip with my artist’s initials).
Cutting the rubylith was a te-
dious and error-prone operation
that required careful and time-
Figure 5: This image shows a portion of the 4004 chip layout with the large data bus ­consuming checking before the
­drivers (the three large MOS transistors with the orange wavy lines, two on the bottom and rubies could be sent to the mask
one on the left of the photo). The external 4-b data bus was the main highway connecting making service. Since each ruby-
all the chips together. For a system with many 4001s and 4002s, the capacitance of each lith represented only one layer of
data line could be several hundred picofarads, requiring powerful drivers. Moving from
the chip, it was necessary to check
right to left on the image, one can see a portion of the control logic of the arithmetic unit,
followed by a portion of the 4-b arithmetic unit. Notice the higher random logic layout its integrity and alignment by su-
density of the 4004 compared to the other three chips of the family. The 4004 was the perimposing the rubies of the oth-
only one of the four chips to use buried contacts. er layers, in various combinations.

16 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

When the ruby cutting was fin-
ished, many people were recruited
to help spot potential errors, and
it could take several weeks to com-
plete the checking, an operation
that could be done only at the end
of the cutting process. Checking
the composite layout was far less
stressful because it could at least
be partially done during its draw-
ing and not just at the end.
The ruby cutting of the 4004 was a
challenge because the entire compos-
ite was larger than the cutting table
and had to be done in two pieces (to
the best of my recollection). Shima and
I carried the brunt of the 4004 ruby
checking—then the most complex chip
ever done at Intel—but Hal Feeney and
others also cheerfully joined forces to
help speed up the process. Figure 6: The Intel 4004, the world’s first CPU-on-a-chip. This 4-b microprocessor contained
After the 4004 ruby checking, approximately 2300 random-logic transistors. The 4004 basic instruction cycle was 10.7 μs
and used eight clock periods of a two-phase clock running at 750 kHz. This time was longer
Shima returned to Japan with a brief
than strictly necessary (by approximately a factor of 2.5) because of the heavy use of
detour to Egypt for a well-deserved multiplexing to send the 12-b address, the 8-b instructions and the 4-b data on the same
vacation. I continued working 70– four data bus lines. The typical power dissipation of the 4004 was 750 mW. Notice the
80 hours a week for many more author’s initials (F.F.) in the lower left corner.
months before I could take a brief
break. During the peak of my work,
my wife, Elvia, turned to her family much work and so many error-prone Eve would usher out 1970, and most
for help with our three-month-old steps. The miracle of technology! people had left the lab. It was fortu-
daughter, since I was so busy with After a few days of checking and nate, because nobody was around
the project. She went to Italy where verification, everything was found to see how nervous I was. My trem-
she stayed for several months, al- to work as expected, not only func- bling hands placed the first wafer
lowing me to work very hard with- tionally but also the clock speed at in the wafer prober. I lowered the
out feeling too guilty about being high temperature, and all the critical probes into the first chip expecting
missing in action. signal and supply margins were ex- to see the now familiar activity in
ceeding the design targets. It was a the data bus, but instead nothing
The Moment of Truth great relief! I passed the litmus test, happened. “Oh, well,” I said to my-
Shortly after Shima returned to and now I couldn’t see any show- self, “that must be a bad chip.” I low-
­Japan, I received the first silicon stopper for the rest of the family. ered the probe on another chip with
of the 4001. This was my first LSI Busicom was also relieved that their the same results, and then probed
chip design, and I was very ner- first chip worked as expected. several more chips, always with
vous because it was the real test of A few weeks after receiving the the same symptoms. “Maybe this
my methodology: If the 4001 didn’t first 4001 wafers, I also got the first is a bad wafer,” I thought. I tested
work, all the other chips would have silicon of the 4003. That chip also another wafer, and got exactly the
been hopeless because its design worked the first time, adding to my same behavior. By this time I was
style was replicated in all of them. confidence level. In late November I sweating profusely thinking, “Noth-
The characterization tester had just received the first silicon of the 4002, ing works! How could I have screwed
been completed enough to verify the which also was fully functional but up so badly?” I decided to look at
4001 operation, and I was delighted for one minor mistake that was the chips under the microscope,
when the oscilloscope displayed quickly identified and fixed. and sure enough, the problem was
the familiar waveforms I had drawn Finally came the big day when obvious: during the manufacturing
many times on paper and now were I was given the first wafers of the process the buried contact layer
replayed live! I was stunned by the 4004. The moment of truth had ar- was left out by a technician’s mis-
fact that the chip was doing exactly rived. It was the end of the work- take, therefore most of the transis-
what it was supposed to do, after so day, a few days before New Year’s tor gates were not connected, hence

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 17

no life. Now my chance to meet the said, “It works!” And we shared feel- In January 1971, Young Feng, a
schedule had been blown away by ings of exhilaration and happiness, new engineer, joined my team to
a trivial mistake in manufacturing knowing that something very sig- help me with the extensive charac-
that was going to cost me about nificant had happened. That was terization and the transfer to pro-
three weeks of delay. the night the first microprocessor duction of the 4000 family. That
About three weeks later I re- was born, almost nine months after same month, the success of the
ceived a new run of 4004 chips. I had started the project. I had just 4000 family brought another sur-
This time nothing was left out; I turned 29 the month before, and I prise: I was assigned the job of de-
made sure of that by checking the realized that nine years earlier, at signing the 1201, supervising Hal
wafers under the microscope be- about this time of the year, I had Feeney who had been helping me
fore loading the first one on the just completed another computer, with the 4000 family testing since
probe station. As before, I received made with germanium transistors, about August 1970.

The Intel 1201

The story of the 1201 started with a visit to The story of the 1201 started with a
visit to Intel by Computer Terminal
Intel by Computer Terminal Corporation Corporation (CTC, later renamed
toward the end of 1969. Datapoint Corp.), toward the end
of 1969. CTC was a customer of
Intel that purchased shift register
the wafers at the end of the work- that had about the same capabili- chips for the memory of its com-
day when most people had already ties as this one, except the new one puter ­terminals, a typical use of
left the lab, and I set out to spend could all fit into a single printed cir- shift registers at that time. CTC
most of the night probing the 4004. cuit board, instead of a few hundred had plans to build a new intelligent
I breathed much easier after the fa- boards; had about ten times higher terminal, called Datapoint 2200,
miliar signals in the data bus ap- speed; and consumed almost 1,000 at the heart of which was a simple
peared in the scope. Now I was in times less power. What a difference CPU of its own design implemented
business! I probed until 3 or 4 a.m., nine years make! with TTL components. CTC wanted
finding that everything was work- In the following days I continued Intel to design a special custom bi-
ing as expected until, exhausted, I to check the 4004 and found a couple polar RAM chip to be used as the
left for home. of minor problems that were rela- stack register for its CPU.
Elvia had been waiting to hear tively easy to diagnose and fix. In the When Stan Mazor found out the
the news. She woke up from a light meantime, after Shima’s return to Ja- purpose of that custom chip—fresh
sleep as soon as she heard my steps pan, Busicom had finished building from his participation in specifying
and immediately asked, “How did it a 4000 system simulator with a full the 4004—he ventured to tell CTC
go?” Still in a state of excitement I 4004 simulator and RAM replacing that Intel had the technology to put
the 4001s so that the calculator firm- CTC’s entire CPU on a chip, not just
ware could be easily loaded, verified, the stack memory. This was a pret-
and changed. This was necessary ty bold statement since the 4004
since the 4001 was a metal-mask- had not yet been designed, and he
programmable ROM, taking several was not a chip designer! Eventu-
weeks to be fabricated and therefore ally CTC was convinced that Intel
appropriate only when the firmware could integrate the CTC 8-b CPU
was fully debugged. Shima, the de- into a single MOS chip and signed
veloper of the calculator firmware, a contract for the development of
sent me the four verified ROM codes a custom product, called the 1201.
in January 1971, soon after he heard Hal Feeney was hired to lead the
the news that the 4004 was working. design of the 1201, and joined In-
Figure 7: Federico Faggin next to the
engineering prototype of the Busicom Intel could then fabricate the 4001s tel in March, 1970, just weeks be-
calculator—the very first application of the in parallel with the new corrected fore I did. Before Intel, Feeney had
microprocessor. This original artifact was version of the 4004. Therefore, by worked for General Instruments,
a personal gift of Yoshio Kojima, presi- mid-March, when the revised silicon where he designed a number of
dent of Busicom, to the author in 1971.
of the 4004 was expected, Busicom custom MOS random-logic chips.
This working prototype was gifted by the
author and his family in 1996, when this could build and verify the entire cal- I found out about the 1201 soon
picture was taken, to the Computer History culator with the final 4000 family after I joined Intel, and I was dis-
Museum, Mountain View, California. components (Figure 7). appointed to find out that there

18 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

was another microprocessor in would have considered prohibi- and many people knew how to do
development at Intel. Clearly the tive to produce, clearly showing logic design. A CPU in a few MOS
1201 would be finished before the the advantages of the silicon gate chips had already been done before
4004, I reasoned, since Feeney had technology with ­buried contacts. the 4004 by Four-Phase Systems,
to design only one chip while I had I later surmised that the highly for example. Furthermore, given
four, and the 4004 was going to competitive nature of the semicon- the clear semiconductor industry
be my last one. I was so busy with ductor business, stirred up by the trends, a CPU-on-a-chip was inevi-
my own challenges, however, that customer’s self-interest, convinced table. It really was only a question
I soon forgot about it. The 1201 TI that, “If Intel can do a CPU-on-a- of who would do it first, and un-
project, however, dragged along chip, so can we!” questionably it happened at Intel.
for several months but never got
into high gear and eventually was
mothballed; Feeney was reassigned
I personally thought that there were
to a memory project and then to
me. Fundamentally, he was over- many control applications where the 4000
whelmed by the magnitude of the family would do well, and I set out
project—not only by the complex-
ity of the job, but also because he
to find out for myself.
had never designed a chip with sili-
con gate technology before and the
lack of design methodology and Many years later I was told by Vic Announcing the
support made the task daunting. Poor—CTC’s vice president of en- Microprocessor to the World
I inherited the 1201 project after gineering in 1971—that the TI chip During the design of the 4000 fam-
the 4004 was essentially completed never functioned, and of course it ily, I found out that Intel had entered
and my experience, combined with was never used. TI also never made into a contractual arrangement with
the now-proven methodology, al- that chip available in the market, Busicom giving them exclusive
lowed me to lead the project to its even after Intel’s announcement of rights to their use. I was upset be-
successful conclusion with Feeney the 4004 and the 8008. It was only cause, seeing the great potential of
doing the detailed design. The 1201 used for public relations purposes. the microprocessor, I wanted my
took the entire year of 1971 to be This simple fact serves to prove that work to have a bigger impact than
designed, with first silicon out in the implementation of the micropro- just being a custom job for Busicom.
December, and became commercial- cessor was far from a routine design With the project nearing comple-
ly available in April 1972 with the job. TI was then a leader in MOS cus- tion, I started lobbying with Intel’s
name 8008. The 8008 is at the origin tom chip development with many management to sell the 4000 family
of the spectacularly successful x86 powerful design tools and much ex- in the open market. Hoff and Mazor
family of Intel microprocessors that perience in random logic design, yet believed that Busicom would at most
are powering most of the personal it could not make its first micropro- give up their rights for noncalcula-
computers in use today. cessor work, though TI claimed it did. tor applications, and they felt that
Another interesting develop- If the TI chip did not work, my point the 4000 family was only good for
ment occurred in April 1971, when is immediately evident, but even if calculator-like applications, there-
Texas Instruments (TI) announced the chip did work, it happened a few fore they were not initially con-
having successfully designed a months after the 4004 was complet- vinced that selling the 4000 family
CPU-on-a-chip, as TI called it, only ed, thus proving again that “invent- in the open market for noncalcula-
one month after the 4004 was ful- ing” the microprocessor was still an tor applications was a good idea.
ly functional. In other words, TI issue of implementation. They felt, however, that the more
had also designed a microproces- Had I not worked so hard, TI general-purpose architecture of
sor. We later found out that such would have beaten Intel to the the 1201 made it more suitable for
development started as a custom punch, and they would now be general-purpose use than the 4000
project for CTC, which wanted a properly hailed as the inventors family. Of course, introducing the
second source for its CPU. The of the microprocessor, rather than 1201 in the market was also prob-
specification of this chip was of Intel. After all, the essence of the lematic since the 1201 was original-
course identical to the 8008, ex- microprocessor was the successful ly bound by an exclusivity arrange-
cept TI used low-threshold-voltage design of a CPU into a single chip. ment with CTC similar to that with
metal gate technology for its de- That was the crucial step that had Busicom for the 4004.
sign. The reported TI chip size was not been done before. Many people I personally thought that there
twice that of the 8008, a size Intel knew how to architect simple CPUs were many control applications

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 19

where the 4000 family would do was metal-mask-programmable, I new vice president of marketing.
well, and I set out to find out for decided to use instead a product Finally, during a phone conversa-
myself. The opportunity came with that had just been developed by tion with Shima, around the middle
a new project I needed to start: a Dov Frohman at Intel: the 1702, the of 1971, I found out confidentially
wafer-sort tester for the 4004. I de- world’s first electrically program- that Busicom was not doing well
cided to use the 4004 to perform the mable, ultraviolet-erasable ROM. in the market and could not com-
pete effectively because the price
they were paying for the 4000 fam-
Finally came the big day when I was given ily chips was too high. Shima also
told me that Intel CEO Bob Noyce
the first wafers of the 4004. and Ed Gelbach were going to visit
Busicom shortly. That information
gave me the break I needed: I told
control logic for the tester, instead The 1702 was intended to aid the Bob Noyce about my conversation,
of using random logic for it. I fig- development, debugging, and pro- suggesting that he might be able to
ured that in that way I would find totyping of ROM codes that, at the get a release from exclusivity from
out firsthand whether or not the end of the market testing, would Busicom, for noncalculator applica-
4004 was appropriate to the task. I then be translated into a conven- tions, in exchange for a lower price.
would also gain insights into what a tional mask-programmable and Of course I also pushed once more
customer would have to do to apply pin-compatible ROM, the 1302, re- the case that the 4004 was very
the 4000 family to solve problems. placing the 1702 for production in good for control applications, as I
Finally, I was very interested in pro- exactly the same printed circuit had learned in my experience with
gramming the 4004, a task I had boards. All I had to do, then, was the tester project.
never done before. to design an appropriate interface Shortly after Noyce and Gelbach’s
Since there were no program- between the 4004 and the 1702 to visit to Busicom, I learned that In-
ming tools for the 4004—that make the 1702 behave like a 4001. tel had been successful in negoti-
was considered the job of Busi- The tester project was quite ating a release from exclusivity
com—and I was pressed for time, successful and convinced me that and had ­decided to introduce the
I wrote the tester control program the 4004 could be effectively ap- 4000 family in the market. I was
by using the instruction mnemon- plied for control applications. I delighted. Soon after that deci-
ics, and then I had to literally used that experience to argue to sion, Intel appointed Hank Smith
translate it by hand into machine management that the 4000 fam- to lead the marketing effort for
­language—the ones and the zeros ily had market value, building a the new microprocessor products,
that needed to be stored in ROM, more convincing case for it, par- and Feeney and I from MOS R&D,
the 4001. However, since the 4001 ticularly with Ed Gelbach, Intel’s together with Hoff and Mazor from
Applications, helped the new mar-
keting group prepare for the 4000
family market launch, with a new
coined name: MCS-4, standing for
microcomputer system 4-bit. The
MCS-4 was soon to be followed in
early 1972 by the MCS-8 introduc-
tion, with the 8008 at the core of
the new family and the rest of the
MCS-8 chip family being mostly
standard Intel memories.
In November, 1971, the official
birth announcement of the micro­
processor to the world finally hap-
pened. A two-page spread in the
well-read Electronic News maga-
zine read: “Announcing a new era
of electronics,” and briefly de-
scribed the microprocessor and its
Figure 8: This is the first microprocessor advertisement, a two-page spread in Electronic availability (Figure 8). This turned
News in November 1971. out to be a prophetic ­statement, a

20 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

rare occurrence in advertising; the 1974 Zilog was born. At Zilog I ini- About the Author
impact of the microprocessor on tially conceived a microcontroller Federico Faggin (Faggin@foveon.
our lives has been truly extraor- (which later became the Z8), but com) is president, chief executive
dinary, as only a handful of other then I opted for a new generation officer, and a director of Foveon
inventions in the last 100 years 8-b microprocessor, the Z80. Intro- Inc. He is also chair of the board of
have been. duced in mid-1976, the Z80 became Synaptics Inc., and of Zilog, Inc. He
The success of the MCS-4 and the wildly successful, powering many was the cofounder of both compa-
8008, combined with my passion to of the early personal computers and nies as he was of Cygnet Technolo-
see the microprocessor take root in hundreds of other applications. The gies Inc. He worked for Intel Corp.
the world, propelled my career for Z80 is still in high-volume produc- from 1970 to 1974. In 1970–1971
the next ten years. In late 1971 I con- tion in 2008, 32 years after its mar- he led the design and development
ceived and architected the 8080, pro- ket debut. of the 4004, the world’s first mi-
posing the idea to Intel’s management. The Z80 was the last engineering croprocessor, and the other three
It took about nine months before I project I directed, marking the end chips of the MCS-4 product family.
got permission to start developing of my technical career and the be- In 1971–1972, he led the develop-
it. That delay reduced Intel’s market ginning of my entrepreneurial ca- ment of the 8008, the world’s first
lead to only six months, with strong reer, which is still going on to this 8-b microprocessor. He architected
competition from the Motorola 6800 day. I was the first CEO of Zilog and and led the development of the
microprocessor. I also conceived and the CEO of two other companies I 8080 microprocessor and the 4040
architected the 4040, an improved cofounded. Five years ago I also microprocessor. He also designed
version of the 4004 that could also became CEO of Foveon, a company or supervised the design of more
use standard memories. I gradually with a highly innovative image sen- than 25 other commercial inte-
took over more responsibility and sor technology. I have been involved grated circuits. He joined Fairchild
more projects, and in early 1974 I was in many other start-up companies Semiconductor in 1968, where he
promoted to R&D department manag- as an angel investor as well. I love led the development of MOS silicon
er in charge of all MOS chip designs, to bring new ideas into the world, gate technology and designed the
except for dynamic memories. My and I find that the most effective world’s first commercial integrated
major contribution in memories was way to do so is through a start-up circuit to use that technology, the
the redesign of the Intel 2102 (5-V, company where focus, passion, and Fairchild 3708. Born, raised, and
1024-b static RAM), proposing a new energy are at their highest. educated in Italy, Federico Faggin
n-­channel process technology with became a naturalized U.S. citizen
depletion loads that my boss, Vadasz, References in 1978. He is the recipient of many
opposed. I eventually succeeded [1] F. Faggin and F. Capocaccia, “A new inte- honors and awards including the
grated MOS shift register,” in Proc. 25th
in convincing him to use depletion Int. Scientific Congr. Electronics, Rome, 1988 Marconi Prize, the 1994 IEEE
load, and the new product, called the 1968, pp. 143–152. W. Wallace McDowell Award, and
[2] F. Faggin, T. Klein, and L. Vadasz, “Insulat-
2102A, was spectacularly successful, ed gate field effect transistor integrated the 1997 Kyoto Prize. In 1996, he
with an access time four times less circuits with silicon gates,” in Int. Electron was inducted in the National In-
Devices Meeting Tech. Dig., Washington,
than the older version. That same DC, 1968, p. 22. ventor’s Hall of Fame for the coin-
process technology was then used for [3] F. Faggin and T. Klein, “A faster generation vention of the microprocessor. He
of MOS devices with low threshold is rid-
several future generations of memo- ing the crest of the new wave, silicon gate received the Lifetime Achievement
ries and microprocessors. IC’s,” Electronics, Sept. 29, 1969. Award of the European Patent Orga-
[4] F. Faggin and T. Klein, “Silicon gate tech-
nization in 2006.
nology,” Solid-State Electronics, vol. 13,
Becoming an Entrepreneur pp. 1125–1144, 1970. He holds a doctorate in physics,
Intel was a memory company mak- [5] F. Faggin and M.E. Hoff Jr., “Standard parts summa cum laude, from the Univer-
and custom design merge in four-chip
ing microprocessors in order to sell processor kit,” Electronics, pp. 112–116, sity of Padua (1965). He also holds
more memories. I wanted to be in Apr. 24, 1972. honorary doctor degrees in com-
[6] F. Faggin, et al., “The MCS-4-An LSI micro
a company whose core business computer system,” Proc. IEEE Region 6 puter science from the University
was microprocessors, not memories. Conf., 1972. of Milan (1994), in electronic engi-
[7] F. Faggin, “Power supply settable bi-stable
Since such a company did not ex- circuit,” U.S. Patent 3753011, Aug. 14,
neering from the University of Rome
ist, I had to start my own. I invited 1973. Tor Vergata (2002), and in electronic
[8] M. Hoff, S. Mazor, and F. Faggin, “Memory
Ralph Ungermann, one of my man- system for multi-chip digital computer,”
engineering from the University of
agers, to join me, and by the end of U.S. Patent 3821715, June 28, 1974. Pavia, Italy (2007).

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 21

by Marcian E. Hoff

How rethinking a customer’s specifications led to

simplifications that made the first microprocessor possible.

W
e now routinely buy personal ­computers in which microprocessors with mil-
lions of transistors perform at gigahertz speeds, so it is easy to forget that
the first microprocessor was not a simple or obvious choice to produce. At the
time it was being contemplated, metal oxide semiconductor (MOS) technology
was still quite new, and integrated circuits themselves had existed less than a
decade. While MOS circuits with a thousand transistors were being manufactured, the econom-
ics of integrated circuits of that day limited how far the technology could be pushed. A 2-in-
diameter silicon wafer, costing perhaps US$50 to process, might have a 10% yield for a 0.02-in2
die. If we pushed the die size higher, there would be fewer potential die per wafer, and yield
would fall precipitously. Table 1 shows how the die cost might vary with die size.

IC Economics in 1968
A die costing US$82 would have to sell for a price close to US$200 for the vendor to show a
profit. Since a minicomputer with much higher performance than MOS might be made us-
ing 100 small- and medium-scale integrated circuits, each costing about US$1 installed,
overly ambitious MOS designs would probably fail to develop a market.
Integrated circuits needed to be sold in large volumes to recover their relatively
large design cost, typically in the order of US$50,000 per design. A concern of the
day was that large-scale integration (LSI) would have limited use as computer log-
ic because of the “parts proliferation problem”; i.e., when logic-chip complexity
reached 100 gates or more, any one chip design would find application in only one
computer, and a 10,000 gate computer might need 100 different chip designs.
The design cost of all those different LSI chips would render the LSI-based com-
puter uncompetitive with other technology.

Intel Is Founded—1968
I was born in Rochester, New York, and did my undergraduate study at Rens-
selaer Polytechnic Institute in Troy, New York. After receiving a bachelor of
electrical engineering degree in 1958, I moved to California to do graduate
work at Stanford University. I received a Ph.D. degree in 1962 and stayed
on at Stanford doing government-sponsored research on what would
today be called neural networks. One day in the summer of 1968, I
received a phone call—the caller, Bob Noyce, introduced himself and

Digital Object Identifier 10.1109/MSSC.2008.930942

22 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/09/$25©2009IEEE

asked if I might be interested in join-
Table 1. Effect of Die Size on Cost.
ing a new company he was starting.
The new company, Intel Corpora- Die area (in2) 0.01 0.02 0.04
tion, was being founded by Noyce and
Percent yield 31 10 1
Gordon Moore, who had both just left
Fairchild Semiconductor. I interviewed Die cost US$0.60 US$3.80 US$82.00
at Bob Noyce’s home and was fortunate
to receive an employment offer, be-
coming employee number 12 at Intel. pany began operation in September for some years, I was surprised to
The purpose of the new compa- of 1968. find how much could be learned
ny was to develop semiconductor I was given the title “manager of from Intel’s marketing people and
memory that could compete with applications research.” My respon- by talking to potential customers
the magnetic core memory of the sibilities were to help define the about what they might require from
day and could be expected to reach memory products Intel would de- semiconductor memory products.
high-volume production. Two new velop, with the expectation that I Magnetic core memory was well
semiconductor processes were to be would help to produce application established as the standard computer
developed: a Schottky bipolar pro- aids for those products when they memory by that time, and it was
cess and a self-aligned p-channel were ready for sale. Having been in understood that it might take some
silicon gate MOS process. The com- the rather biased world of academia time for a sizable customer base to

© creatas & photo f/X2

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 23

materialize. As the new processes Corporation (NCM), whose calculators The specifications for the chips
became production worthy, Intel were sold under the name Busicom. would be developed in Japan by
management decided that some Intel agreed at that time to do custom an organization known as Electro-
needed revenue might be derived by LSI for them. Figure 1 shows the first ­Technical Industries (ETI), and even-
performing custom development for page of the agreement between the tually those specifications would be
a few selected customers. two companies. Intel was confident transferred to Intel for completion
that its new silicon-gate MOS technol- of the chip designs. In June of 1969
The Busicom Project ogy was ahead of its competitors and a team of three engineers, Masatoshi
In April 1969, Intel met with the man- felt comfortable that random-logic ­Shima, Hiroyuki Masuda, and Sho-
agement of a Japanese calculator man- chips up to 2000 transistors would be go Takayama, came from Japan to
ufacturer, Nippon Calculating Machine quite manufacturable. transfer the specifications to Intel.
I was assigned to act
as liaison for the en-
gineering team. My re-
sponsibilities were pri-
marily to help connect
the Japanese engineers
with the appropriate In-
tel employees. I should
emphasize that I was
not given design re-
sponsibility, primarily
because I did not have
experience in MOS chip
design. I did have some
MOS circuit experience,
primarily from writing
and testing computer
simulations of MOS cir-
cuits. These computer
simulations were used
to aid the design of
MOS integrated circuits
because, unlike bipo-
lar integrated circuit
concepts, which could
usually be tested by
building breadboards
with discrete compo-
nents, MOS devices
were too sensitive to
parasitic capacitance to
be breadboarded.

Exploring Ways
to Simplify
Having designed in-
terfaces to various
computers, including
an IBM 1620, an IBM
1130, and a Digital
Equipment Corporation
PDP-8, I was curious
about the calculator
Figure 1: The first page of the 28 April 1969 agreement between Intel and NCM to make LSI chips for the design and studied the
Busicom calculator—an agreement that led to the first microprocessor. specifications ­perhaps

24 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

more than was necessary to
merely transfer the design. At
the April meetings with Busicom, I interviewed at Bob Noyce’s home and was
I had learned the cost targets for
the chips, and I soon became con-
fortunate to receive an employment offer,
cerned that the specifications were becoming employee number 12 at Intel.
more ambitious than we had origi-
nally expected, both in terms of
logic complexity and package pin
count. I expressed some of my con- tary and made to operate quickly process 4 b per operation. It seemed
cerns to Bob Noyce, and he encour- enough, then perhaps it could be that by providing a instruction for
aged me to explore ways by which used to perform some of those func- converting a 5-b binary value in the
the design might be simplified. tions by programming, instead of by range from 0 to 19 into a valid binary
The design specifications had separate and unique chips. Eliminat- coded decimal (BCD) digit and a car-
several features that I thought might ing some or all of those chips would ry, the processor could be capable
be exploited to achieve simplifica- help ease the load on Intel’s limited of both binary and BCD operations.
tion. The specifications included a MOS-chip design staff. Eliminating the serial logic needed
read-only memory (ROM) that was for a shift-register interface reduced
used to adapt the proposed chip set A More Primitive Architecture the processor complexity, while
to different calculator models, but With continued encouragement from very little extra logic was needed
it seemed to me that the instruc- Noyce, I started looking at a more to allow parallel 4-b operations. An-
tion set executed from that ROM primitive architecture that would other promising innovation was to
could be made simpler. use three-state logic for
In addition, adding a buses. MOS technology
multilevel subroutine made it quite easy to
capability should allow multiplex signals onto a
ROM-based routines to bus, and the use of mul-
substitute for complex tiplexing would permit
instructions. The mem- us to reduce the pack-
ory to be used in the age pin count. At the
original design called time there were some
for 64-b shift regis- concerns about silicon-
ters that required six gate devices in plastic
transistors per bit and packages. Being able to
rather complex logic to eliminate the need for
track data location. It 40-pin packages was ad-
seemed that the DRAM ditional cost insurance.
being developed at Intel With a multiplexed
might be a better choice, 4-b-wide bus, all of the
because it required but chips of the set could be
three transistors per in 16-lead packages, and
bit, and could access even with that limited
data much more sim- pin count, each package
ply and rapidly than made available a few
the shift register. pins for input/output
Other features of the connections.
original specifications An instruction cycle
were separate chips of eight steps seemed
for such functions as reasonable, with three
scanning and debounc- steps for sending a 12-b
ing a keyboard, main- address to program
taining a multiplexed ROM, two steps to fetch
display, and controlling Figure 2: Once the specifications for chip numbers 4001, 4002, 4003, and an 8-b instruction, and
4004 were finalized, the design was transferred to Intel’s MOS group, head-
a small drum printer. If three steps for execu-
ed by Leslie Vadasz. Les brought Federico Faggin on board in April 1970 to
an instruction set could perform the actual chip circuit design and layout, which were completed tion. Because the DRAM
be made more rudimen- early in 1971. This photo shows Intel’s staff about this time. was used only during

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 25

instruction execution, no access finishing touches on the specifica- Vadasz. Figure 2 shows Intel’s staff
to it would occur for the first five tions for the simplified Intel chip about this time. Vadasz brought
steps of each instruction cycle. Dur- set proposal. In mid-September, In- Federico Faggin on board in April of
ing that time, the DRAM could be re- tel’s Marketing department sent a 1970 to perform the actual chip cir-
freshed. Because each chip needed letter to Busicom, suggesting they cuit design and layout, which were
to know what step of the cycle was con­sider the simplified design. Ulti- completed early in 1971.
being performed, some timing in- mately, Busicom management came The 4004 central processor chip
formation needed to be sent from to California, and we presented them had an area of just about 0.02 in2,
the CPU to other chips in the sys- with two options: a somewhat modi- which allowed the chip to be very
tem. It seemed reasonable to count fied version of the original Busicom competitive. Within a year, the 4004
down the clock on each chip and ­chip-set specifications, and the Intel was priced at US$60 each in single
synchronize the chips via a single approach. Even then, Mazor and I em- quantities, at US$30 each for a quan-
signal from the CPU rather than to phasized the more versatile nature tity of 100, and at even lower prices
use more pins. Even with the eight- of the Intel approach. At the end of when purchased in much higher
step instruction cycle, the use of the session, Busicom’s management volumes. At those prices, the 4004
DRAM allowed instruction execu- team chose the Intel design. was a much less expensive proces-
tion times to be about one-tenth of The main goal of the effort thus sor than could have been built using
what would have been needed had far was not to make a single-chip standard logic families.
64-b shift registers been used. The computer; rather it was to simplify
The 8008 Microprocessor
The 4004 was not the only micro-
processor in development at Intel
Stanley Mazor joined my group and helped put during 1970. In December of 1969,
the finishing touches on the specifications for Computer Terminals Corporation
(CTC) had contacted Intel about a
the simplified Intel chip set proposal. custom memory chip for an intelli-
gent terminal CTC was developing.
The memory chip was to be used to
implement various registers for a
transmission of the 12-bit program the design and to reduce the number fairly simple general-­purpose pro-
address to program ROM was done of complex chips to be developed. cessor within the terminal. By this
low-order bits first, which had two At the time we made the presenta- time Intel was committed to build
advantages: tions to Busicom’s management, the the Busicom microprocessor, and
1) The program counter could be ad- central processing unit would have when we realized that the CTC pro-
vanced by using only a 4-b incre- consisted of two chips, with the sec- cessor was not that much more com-
menter with end-around carry. ond chip being primarily devoted to plex than the Busicom processor, we
2) The relatively slow access to ROM generating timing signals. Later, as proposed that CTC’s processor also
content could take place while the design specifications were being be implemented as a single chip.
the central processor transmit- finalized, it became evident that the That proposal ultimately led to the
ted the high-order program ad- timing functions could be integrated Intel’s second microprocessor, the
dress bits (which determined onto the central processing chip. 8008. The 8008 was intended to op-
which ROM would respond). With that change, the target specifi- erate with standard semiconductor
Most of these concepts were de- cation called for a central processing memory devices, so unlike the four-
veloped in July and August of 1969. unit implemented on a single chip. chip Busicom set, only one chip, the
I tested the proposed instruction The chips of the Busicom set CPU itself, was defined.
set by writing routines for arithme- were ultimately given the num- After the Busicom set and the
tic, keyboard scanning, and display bers 4001, 4002, 4003, and 4004; 8008 were transferred to Intel’s MOS
maintenance. With reasonable esti- the 400 was the central processing group, my activity primarily con-
mates for processor clock speeds, it unit. Early in 1970, a contract that sisted in developing design tools
appeared that most of the calculator gave the rights to the set to Busi- for the microprocessors, as well as
interface functions could be done com was signed, although contract other applications development.
by programming. clauses did indicate that other sales One product needing support was
might be contemplated. the newly developed Intel erasable
The Project Is Launched With the specifications final- programmable read-only memory
In September of 1969, Stanley Mazor ized, the design was transferred to (EPROM). This device was ideal for
joined my group and helped put the Intel’s MOS group, headed by Leslie developing applications that would

26 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

ultimately be cast into ordinary
mask-programmed ROM, so my
group developed circuit boards that
allowed 4004 microprocessor appli-
cations to be developed on EPROMs,
with the expectation that they would
eventually be converted to the mask-
programmed 4001. We also devel-
oped tools that allowed “burning”
data into the EPROM’s.

Making the Microprocessor

an Intel Product
When the Busicom chips became
available early in 1971, we found
that they could be very useful for
many applications in our own lab
where we had been using medium-
and small-scale integrated circuits.
I then learned that Busicom was
requesting price reductions. Mazor
and I begged our Marketing depart-
ment to get the rights to sell the
chips to other customers, feeling
that since we found microproces-
sors to be useful for our applica-
tions, other engineers would find
them useful as well. In May of 1971,
Intel negotiated the right to sell the
chips to others, but Intel Marketing
and upper management were reluc-
tant to offer them.
A major concern was that the
large computer companies­—that
is, our memory-product customer
base—would see us as competitors
and reject us as suppliers. We tried
to emphasize that the applications Figure 3: The first page of Intel’s first microprocessor data sheet.
for the relatively low-performance
Intel microprocessors were very MCS-4 family (consisting of the 4001, allowed it to achieve minicomputer-
likely to be different from those for 4002, 4003, and 4004) was advertised class performance.
more expensive minicomputers with with the proclamation “Announcing
far higher performance. In fact, one a new era of integrated electronics.” In Retrospect
of our concerns was that customers, To help launch the new products, People have often asked me if we
used to minicomputer capabilities, my group produced a user’s manual foresaw the applications for mi-
would try our microprocessors and and assisted in the preparation of croprocessors, usually referring to
be so disappointed by their limited the data sheet. The first page of that personal computers. The market we
per­formance that a market for them data sheet is shown in Figure 3. anticipated for microprocessors is
would not develop. Throughout the The 8008 followed in early 1972. what today would be called embed-
summer of 1971, there were many Interest in the products was high, ded control. While we might have
discussions about how the prod- sales followed, and feedback from liked to see personal computers
ucts might be supported. When a customers, primarily users of the developed, memory and peripheral
new marketing director, Ed Gelbach, 8008, suggested improvements that devices, such as printers and disk
joined Intel, the attitude changed ultimately led to the 8080 in early drives, were then so costly that it
in favor of the microprocessor as a 1974. The 8080 also took advantage is unlikely that many could have af-
product, and in November 1971 the of a new n-channel MOS process that forded them.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 27

 Advances in the underlying dustry. I ­believe we developed the About the Author
semiconductor technology have first ­commercially available mono- Marcian E. “Ted” Hoff (MHoffJr@
made enormous improvements in lithic telephone coder-decoder (CO- aol.com) received a bachelor of
performance and almost unimagi- DEC), a device that converts be- electrical engineering degree from
nable reductions in cost. An ar- tween analog and ­digitally-encoded Rensselaer Polytechnic Institute,
ticle I coauthored in Intel’s early voice signals. Our group also pro- Troy, New York, in 1958 and M.S.
days predicted that semiconduc- duced the first commercially avail- and Ph.D. degrees, both in electrical
tor memory would cost less than a able monolithic switched-­capacitor engineering, from Stanford Univer-
penny a bit by 1972—a prediction filter, which provided needed an- sity, California, in 1959 and 1962,
that proved true. However, at that tialiasing for the CODEC. respectively. During the summers
of 1954–1959 he worked for Gen-
eral Railway Signal Co., Rochester,
where his work resulted in two pat-
ents. After receiving his Ph.D. de-
Around 1975, at Bob Noyce’s request, I started gree, he remained at Stanford Uni-
a group that developed products for the versity as a research associate from
telephone industry. 1962 to 1968. In September 1968 he
became manager of Applications
Research at the newly founded Intel
Corporation. In 1975 he headed a
price, the memory to store one I left Intel in 1983 to join Atari group developing products for the
typewritten page would have cost Inc. Atari had some very advanced telephone industry. He later headed
over US$200. Today’s semiconduc- research programs in the area of a group that developed products
tor memory is some seven orders computer graphics and home com- for speech recognition.
of magnitude less expensive. Pe- puter applications. However, the He left Intel in early 1983 to be-
ripherals manufacturers have also company lacked the kind of disci- come vice-president for Corporate
made enormous strides in perfor- pline that I took for granted at Intel, Technology of Atari Corp. When Atari
mance and cost ­reductions, so that and when its main source of profit, was sold in mid-1984, he left to be-
today’s personal computer owner video games, took a downturn, Atari come an independent consultant.
can buy a color ­laser printer or a stumbled and was sold by its parent From 1986 on, most of his consult-
500-GB disk drive for a tiny fraction company, Warner Communications, ing was done through Teklicon Inc.
of what the cheapest printer or disk in mid-1984. I left at that time and in Mountain View, California. He be-
drive would have cost in the early became an independent consultant. came an official employee of Teklicon
1970s. For example, at that time From 1986 on, I did my consult- in 1990, as chief technologist. He re-
US$10,000 might have purchased a ing through Teklicon Inc., a small tired from Teklicon in October 2007.
2-MB disk drive. company specializing in provid- He is named as inventor or co-
Today it sometimes appears that ing expertise to attorneys in patent inventor on 17 U.S. patents. He has
the media are aware only of mi- litigation. At first Teklicon acted as published numerous articles on
croprocessors used for personal my agent, but in 1990 I officially be- topics such as adaptive systems,
computers and don’t realize that came Teklicon’s “chief technologist.” memory components and their ap-
embedded control applications uti- I retired from Teklicon in 2007. plication, microprocessors and
lize much larger numbers micro- Two years ago, I was invited to their applications, and telephony-
processors. Embedded controllers judge a collegiate inventors com- related products.
help reduce automobile pollution, petition sponsored by the National He has been recognized many
and they are found in cellular tele- Inventor’s Hall of Fame. One project times for his contribution to the first
phones, digital cameras, and count- that intrigued me involved water microprocessor with awards such
less other devices we do not think of desalination. It seemed to me that as the Stuart Ballantine Medal of the
as computers. Indeed, an embedded the energy budget of most modern Franklin Institute, the Cledo Brunetti
controller, in the form of a cardiac desalination systems is much higher Award and the Centennial Medal of
pacemaker, has helped me remain than would be predicted by the rela- the IEEE, the National Inventors Hall
alive for the last 17 years. tively small differences in the prop- of Fame, the Kyoto Prize, and the Da-
erties of seawater and freshwater. vies Medal for Engineering Achieve-
What Next? I have been recently investigating ment given by Rennselaer Polytech-
Around 1975, at Bob Noyce’s re- this area and believe that it should nic Institute. His contribution has
quest, I started a group that devel- be possible to significantly reduce also been recognized in many books
oped products for the telephone in- the cost of desalinating seawater. about Silicon Valley.

28 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

A confluence of skills
made the microcomputer revolution possible:
device design, process design, applications, and marketing.

by Stanley Mazor

I
n 1960—ten years
before Intel deve­
loped the first sin­
gle-chip CPU (micro­
computer central pro­­
cessing unit) —the revolution that
would ensue was inconceivable: the
cost of computing dropped by a fac­
tor of a million, modes of personal
communication changed forever,
and intelligent machines took over
processes in manufacturing, trans­
portation, medicine—virtually ev­
ery aspect of our lives.
Certainly Moore’s law—that the
number of transistors on a chip dou­
bles every year, later amended to ev­
ery two years—is a dominant factor in
this revolution. But at Intel, there were
three other enabling conditions:
■■ a customer with a problem

■■ an applications engineering de­

partment that listened to the

­customer
■■ a talented engineering group to

implement a solution.
Here I give my views on Moore’s
law and focus on the role of applica­
tions engineering in developing Intel’s
first microcomputer. (For an overview
© artville & photo f/X2 of basic chip technology, see “IC Back­
Digital Object Identifier 10.1109/MSSC.2008.930943 grounder: Process and Design.”)

1943-0582/09/$25©2009IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 29

 State University didn’t let students
I want to tell you about my experiences play games on the campus’s only
with Gordon Moore’s law in Silicon Valley as computer, an IBM 1620 (Figure 1).
“After all,” he said, “it cost almost
an applications engineer using and designing $100k and could execute instruc­
digital computers, digital IC components, and tions in milliseconds. This valuable
microcomputers. resource should neither be wasted
nor made to do frivolous tasks.” Ac­
cordingly, I played my own tic-tac-
Although electrical engineering plications engineer using and design­ toe assembler language program
students study the design of logic and ing digital computers, digital IC com­ only at night, when no one was
circuits, when they graduate, they ponents, and microcomputers [1]. watching; playing games on com­
find a large number of nondesign po­ But first, let me contrast the change puters was not allowed.
sitions posted: quality engineer, pro­ in the value of a computer over a Fifteen years later, I visited
cess engineer, marketing engineer, 15-year period with the following Midway Games, which had been
and applications engineer. But what personal anecdote. acquired by Bally Technologies, a
does an application engineer do? I manufacturer of pinball machines
want to tell you about my experienc­ Computer Values (1962–1977) and slot machines, and coordinated
es with Gordon Moore’s law in Silicon In 1962, Prof. Robert J. Levitt of the development of a custom Intel game
Valley (from 1964 to 1984) as an ap­ Math Department at San Francisco chip for the Magnavox ­Odyssey2

IC Backgrounder: Process and Design

Chip Size and Cost with all-NMOS transistors. After mastering both of these technologies,
Although larger chips can accommodate more functions, a chip’s most semiconductor companies moved into CMOS production (about
manufacturing cost increases with the square of its die size. So the 1985), which required more photomasks and costlier production meth-
chip cost constrains the practical number of transistors that can be ods, but gave a better-performing product.
placed on a chip. But, as Gordon Moore observed in the mid-1960s,
the practical limit doubles every year. Power Dissipation
The early Intel microcomputers (circa 1970) contained about 2,000 CMOS transistor pairs minimize the amount of power consumed in their
transistors, organized into a few logic blocks—ALU, register array, in- steady or quiescent state, and lower operating voltages reduced the active
struction decoder, I/O pads, and so forth. As processing improved over power consumption. The combined effects reduced the power that has
the years, the individual transistor sizes shrank, and at the same time the to be dissipated, thereby permitting more transistors on a chip. Process
chips grew bigger. As transistor features got smaller, the lower capaci- improvements such as ion implantation and polysilicon (rather than metal)
tance helped the circuits run faster. gates lowered transistor threshold voltages and subsequent operating volt-
ages. These processes were pioneered in the United States by: Fairchild,
MOS Process Technology Intel, and Mostek. Operating voltages dropped from 14 V in 1970 to 5 V in
Modern complementary metal-oxide semiconductor (CMOS) ICs 1975, and then to 1.5 V in 2000. Since power varies with the square of the
provide optimum power dissipation and speed, but the manu- voltage, reducing the operating voltage by a factor of 10 reduced power
facturing process is complicated because two different transistor dissipation by a factor of 100. Early ceramic packages could handle about
types are needed within the same chip: NMOS and PMOS, with 1 W of power; plastic packages had a much lower rating.
n-type and p-type substrates, respectively. Standby power is reduced
by pairing transistors, so that at any instant one of the transistors is Circuit Background
turned off. NMOS devices are faster and smaller than PMOS devices A CPU chip is characterized by its maximum clock frequency. A 100-
because the carrier mobility of NMOS is about twice that of PMOS, MHz chip corresponds to a clock cycle period of 10 ns. The clock pe-
but both transistor types are needed within a CMOS chip. riod in digital integrated circuits allows for signal propagation along
For lower manufacturing costs and simpler processing, either all the longest logic switching path within the chip’s circuitry. This path
NMOS or all PMOS ICs are preferred. Early semiconductor companies typically goes from a flip/flop output, passes through a number of logic
such as Electronic Arrays, General Instrument, and Texas Instruments gates, and finally enters another flip/flop.
produced ICs containing only PMOS transistors. NMOS required ex- In typical MOS circuits, each logic gate’s output transistor drives one or
ceptionally clean fabrication facilities, as any impurities tend to perma- more transistor gate input loads. These loads are equivalent to an open cir-
nently turn on NMOS transistors. Only IBM experienced early success cuit (high resistance with some stray capacitance to ground); there is no DC
with NMOS chip production. Early microprocessor chips were made load. The switching speed of such a digital logic circuit depends on the volt-
with only PMOS transistors, but within ten years they were being made age swing to be traversed, for example from .2 V (logic 0) to 4 V (logic 1), and

30 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

home TV game system. This spe­ charge of Fairchild R&D.) I’ve lived tions. Now after 40 years we have
cial video chip was used with an with Moore’s law from its beginning chips with billions (230) of transis­
off-the-shelf single chip microcom­ and have found it both difficult to tors, a daunting result of this kind of
puter to display game objects on a ignore and difficult to grasp. The exponential behavior. We live most­
TV screen. In just 15 years, play­ following story is enlightening: Leg­ ly in a linear world—miles/gallon,
ing games had gone from being a end has it that the man who saved a ­dollars/pound—and we just don’t
frivolous use of computers to a big king’s son’s life was asked what he experience exponential relations
business [2]. Thanks to Moore’s wanted as a reward. The hero asked (except perhaps for acceleration and
doubling, computers became cheap that rice be placed on his checker compound interest) [5], [6].
and new markets (for digital logic) board as follows: one grain on the Did anyone predict that “some­
appeared. (Today, Midway Games first square, two grains on the sec­ day” the whole computer would fit
offers such popular video games ond square, doubling on each suc­ on a single chip? Considering that
as Mortal Kombat, Ms. Pac-Man, Spy cessive square. The king agreed to a minicomputer (circa 1962) CPU
Hunter, Tron, and NBA Jam.) this seemingly modest request, not needed about 16k transistors, and
realizing that the total would be 16k = 214, one could have predicted
Moore’s Law (1965) more rice than there are grains of a single-chip CPU after 14 years of
I joined Fairchild Semiconductor in sand on the beach. Moore’s doubling, or roughly in 1976.
Mountain View, California, before Similarly the significance of However there weren’t any such pre­
Gordon Moore published his de­ Moore’s doubling of transistors each dictions! Apparently Moore’s law is
finitive paper [3], [4]. (Moore was in year is outside our normal expecta­ easier to apply in hindsight than in

the speed of the voltage transition. This switching speed (dv/dt) is directly •• lowering the voltage swing needed to switch a logic signal
proportional to the current output (I) of the driving transistor and inversely •• reducing the transistor size to improve a driver’s output current
proportional to the capacitance (C)of the driven transistor gates and the •• reducing the transistor size to lower the gate’s capacitance.

interconnection wiring, as given by the formula dv/dt = I/C.

The output current of an MOS driver transistor sets the switching RAM Circuits
speed, and depends on circuit layout and process features. The voltage In 1970 an IC could contain about 256 bits of static RAM, the limit be-
on the gate and the transistor’s size are the most important circuit de- ing imposed by both power dissipation and chip size. Dynamic RAM
sign features, determining an output transistor’s drive strength and the (DRAM) chips became practical in the early 1970s and had much low-
ultimate circuit’s speed. With silicon (rather than metal) gate the tran- er power requirements, but needed to be refreshed periodically. The
sistor’s size was reduced because the source and drain features were three-transistor dynamic memory cell was considerably smaller than a
formed by the self-aligned ­silicon gate [31]. six-transistor static memory cell.
Although today’s circuits utilize two transistor types for optimum In addition, the cell connection signals were a major area constraint.
drive for both rising and falling signals, that is, transition from logical Memory circuit design was often described in terms of the number of con-
0 to 1 and from 1 to 0, earlier circuits weren’t good at both “pushing necting bus lines, for example, a three-line or six-line organization. Larger
and pulling.” Accordingly, the circuits were operated in dynamic mode DRAM memory chips were made possible by using a single transistor per
with a precharge and conditional discharge circuit. First a circuit was cell and just two lines—gate s­ election and bidirectional data bus.
precharged by an on-chip amplifier, and then, according to the logic Early microcomputer chips used small, integrated dynamic RAM arrays for
state, was conditionally discharged. the CPU’s registers and a program counter stack. For example, Intel’s 4004
The PMOS transistors of 1970 required 14 V to operate; the circuits had a 64-b DRAM for its 16 four-bit registers, and the 8008 had a push-
were operated dynamically in either a two-phase or a four-phase mode. down stack of 14 3 8 within a DRAM array. The decisions to be made in
The historic improvements in MOS process technology have resulted in designing ICs—then and now—are many. Table 1 highlights some of them.

Table 1. LSI Chip Issues.

LSI Chip Issues:

■ How many pins on the IC package? ■ What are the operating voltages? ■ What chip speed and power goals?
■ What is IC package’s power dissipation ■ What are the I/O interface voltages and ■ What is the on-chip routing/bus
constraint? signal timings? strategy?
■ What is the projected die size and aspect ■ What are the technology constraints? ■ How will the chip be tested?
ratio?

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 31

 sense, that is, can you use more
You will see that our early experience with transistors sensibly?
If Moore’s law is taken into ac­
small computers was a factor in creating the
count, there are more choices to con­
first microcomputer. sider, as Table 2 shows. First, for an
existing product, one needs to know
foresight. This despite the fact that $1.25. After a while everyone would the results of lowering the price. Of­
we announced the MCS-4 chip at In­ own several and the market would ten new applications and new mar­
tel in 1971, roughly five years “ahead become saturated; this wouldn’t be kets are needed to propel the sales
of schedule”; the CPU had about 2k a good business. Sometimes lower­ volume of an existing IC chip.
transistors [7], [8]. ing prices increases market con­ For new chip designs, it is a chal­
Generally, if you can double a sumption and sometimes not. Ac­ lenge to determine what kind of chip
chip’s density next year, you have cordingly, although many believe to make. Table 1 illustrates the op­
two choices: Moore’s law is about semiconduc­ tions for new chips for both existing
■■ halve the cost of a chip you’re tor technology, thoughtful analysis and new markets. Deciding on how
currently making reveals two fundamental business to use more transistors requires
■■ make a new chip with twice as questions: Will decreasing chip pric­ a good understanding of how new
much “stuff” on it. es dramatically increase chip sales? chips would be used—their applica-
By way of analogy, suppose you Will the expected profits justify im­ tion. The role of both the applica­
were a bicycle manufacturer that proving semiconductor processes? tions engineer and the product mar­
could reduce bicycle prices every In other words, Moore’s doubling oc­ keting engineer become prominent
year by 50%: $80, $40, $20, . . . curs only if it makes good business in new chip specification—how big,
how fast, what features, how many
will sell, what price?
Let me continue now with my per­
sonal story after I joined Fairchild.

Transistor Data (1964)

One of my application engineering
projects at Fairchild was to write
a program to calculate the Y-pa­
rameters of individual, or discrete,
transistors. At that time each three-
legged transistor had a serial num­
ber, and we recorded and calculat­
ed parameters for each part. When
users paid US$150 per transistor,
arguably they paid more for the
data than for the transistor itself.
Fairchild applications engineers
were selling their service bundled
with the devices.
Figure 1: Stan Mazor and an IBM 1620 in 1963. When transistor prices dropped
by a thousand times (to US15¢ each),
the price of a five-transistor radio
Table 2. LSI chip marketing issues. dropped to about US$2. At some
point the solid-state devices weren’t
Lower the price of existing chips. a factor in a radio’s price; the costs
Find new uses for existing chips. of the case, power supply, battery,
coils, capacitors, and resistors
Build a similar chip with improved features.
­outweighed transistor costs. Soon
Build a noncompatible chip with improved features.
everyone owned a couple of these
Develop a new chip design for an existing chip market. radios, and the market for radios
Develop a new chip to replace another technology—mechanical, magnetic, analog, other. saturated. Chips containing more
Develop a new chip for a totally new market. transistors and their wiring—that
is, integrated circuits—would be

32 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

the key to fueling Moore’s law and
lead to lower digital system costs.

Novel Computer Architecture (1966)

At Fairchild I programmed six differ­
ent computers, and in 1966 I trans­
ferred to Gordon Moore’s R&D labs
in Palo Alto, joining Rex Rice’s high-
level language computer ­design proj­
ect. Following Moore’s predictions
for “cheap” logic, we built a radical
computer called Symbol (Figure 2)
that had 100 times more logic with­
in the CPU. It used more than 20,000
of Fairchild’s complementary tran­
sistor logic (CTL) chips. However
the idea of “maximizing” CPU logic,
while consistent with Moore’s law,
was flawed and the project wasn’t a
success [9], [10].
However, my experience in de­ Figure 2: Experimental Fairchild symbol computer, circa 1968, shown with its developers in
the rear and, in the foreground, two attendants at Fairchild’s introduction.
signing the serial decimal floating
point arithmetic logic unit (ALU) and
the string-processing unit would Shift Register ICs (1969) out just ­repeats the memory cells,
later help me in understanding the If you look at history you’ll find thousands (or millions) of times.
Busicom calculator’s arithmetic, that shift registers were one of the ■■ On-chip wiring is minimal, since

with Intel’s first microcomputer [1]. first large-scale integration (LSI) each cell communicates with just
chips available, and from several its left and right neighbors.
Intel Is Founded (1968) companies—including: General In­ Finding new uses for shift reg­
Robert Noyce and Gordon Moore strument, Electronic Arrays, MOS ister chips was a challenge for the
quit Fairchild, where they were Technology, AMI, and Intel. Although Applications Engineering depart­
general manager and director of dynamic random-access memories ment. We built a few interesting
R&D, respectively, and started (DRAMs) are now common, the shift systems such as a moving sign­
Intel to capitalize on the emerg­ register was a precursor memory board using shift register chips.
ing semiconductor memory mar­ chip and had several advantages. A Realizing that some of the early
ket and fulfill Moore’s promise shift register chip has few leads and computers used serial disk memo­
of growing chip density [11]. My can be encased in a small eight-pin ries for the main program memory,
Fairchild officemate, Jim Angel, package (the TO-5 can). we proposed using shift registers
suggested they hire a brilliant Keep in mind that, although chip for main memory. However, a prin­
Stanford research associate, M.E. density had been doubling, the number cipal use of shift registers turned
(Ted) Hoff, as director of applica­ of input and output pins on a package out to be video screen refresh cir­
tions research. I joined Hoff at In­ was growing slower, so I/O pin count cuits, since video is a bit-serial ap­
tel in 1969 as an applications engi­ was a real limitation to a chip designer. plication [12], [23].
neer. (I recall first meeting Hoff in Normally chip wiring is a major prob­
1963 while he was demonstrating lem for designers—one that eats up Minicomputer Market (1965–1969)
his experiments in speech recog­ valuable chip real estate. But not in a DEC’s 12-b PDP-8 and Data Gener­
nition on an IBM 1620 at Stanford shift register, for three reasons: al’s 16-b Nova popularized the gen­
University. At that time I was also ■■ Serial memories have no address eral-purpose minicomputer. A few
programming an IBM 1620 on more pins, just the data-in, data-out, and
mundane applications.) clock and power pins—regardless
You will see later that our early of the number of bits inside the Power Clock
experience with small computers chip, as shown in Figure 3.
was a factor in creating the first mi­ ■■ Shift register chips are simpler to Data In Data Out
Shift Register
crocomputer. But let’s consider the design and debug because they
first kinds of memory chips that have no address decoder in the
were enabled by Moore’s law. chip, and most of the circuit lay­ Figure 3: Shift register block diagram.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 33

 at Intel. My job was to design and
In just 15 years, playing games had gone demonstrate a CPU using this UAE
from being a frivolous use of computers to with Intel ROMs and RAMs. We de­
cided to emulate the 12-b DEC PDP-8
a big business. minicomputer, which was a popular
standard. To make it interesting, my
coworkers and I fit the entire CPU
years later, many other vendors of­ in the early 1960s, many manu­ on a small 36-chip board (Figure 4),
fered comparable minicomputers facturers produced TTL logic in and we used ROM microcode to de­
for under US$10,000. There were a 14-pin dual in-line packages— fine an instruction set similar to the
variety of minicomputers featuring Texas Instruments, National Semi­ PDP-8’s. We presented the results of
12–18-b words for both data and conductor, Sylvania, and others. this experiment at the Northeast Re­
instructions, and they came with These sold for about US25¢ each gional Electronics Meeting (NEREM)
4K words of core memory. These on average, and the cost of a three- in 1970 [15]. Intel considered the
minicomputer CPUs were built with input NAND gate was less than a UAE experiment as a demonstration
bipolar transistor-transistor logic dime. The plentiful availability of “miniaturization” and did not
(TTL) gates and a few medium- and low cost of these ICs made pursue the UAE as a product.
scale integration (MSI) ICs. These possible digital systems in general
MSI parts were typically 4-b wide— and minicomputers in particular. DRAM Versus Core Memory (1972)
multiplexers, adders, shifters, and Moore’s law was at work; the lower A general-purpose computer can’t
so forth. costs of ICs opened up a vast mini­ do much until a program is load­
While the new metal-oxide semi­ computer market [13], [14]. ed into its memory. The magnetic
conductor (MOS) circuits offered cores used in memories in 1972
ten times the density of TTL cir­ Universal Arithmetic Element (1970) could hold a program with power
cuits, their slow speed made them Given the popularity of 4-b-wide absent. When Intel promoted semi­
unacceptable for CPU logic circuits. MSI parts, one of Intel’s first prod­ conductor DRAM as a replacement
And even though MOS chips cost ucts was a 16 3 4 high-speed bipo­ for core memory, an oft-heard com­
less than TTL, when you added the lar memory chip. It could be used to plaint was that DRAM would lose
cost of main memory and periph­ provide data registers within a CPU. data if the power was off, and this
erals, the cost savings would not Intel’s bipolar read-only memory was true. However, in reality not
be significant. (ROM) could hold the microcode for many computers relied on this fea­
Moving from diode-transistor the CPU’s logic. ture, and it was common practice to
logic (DTL) and resistor-transistor Hoff also began developing a 4-b load/reload a program just before
logic (RTL) logic that was popular universal arithmetic element (UAE) executing it. Arguments from In­
tel applications engineers familiar
with actual customer use overcame
this criticism of DRAMs; we did suc­
ceed in getting computer designers
to switch from magnetic core to
DRAM chips. It’s been said that Intel
created the RAM business in 1972,
and Intel was indeed a major DRAM
chip supplier, but that success was
a result of a combination of chip
engineering and applications engi­
neering support [11].

DRAM Improvements (1972)

Historically, doubling RAM chip
bits according to Moore’s doubling
of the transistor count was a good
fit—larger RAMs were both natural
and needed. Furthermore, only one
additional address input lead was
needed on the chip’s package—
Figure 4: Intel’s experimental 12-b CPU using universal arithmetic element chips. and, as I noted earlier, I/O pins are

34 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

a severe limitation in chip design.
With minor redesigns, customer
memory boards were upgraded to When Intel successfully produced the first
use newer and larger DRAM chips, DRAM chips, commercial viability was
and customers readily accepted
slow to come.
these improved chips [16].

Content-Addressable
Memory—A Failure (1974) US$1,000. Again, low prices led to play, and printer. Hoff proposed a
After an address is input into a large sales volumes. simpler approach substituting pro­
RAM, the contents are returned. Because a desk calculator responds gramming for hardware, and I as­
In a content-addressable memory to keystrokes, not stored programs as sisted in this design. Table 3 lists
(CAM) it’s just the opposite. Data in minicomputers, it was a fine match some of the key design decisions on
for matching are entered, and if a for the speed, density, and cost of this project [19].
match is found within the CAM, the MOS LSI. Japan’s Busicom promised Shima and I shared an office;
location is output. CAMs are much the substantial sales volume that Intel I was the principal liaison on the
faster than searching RAMs, but needed if we could design and build project. Because he had done quite
they require additional circuitry custom MOS LSI chips for their new a bit of work on his design, he was
that increases the physical size desktop calculator [18]. skeptical of Intel’s alternative pro­
of the CAM chip, which in turn in­ Hoff was evaluating Busicom’s posal. I needed to demonstrate how
creases manufacturing cost. design when I joined him at Intel in we could achieve various calcula­
We believed CAMs would be useful 1969. Busicom’s Masatoshi Shima tor features by programming rath­
in CPU memory page tables (virtual had designed the overall logic for er than in hardware. Moreover, all
memory). Applications engineering his calculator’s custom chip set. of his flowcharts for floating-point
promoted this product, but regretta­ His design called for a processor arithmetic assumed multidigit
bly no large-scale market appeared that operated on multidigit decimal fixed-point numbers, but our CPU
after the chip materialized—an ap­ numbers, a ROM for coding float­ operated on only a single digit. I
plications engineering failure. ing-point operations, and separate needed to make the CPU look more
Today, CAMs are only used in control chips for the keyboard, dis­ like Shima’s original and show him
specialized applications where ad­
equate searching speed cannot be
Table 3. Key design decisions for the Busicom chip set.
achieved with a less costly method.
Busicom/Masatoshi Shima:
A Memory Market Pitfall—    Family of systems using the same custom components
And a Solution (1969)
   Serial decimal floating point arithmetic via a ROM program
When Intel successfully produced
the first DRAM chips, commercial Intel/Ted Hoff:
viability was slow to come. Although    4-b architecture
customers would buy samples,    Separate program ROM and data RAM chips
their lead time from engineering to
   Time multiplex 4-b bus; 16-pin IC packages
manufacturing meant that volume
   Dynamic RAM for CPU registers and PC stack
production orders wouldn’t be re­
alized for several years. Meanwhile    4-b I/O ports (RAM and ROM chips) for interfacing
Intel’s own production line would    ROM program: keyboard, printer, lights
be idle. Intel needed a way to utilize Intel/Stan Mazor:
its factory with a shorter lead-time
   FIN/JIN instructions to Fetch/Indirect jump within ROM
product [17].
The Busicom desktop calcula­    Pseudo-code interpreter to reduce ROM code size
tor provided a way to keep idle    4004 assembler and ROM code bit mapper
production lines busy. While    Code snippets for calculator functions
minicomputer unit sales were Intel/Federico Faggin:
only in the low thousands at the
   Custom chip methodology, circuits, layout
time, desktop calculators were
selling by the hundreds of thou­    Bootstrap amplifier circuit for silicon gate process
sands. Using a handful of MOS    Checking and debugging custom IC chips
LSI chips, they sold for less than

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 35

 Program.Ctr 0 1
CPU 4004  2 3
 ADDR STACK 4 5
 6 7
8 9
Instruction Reg. 10 11
12 13
OPR OPA 14 15
Registers
Test
Control
Arithmetic
RAM Control Lines ROM Control Line
Command CY ACC
Line Control
SYNC SYNC

Data Bus

Addr. Reg. Addr. Reg.

Control Control

ROM Array
256 × 8

Status Main Memory

Port Logic Port Logic

RAM 4002 ROM 4001

Output Port Input/Output
Port

Figure 5: Block Diagram of the Busicom chip set (MCS-4).

how the features he needed could This also reduced the amount of ­became a standard product, MCS-4
be provided. ROM needed by replacing 2-byte [20]–[22].
Using my college programming instructions with 1-byte pseudo Busicom produced several dif­
experience with virtual machines, operations. To interpret Shima’s ferent calculators using this fam­
I made Intel’s system look more “pseudo-instructions,” we added ily of parts. However, in just a few
like Shima’s original. An inter­ two CPU instructions—the ability years the growing density of LSI
preter program, occupying less to fetch data from ROM (fetch indi­ made the products obsolete. Busi­
than 20 bytes, was the solution. rect) and to jump to a subroutine com was ultimately beaten by com­
(jump indirect). I wrote program­ petition that used more dense and
ming snippets, to operate on a less general chips.
field of digits, and also wrote pro­
gram pieces for scanning the key­ MCS-8 (1972)
board, displaying data in lights, In 1969, Intel built custom shift
and running the printer. register chips for Control Terminal
In the end, Shima did all the cal­ Corporation’s (CTC’s) Datapoint dis­
culator design and coding of four play terminals. (The company later
ROM chips for the Busicom calcu­ changed its name to Datapoint Cor­
lator. The interpreter directed the poration.) CTC asked me for a “stack
program to the correct subroutines. chip” for use in their new 8-b CPU,
Hoff’s architecture was proven and unaware of our Busicom microcom­
provided a general-purpose solu­ puter project. Although a single-chip
tion (Figure 5). Federico Faggin did CPU like the MCS-4 was “conceiv­
all the chip design, circuit design, able,” few knew how to do it practi­
Figure 6: An 8008 die with designer Hal and layout, resulting in a new mi­ cally. There were limits on the size
Feeney’s initials. crocomputer chip set that later of chip that could be built and the

36 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

amount of circuitry we could put on dependent on the data word size, so the 8008. This led to the 8080 and
a chip. Hoff and I discussed the pos­ instruction decoding logic in an 8-b the 8086—the CPUs that launched
sibility of building the Datapoint CPU CPU doesn’t require much more cir­ the PC business [23]–[30].
as a single chip. At first the amount cuitry than that for a 4-b CPU—and
of logic circuitry required for an 8-b we knew a 4-b CPU was feasible. See In Retrospect
CPU seemed prohibitive, with twice the photo of the 8008 chip in Figure Moore’s law of doubling density
as many transistors as a 4-b CPU. 6 and designer Hal Feeney’s signage. unquestionably affects everyone’s
But in a CPU, the logic for instruc­ Subsequently, we proposed the first life, with ubiquitous cell phones,
tion decoding and execution is not 8-b CPU chip, announced in 1972 as ­personal computers, ATMs, and

From Programming to Photolitho­graphy: A Professional Odyssey

As Ted Hoff and I were computer users as well as computer designers, p­ hase-shift masking, which made 20-nm geometries feasible—and
we organized and managed digital computers at Intel. One of our major helped continue Moore’s law.
accomplishments was providing computer-aided design (CAD) tools to
assist chip designers—including logic simulation and circuit simulation Smaller Focus
tools (transient analysis). I wrote and maintained the production version It’s amusing that, although I started as a computer programmer, I moved
of our home-grown (pre-Spice) circuit analysis program, using Hoff’s cir- into logic design, then circuit design, layout, and finally photolithogra-
cuit simulation strategy and Dov Frohman’s transistor model. I constantly phy. While the focus of my work continued to grow “smaller,” most of
revised my program to handle larger circuits and the ever-changing tech- my concerns were with automation tools and techniques to give design-
nology on our DEC PDP-10 large-scale, time-shared computers. This was ers more power and flexibility in doing their designs—for logic, circuits,
a nice way for me to learn some semiconductor physics and observe cir- layout, and photomasks.
cuit phenomena. At Fairchild, I had done extensive logic simulation on Since I “retired,” I’ve written two books: one on using high-level design
my floating-point arithmetic unit, and there is a fine difference between methodologies in home construction (Design an Expandable House)
functional logic simulation and lower-level circuit simulation. and the other on using statistical techniques in the stock market (Stock
In 1974 I transferred to Belgium to become Intel’s first field applica- Market Gambling) [35], [36]. Each year I visit two colleges and share
tions engineer in Europe, and to develop new markets in new places. I some of my engineering experiences, and I’m active in writing short
found many exciting applications for our microcomputers in a variety history articles about the early microcomputer days [37]. Every year I
of companies and industries. When I returned to the United States in help to organize the invitational Asilomar Microcomputer Workshop. I
1976 I worked extensively on microcomputer programming, writing, invite interested readers to contact me at [email protected] with
lecturing, and teaching on the subject. In fact Intel trained tens of thou- comments or questions.
sands of engineers using the Intel Development System (Figure 7), in
which I participated.

A Higher Level of Abstraction

In 1983, I left Intel to join a start-up, Silicon Compilers, realizing that
the real potential of very large scale integration (VLSI) could be reached
only by designing at a higher level of abstraction [32]. After five years I
abandoned that work to join CAD start-up, Synopsys, working in logic
synthesis. I had found that, although the compilation ideas weren’t ef-
fective, logic synthesis from a hardware description language was
practical. At Synopsys I managed a capable team of application engi-
neers and trainers for more than five years. I continued my writing and
teaching about these new methodologies and published a popular book
on VHDL, the design language for field-programmable gate arrays and
application-specific integrated circuits [33].
Staying in the CAD field, I worked at Cadabra, where we automatically
generated standard cell layouts from transistor netlists. Again, the ever-
changing technology meant reducing the time delay in developing an IC
layout. Standard cells were a good meeting place for the logic designer
and circuit and layout designer.
Later I joined Numerical Technologies to help overcome the 250-
nm limit on optical photomask resolution [34]. Our solution involved Figure 7: Intel development system.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 37

 [27] G. Bylinsky, “Here comes the second com­
Since I “retired,” I’ve written two books: one puter revolution,” Fortune, Nov. 1975.
[28] S. Mazor, “Intel 8080 CPU chip develop­
on using high-level design methodologies ment,” IEEE Ann. History Computing, vol.
29, pp. 70–73, April–June 2007.
in home construction and the other on using [29] F. Faggin, M. Shima, and S. Mazor, “Single
chip CPU,” U.S. Patent 4,010,499, Intel
statistical techniques in the stock market. Corp., 1977.
[30] S. Morse, B. Ravenel, S. Mazor and W.
Pohlman, “Intel microprocessors 8008 to
8086,” Computer, pp. 42–60, Oct. 1980.
[31] L. Vasdasz, A. Grove, G. Moore, and T.
Rowe, “Silicon gate technology,” IEEE Spec-
trum, pp. 27–35, Oct. 1969.
i­nvisible, ­embedded computers Video book available at www.dadgum.
[32] S. Mazor and L. Jack, “The validation of
providing smarter machines every­ com/halcyon/.
silicon compiler technology on a VHSIC
[3] G. E. Moore, “Cramming more compo­
process,” in GOMACTech Digest, Nov.
where. That Intel was a memory com­ nents onto integrated circuits,” Electron-
1986, pp. 437–441.
pany certainly influenced our ability ics, pp. 114–117, Apr. 19, 1965.
[33] S. Mazor and P. Langstraat, A Guide to
[4] “The technical impact of Moore’s law,”
VHDL, 2nd ed. Norwell, MA: Kluwer, 1993.
to make CPUs, and microcomputers IEEE Solid-States Circuits Society Newslet-
[34] L. Karklin, S. Mazor, et al., “Subwavelength
helped Intel sell main memory chips ter, vol. 20, Sept. 2006.
lithography: An impact of photomask er­
[5] F. G. Heath, “Large scale integration in
rors on circuit performance,” Proc. SPIE,
(DRAM, EPROM, ROM). electronics,” Sci. Amer., p. 22, Feb. 1970.
pp. 259–267, July 2002.
This success was made possible [6] P. E. Haggerty, “Integrated electronics—A
[35] S. Mazor, Design an Expandable House,
perspective,” Proc. IEEE, pp. 1400–1405,
2nd ed. Morrisville, NC: Unlimited Pub­
by intertwined efforts. Developing Dec. 1964.
lishing, Lulu, 2003.
new standard chips requires close [7] “MCS-4 micro computer set,” Data Sheet
[36] S. Mazor, Stock Market Gambling: Turn-
7144, Intel Corp., 1971.
ing on a Dime. Morrisville, NC: Unlimited
cooperation among applications [8] Intel advertisement, Electronic News, Nov.
Publishing, Lulu, 2007.
and marketing engineers who in­ 1971.
[37] S. Mazor, “Programming and/or logic de­
[9] L. C. Hobbs, “Effects of large arrays on
sign,” in Proc. IEEE Computer Group Conf.,
terpret users’ needs, as well as machine organization and hardware/
1968, pp. 69–71.
clever ­process and chip designers software tradeoffs,” in Proc. 1966 Fall
[38] B.O. Evans, “System/360: A retrospective
Joint Computer Conf., vol. 29, p. 89.
view,” Ann. History Computing, vol. 8, no
who implement new technology. [10] S. Mazor, “Fairchild Symbol Computer,”
2, pp. 155–179, 1986.
The development of businesses IEEE Ann. History Comput., vol. 30, pp.
[39] M. Wilkes, “The genesis of microprogram­
92–95, Jan.–Mar. 2008.
ming,” Ann. History Computing, vol. 8, no.
at Intel relied on applications en­ [11] G. Bylinsky, “Little chips invade the memory
2, pp. 115–126, 1986.
gineers to define new products as market,” Fortune, pp. 100–104, Apr. 1971.
[12] M. Hoff and S. Mazor, “Operation and
well as skilled design engineers. application of shift registers,” Computer
Hoff and Mazor’s early experiences Design, pp. 57–62, Feb. 1971. About the Author
[13] D. C. Hitt et al., “The mini-computer—A
with computers and programming, new approach to computer design,” in Stanley Mazor (stanmazor@sbc­
and Shima’s and Faggin’s design Proc. IEEE 1968 Fall Joint Comp. Conf, pp. global.net) worked on early micro­
655–662.
background were key to the cre­ [14] R. Hooper, “The minicomputer, a pro­ processor chips at Intel and shares
ation of the microcomputer at Intel gramming challenge,” in Proc. 1968 Fall patents on the 4004 and 8080 mi­
Joint Comp. Conf., pp. 649–654.
during the early 1970s. I was very [15] M. Hoff and S. Mazor, “Standard LSI for crocomputer chips. Previously he
lucky to be working with these tal­ a micro programmed processor,” in worked on the design of Symbol,
IEEE NEREM ’70 Record, Nov. 1970, pp.
ented coworkers and to participate 92–93. a high-level language computer at
in a great team. Although Moore’s [16] J. Karp, A. Regitz, and S. Chou, “A 4096- Fairchild R&D (1964). He has worked
bit dynamic MOS RAM,” in Proc. Int. Solid-
curve is aggressive, the first mi­ State Circ. Conf., Feb. 1972, pp. 10–11. in several start-up companies includ­
crocomputer was “slightly ahead [17] R. Noyce and M. Hoff, “A history of mi­ ing: Intel, Synopsys, Silicon Compil­
croprocessor development at Intel,” IEEE
of the curve.” Micro, vol. 1, no.1, pp. 8–21, 1981. ers, Numerical Technologies, Ca­
Incidentally, my career didn’t [18] M. Shima, The Birth of the Microcomputer: dabra, and BEA Systems. He studied
My Recollections. Tokyo: Iwanami Shoten,
end when I left Intel—far from it. 1987 (in Japanese). mathematics at San Francisco State
I continued to work on microcom­ [19] M. E. Hoff, S. Mazor, and F. Faggin, “Memory College. He has published 55 articles
system for a multi·chip digital computer,”
puters, albeit in diverse ways, and U.S. Patent 3,821,715, Intel Corp., June 1974. relating to large-scale integration
I continued to see Moore’s law in [20] F. Faggin et al., “The MCS-4—An LSI micro chips and three books including A
computer system,” in Proc. IEEE Region 6
operation (see “From Programming Conf., 1972, pp. 8–11. Guide to VHDL (Kluwer, 1993). For his
to Photolithography: A Profession­ [21] H. Smith, “Impact of LSI on microcomput­ work on Intel’s microcomputers he
er and calculator chips,” in IEEE NEREM ’72
al Odyssey”). Rec., 1972. was awarded the Kyoto Prize, the Ron
[22] S. Mazor, “Micro to mainframe,” IEEE Ann. Brown American Innovator Award,
History Computing, vol. 27, pp. 82–84,
April–June 2005. and the Semiconductor Industry As­
References [23] S. Mazor, “8-bits of Irony,” IEEE Ann. His- sociation Robert Noyce Award and
[1] S. Mazor, “The history of the microcom­ tory Computing, vol. 28, pp. 73–76, April–
puter,” in Readings in Computer Archi- June 2006. was inducted into the Inventors’ Hall
tecture, M. Hill, N. Jouppi, and G. Sohi, [24] Intel MCS-8 User Manual, 1972.
Eds. San Francisco, CA: Morgan Kaufman,
of Fame. His hobby is architecture,
[25] V. Pzoor, “Letters,” Fortune, p. 94, Jan.
2000, p 60. Reprinted from Proc. IEEE, vol. 1976. and he recently published Design an
83, pp. 1601–1608, Dec. 1995. [26] G. Boone, “Computing system CPU,” U.S.
[2] “Halycon days: Interviews with classic
Expandable House as well as Stock
Patent 3,757,306, Texas Instruments,
computer and video game programmers.” Sept. 1973. Market Gambling.

38 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 by Masatoshi Shima

© artville & photo f/x2

Developing the world’s first microprocessor.

T
his article is a recollection of the development of the world’s first micro-
processor, the 4004, as seen from Busicom Corp., the Japanese desktop
calculator manufacturer where I was working from the late 1960s to the
early 1970s. In 1969, Busicom Corp. launched a project to develop LSI chips
for a ROM-based, macroinstruction-programmable decimal computer sys-
tem. At that time, Busicom was a successful Japanese manufacturer of electronic calculators
with a reputation for innovation. Through the LSI project, Busicom and Intel Corporation
succeeded in March 1971 in developing the world’s first 4-b microprocessor, the 4004, a
product that was conceptually the exclusive property of Busicom.
I worked at Busicom from the late 1960s to the early 1970s to develop the 4004. In this
article, I recall my role throughout the development process, including:
■■ the development of a printing desktop calculator using ROM-based programmed-logic that

led to the birth of the 4004

Digital Object Identifier 10.1109/MSSC.2008.930946

1943-0582/09/$25©2009IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 39

 ing on decimal and binary data, an
accumulator, a keyboard input reg-
We designed the logic at the transistor level ister, a multiplication and division
instead of the gate level so that it could be register; control registers (compris-
ing counter, decimal point register,
used for both the circuit and the layout designs. and flag status register), a timing
module; and data memory.
The control unit consisted of an
■■ clarifying problems with the bi- addition of new system functions in 8-b program counter with an address
nary processor proposed by Intel a short period of time. incrementer, a ROM for storing the
■■ optimizing the 4004 system con- program, an 8-b instruction register,
figuration and its instruction set Moving to ROM-Based an instruction decoder, and an in-
■■ designing the logic of the 4004 Programmed-Logic struction execution control module.
CPU In 1968 at Busicom, I developed a The instruction set included 23 in-
■■ developing the 4004-based print- ­printing desktop calculator with a structions for operations such as data
ing desktop calculator. ROM-based, macroinstruction pro- transfer, data exchange, load immedi-
The first transistor desktop cal- grammable decimal computer archi- ate, clear, addition and subtraction of
culator had been developed in Japan tecture. Like a computer, the calculator decimal data, shift, addition and sub-
a few years earlier, in 1964. It was consisted of: traction of binary data, increment and
quickly put into commercial pro- ■■ input-output (I/O) devices com­ decrement, flag control, uncondition-
duction, leading to a rapid growth prising a keyboard, a display, and al jump, conditional jump, and print.
in the calculator market and making a printer The program size was less than 256
Japan a major manufacturer of cal- ■■ a processor for data processing B. The I/O device control was imple-
culators. At that time, desktop cal- ■■ ROM for program memory mented in wired logic.
culators still used wired logic. For ■■ data memory.

calculator technology to proceed, Figure 1 shows a block diagram LSI Enters the Scene
however, a new approach to logic of the CPU in this calculator. The In 1969, Busicom started develop-
design was needed—one that would CPU was multichip; its data path ment of LSI chips for a decimal com-
allow the design, modification, and consisted of a 4-b serial ALU operat- puter system. First of all, the number

PROGRAM Unit ALU & Register Unit

(Control) (Data Path)

Keyboard System Bus (2 b)

Data Reg.& Memory Reg. Control Reg. Sign
Keyboard Accumulator Shift-Out B:
Code Conversion M
X Register (64 b) u SR Reg. (4 b) XS
l
Input Register t Counter
Program Counter Y Register (64 b) i YS
CR Reg. (4 b)
with Address p
Mul-Div Register l Decimal Point
Incrementer
Z Register (64 b) e DPX Reg. (5 b)
x
Data Memory e Decimal Point
ROM (256 Bytes) DPY Reg. (5 b) MS
M Register (64 b) r

Flag
Multiplexer First Adder Temporary Register Secondly Adder B:
Full AR Reg. (4 b) Full F1
Adder Adder
Instruction Register
(1 b) Decimal Adjust (1 b) F2
Micro Order
Carry Carry
Instruction Decoder
TIMING B Digit

Instruction OSC (400 KHz) ÷2 ÷4 ÷ 16

Execution Control

Figure 1: Block diagram of the CPU of a ROM-based, macroinstruction programmable desktop calculator.

40 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 JUMP Instruction Address Transfer Instruction
JUN A1A2A3 Jump Direct SRC PRn Send Address Pointer PRn to RAM & ROM
JCN CC A1A2 Jump Conditional DCL Designate Commnand Line
JIN PRn Jump Indirect Acc → Command Register ; RAM select
ISZ Rn,A1A2 Increment Rn and Jump if not Zero Arithmetic & Login Instruction
JMS A1A2A3 Jump to Subroutine
BBL d Return from Subroutine & d → Acc ADD Rn Add Rn to Accumulator with Carry
ADM Add RAM Character Acc. with Carry
Data Transfer Instruction SUB Rn Substract Rn from Acc. with Borrow
LD Rn Load Rn to Acc. SBM Substract RAM Character from Acc. with Borrow
XCD Rn Exchange Rn and Acc. INC Rn Increment Rn
STO Rn Store Acc to Rn IAC Increment Acc.
LDM d Load Immediation to Acc DAC Decrement Acc.
FIM PRn, dd Load Immediation to PRn RAR Rotate Right Acc. with Carry
FIN PRn Fetch Immediate from [PRo] to PRn RAL Rotate Left Acc. with Carry
RDM Read RAM Character to Acc SHR Shift Right Acc.
RD[0:3] Read RAM Status[0:3] to Acc. SHL Shift Left Acc.
RDSGN Read RAM Reg.Sign to Acc. CLA Clear Acc.
RDDP Read RAM Reg.DP to Acc. CLB Clear Both Acc. and Carry
RDR Read ROM Input Port to Acc. CMA Complement Acc.
WRM Write Acc. to RAM Character STC Set Carry
WR[0:3] Write Acc. to RAM Status[0:3] CLC Clear Carry
WRSGN Write Acc. to RAM Reg.Sign CMC Complement Carry
WRDP Write Acc. to RAM Reg.DP TCC Transmit Carry to Acc. then Clear Carry
WRR Write Acc. to ROM Output Port DAA Decimal Adjustment for Add
WMP Write Acc. to ROM Output Port TCS Substract Carry from Acc.
CLDR Clear All of RAM and RAM Reg. KBP Keyboard Process for Code Conversion
DSPON Display Output is Enabled NOP No Operation
DSPOFF Display Output is Disabled HLT n HALT for External Signals
RDKB Read Input Data on Keyboard Port

Black Character: Instruction Proposed by Intel Green Character: Instruction Proposed by Intel but Later Deleted
Blue Character: Jointly Defined Instruction Red Character: Instruction Proposed by Busicom Strongly

Figure 2: History of the 4004 instruction set.

of control registers was increased reasons, Busicom did not disclose to Takayama, I visited Intel in Califor-
to eight; these registers were collec- Intel its plans to use the chips in ap- nia in June 1969 to work together
tively called the “index register.” The plications other than calculators. on the development of the LSI. At
instruction set was improved, and With two other project mem- that time, Intel was a small semi-
subroutine jump and processor stop bers, Hiroyuki Masuda and Shogo conductor company specializing
instructions were added. in memory chips. Without logic
Busicom planned to develop designers, they did not have a
seven different types of LSI chips, Decoding the Acronyms clear picture of the logic used in
one each for the program control, Many of the acronyms in this article are so familiar our calculators and responded
the arithmetic unit, the ROM for they hardly need definitions. But, for the record, here negatively to our proposal for
program, the shift register for is a complete list of terms with their meanings. developing a family of various
data, the timing circuit, the print- LSI chips based on combinational
er control, and the output buffer. LSI large-scale integration logic and sequential logic. Fortu-
The printing calculator was to be ROM read-only memory nately for us, however, Marcian E.
constructed with nine LSI chips. CPU central processing unit (Ted) Hoff, who was assigned to
The chips were to be used in a I/O input-output work for this project, showed in-
variety of applications—business ALU arithmetic logic unit terest in the ROM-based, macroin-
calculators, scientific calculators, MOS metal-oxide semiconductor struction programmable decimal
billing machines, teller machines, DAA decimal adjust accumulator instruction computer system, the instruction
and cash registers. BCD binary-coded decimal set, and the calculator program
Busicom selected Intel as its DRAM dynamic random-access memory that Busicom proposed for the
development partner for this par- PLA programmable logic array project.
ticular project because Intel had RAM random-access memory
developed a high-performance SR shift register Intel’s Proposal
and high-density silicon-gate RISC reduced instruction set computer It was in late August 1969, when
MOS process. For confidentiality the project was at a standstill, that

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 41

 7 4 3 0 size, increase performance, imple-
PR0 R0 R1 ; Program Counter of Macro Program ment an interpreter, and achieve real-
PR1 R2 R3 ; Start Address of Macroinstruction time control of I/O devices. Figure 2
shows the sources of the instructions
Interpreter Program: in the final 4004 instruction set.
[ Chip 2: Interpretive Routine]
L1: JCN(Test), SIO ; Jump to I/O Control Program of Input-Output Devices Developing the Instruction Set
FIN PR1, PRO ; Load Start Address of Macroinstruction to PR1 The instruction development pro-
JMS S0 ; Jump to Top of Macroinstruction Program ceeded in the following sequence.
[ Chip 3: Subroutine Program for Macroinstruction Set] For real-time control of I/O devices, I
S0: JIN PR1 ; Branch to Macroinstruction added the status of an external input
M_A ; Subroutine Program of Macroinstruction-A pin (Test) as one of conditions of the
conditional jump instruction (JCN).
BBLn ; Return from Subroutine Next I added a 10-b static shift regis-
L2: ISZ R1,L3 ; Update Program Counter of Macro Program ter LSI (SR) to serve not only for key-
INC R0 board scanning but also as an output
L3: JCN(Zero),L1 ; If Macroinstruction is not Branch Instruction, go to L1
buffer for a printer.
TCC ; Check Branch is taken or not (Transfer Carry to Acc & clear Carry)
JCN(Zero),L2 ; If Branch is not taken, go to L2 Further, I added the keyboard pro-
FIN PR0, PR0 ; Load New Address to Program Counter of Macro Program cess (KBP) instruction for converting a
JUN L1 ; Go to Start of Interpreter (L1)
4-b row data of the keyboard into 0, 1,
Figure 3: The interpreter program. 2, 3, or 4, or, if two or more keys were
pressed simultaneously, into 15.
So that we could implement an in-
Hoff proposed to us his basic idea of With this emphasis in mind, as well terpreter program, we added a fetch
a binary processor. He showed us a as our goal of using only LSI chips to indirect instruction (FIN) to load the
block diagram consisting of construct a system, Busicom and In- 8-b data from ROM addressed by the
■■ a 4-b parallel ALU including a 4-b tel agreed to develop a program ROM pair register PR0 into the pair reg-
accumulator; 16 sets of 4-b index and a data RAM in addition to the ister PRn. Next I re­defined the BBL
registers (which could also work processor. Then, we jointly defined instruction (branch back and load
in pairs as eight 8-b registers) a 4-b time-multiplexed bidirectional data to the accumulator) so that it
■■ a 4-level, 12-b address stack system bus for connecting the pro- loads a constant return value n into
holding the program counter cessor directly with both ROM and the accumulator on execution.
and three return addresses reg- RAM. We also agreed to add a deci- Figure 3 shows the interpreter
isters, allowing for three levels mal adjust addition (DAA) instruc- program. It uses PR0 as the program
of nested subroutines tion to be used after the binary ad- counter of the macro program while
■■ keyboard input pins. dition of binary-coded decimal (BCD) the PR1 register holds the start ad-
There were, however, some major data in multidigit decimal numbers. dress in ROM for the macroinstruc-
problems with the proposed binary With DAA, the time required for one- tion to be executed. The interpreter
processor: digit of addition was reduced to 107 first executes JCN, which checks the
■■ It focused only on processor func- microseconds with a 750-kHz clock. Test input to determine if there is a
tion. I conducted both a static evalua- request from an external device. If
■■ The arithmetic instructions oper- tion and a dynamic evaluation of the there is, it jumps to the I/O control
ated only on binary data. proposed instruction set by utilizing program; if not, the interpreter be-
■■ It lacked several instructions a macroinstruction set and an gins normal program execution.
necessary for interpreting appli- application program such as would First, the interpreter executes
cation programs that use a mac- be used in the printing calculator. I FIN to fetch the start address for
roinstruction set. also asked Busicom to measure the the current macroinstruction from
■■ It lacked instructions and features contact time of the keyboard’s key. the ROM addressed by PR0 and
required to control I/O devices in On the basis of these evaluations stores this start address into PR1.
real time. and measurement, I concluded that Next, using the jump to subroutine
■■ The proposed instruction set was it would be critical to the success of instruction (JMS), it transfers ex-
too primitive. the project to add a collection of new ecution to the top of the macroin-
In responding to Intel’s proposal, I useful instructions, redefine some struction program; then it jumps to
emphasized the need to meet the de- instructions, and delete unnecessary the current macroinstruction’s pro-
mands of the application in the sys- instructions; with these changes it gram by using the register-indirect
tem architecture and instruction set. would be possible to reduce the ROM jump instruction (JIN) with PR1.

42 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 In the last step of execution of the
CM-ROM, CM-RAM0-3 +5V –9V PH1 PH2 RESET SYNC
macroinstruction program, a non-
zero return value is stored into the
accumulator with BBL if the macro- RAM/ROM
Selection Timing: A1,A2,A3,M1,M2,X1,X2,X3 Read/Write/Refresh/
instruction is a branch instruction, Address Incrementer
Command DCL Mux. Address Stack
and the carry is set if the branch Register & with Program counter
condition is not met. Reg. 4 × 12 bit
ALU sele-
On returning from the macroin- Instruction ction (3 Tr DRAM Cell)
ROM Table: Encoder Address 1 0 1 0
struction program, the interpreter Decimal Adjust,
Keyboard & Stack Stack Pointer Refresh Counter
updates PR0, processes the branch ALU Control 2 0
macroinstruction if any, and then Control & Refresh Counter
Accumulator & Index
returns to its start. The program & Carry Read/Write
System Instruction Register /Refresh
size of interpretive routine in the in- Bus Decoder Control
4 bit parallel Interface Mux. Index Register
terpreter was 16 B, the longest mac- & 16 × 4 bit
Adder Control
roinstruction took 2 ms to execute, Reg. or
and real-time control of I/O devices sele- 8 × 8 bit
Temporary Reg. Instruction Reg. ction (3 Tr DRAM Cell)
was made possible by polling the
synchronization signal of the print- Internal Data Bus (4 bit)
er via the Test input pin at 2-ms
intervals in the interpreter. This be- TEST D3:0 Address Data Bus (4 Bit)
came one of the keys to the success of
Figure 4: Block diagram of the 4004 CPU.
the 4004 system.

Optimizing Instructions command line instruction (DCL) engineer and two layout designers for
The original proposal from Intel in- and the chip select output pins were the project. There was no logic design
cluded the store instruction (STO) added for selecting RAM without an engineer. Consequently, I joined the
to transfer data from the accumula- external decoder circuit. At the same design group and took charge of the
tor to the index register, but it did time, keyboard input pins and the logic design of the 4004 CPU, logic
not include the load instruction (LD) halt instruction (HLT) were ­deleted. simulation, layout checking, and test
to transfer the data in the opposite It took me three months to opti- program generation. Busicom in To-
direction. In optimizing the instruc- mize the system configuration and kyo took charge of building a CPU
tion set, the STO instruction was the instruction set. However, with emulator for logic verification.
replaced with LD, and the exchange these major changes to the instruc- I designed the logic at the tran-
instruction (XCH), which swaps the tion set, I reduced program size by sistor level instead of the gate level
contents of accumulator and index around 30%. so that it could be used for both the
register, was added. The XCH in- circuit and the layout designs. First, I
struction does not destroy the con- A Brief Return to Japan clearly defined the interface signals
tents of either register. The addition I returned temporarily to Japan in between the functional modules and
of XCH and eight more RAM status December 1969 to finalize the de- then made a detailed functional block
registers per chip made up for the tails of the printing calculator’s diagram of the 4004 CPU before pro-
lack in number of registers in the in- program and confirm the instruc- ceeding with the detailed logic design.
dex register. tion set. Busicom and Intel formally Figure 4 shows the block diagram of
The proposed shift instruction signed a contract for the develop- the 4004 CPU. This was an important
(SH) was replaced with the more use- ment of the LSI chips on February 6, step; back in the 1970s, the success
ful rotate instruction (RA). To reduce 1970, with the development fee set of a microprocessor development de-
program size further, the ­following at US$60,000. In mid-March of that pended largely on the quality of its
instructions were also added: the year, Busicom sent Intel the formal detailed block diagram.
clear-both instruction (CLB) to clear functional specification and the in-
both the accumulator and the carry; struction set, attaching detailed dia- Reducing the Transistor Count
the complement-­carry instruction grams to avoid misunderstanding. Because we chose a three-transistor
(CMC); the transfer-­carry-subtract I visited Intel again to verify the DRAM cell for the address stack and
instruction (TCS) to be used for logic in April 1970, only to find that the index register, each cell con-
decimal subtraction; and the no- the project had made little progress tained one read bit line and one
­operation instruction (NOP) to be since I had returned to Japan—all write bit line. First of all, an address
used for the software timer and the Intel had done in the intervening incrementer was built in the refresh
debugging. Finally, the designate months was to hire one development circuit of the address stack and was

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 43

executable in one state by using two gineering prototype with the 4004
interleaved clocks. Next, in order CPU, 4001 ROM emulator, 4002 RAM,
to calculate early the total number 4003 SR, a card reader, and a control
of transistors needed, the logic de- panel with display. The program
sign started from those modules for the calculator was completed in
that used relatively large number SR 4003 × 2 for March 1971. The total program size
Printer Cont.
of transistors. Those modules were Printer Driver RAM was kept to within 1,000 B, with ap-
the index register (402 transistors), 4002 × 2 proximately 250 B allocated for the
the address stack with an address CPU application program, 400 B for the
incrementer (374), the instruction 4004 macroinstruction program, and 350
­register (72), the timing circuit (99), ROM B for the interpretive routine, key-
the command control (100), and the 4001 × 4 board control, and printer control.
Sense Amp. of Printer
system bus interface control (92), Figure 5 shows the motherboard
SR 4003 × 1 for Option:
which brought the total number Keyboard Scan of the 4004-based printing desk-
4001 × 1
of transistors used to 1139. This OSC. & Clock (Square top calculator. Figure 6 shows the
meant that it would be impossible Root) world’s first microprocessor-based
to design the 4004 CPU within the Figure 5: Motherboard of the 4004 calculator.
2,000-transistor limit that was first microprocessor-based printing desktop
estimated by Intel in the proposal. calculator. The Moment of Truth
The logic design was now reaching The long-awaited moment finally
its completion. In order to simplify send the accumulator and the carry came in April 1971 when the 4004
the logic—and thereby reduce the flag out to the system bus when it CPU arrived at Haneda Airport.
transistor count—we decided that any was idle. In the end, the number of After some simple testing of the
4004 CPU, the 1-Kbyte program was
loaded into the ROM emulator via
a card reader. Now all I had to do
Busicom selected Intel as its development was push and release the reset but-
partner for this particular project because Intel ton of the engineering prototype.
had developed a high-performance and high- While not ­being afraid of failure, I
was also fully aware that the out-
density silicon-gate MOS process. come of the two-year project would
be determined in that one moment.
I pushed the reset button, but hesi-
machine cycle would be composed of transistors used for the 4004 to- tated for a while before releasing
eight states (A1, A2, A3, M1, M2, X1, taled 2,237. it; once released, the final result
X2, and X3). A combinational logic would be inescapable.
circuit was used for instruction ex- Only One Logic Error After a deep breath, I took the
ecution control, and constructed with In the logic simulation carried out in plunge and released the button. The
signals of the instruction decoder (48 August 1970, only one logic error was calculator activated, and the pro-
PLA terms), the instruction encoder found. Consequently, the layout of gram started to run. The address
(6 terms), state timing, and machine the 4004 was almost the same as the display of the program counter in-
cycle timing. A major challenge at this transistor-based logic circuit sche- dicated that the keyboard scan pro-
point—and critical for logic simplifi- matics that I drew in the last phase of gram was executing. Unable to wait
cation—was optimizing by balancing the logic design. I have been feeling any longer, I pressed the number
the selection of the instruction decod- that after Busicom transferred the
ers and encoders with the number of rights to the 4004 to Intel in 1974,
combinational logic circuits. Busicom’s contribution to the 4004
Next, taking the overall layout development faded out.
into consideration, I carefully de-
signed the ALU module (329 tran- Back to the Desktop Calculator
sistors), including the accumula- After completing the test program
tor and decimal adjust circuit, the generation and the layout checking, I
instruction decoder and encoder flew back to Japan in November 1970
(269), and the instruction execu- and returned to my original work
tion control module (500). Then, of developing the printing desktop Figure 6: The world's first microprocessor-
to reduce testing time, I decided to calculator. At Busicom, I built an en- based calculator.

44 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

keys and then the addition key. It felt microprocessors and a Java just-
like I waited forever for the printer in-time-compiler, and teaching the
to start. Finally, the printer roared history of the microprocessor from
into life, and the numbers and addi- the viewpoint of a microprocessor
tion symbol I had input were printed development engineer.
out. I pressed some more number
keys, the addition key, and the equal About the Author
key at the end. “It’s working!” I felt my Masatoshi Shima (Shima80z@
heart pounding and my entire body green.ocn.ne.jp) is a former pro-
flash hot with excitement, while my fessor at Aizu University in Japan.
head alone remained sober. Figure 7: Masatoshi Shima in 1973 at Intel Previously, he was manager of the
during development of the 8080
This was the very moment of Intel Japan Design Center. While
microprocessor.
the birth of the world’s first mi- an employee at Busicom Corp. in
croprocessor, the 4004, and the important to optimize between the Japan, he worked as a program-
microprocessor-based system. I product’s specification and its im- mer of the Mitsubishi-­Melcom-3100
still remember vividly the feel of plementation. After establishing the computer and as a ­logic designer
the reset button on the prototype Intel Japan Design Center in 1980, I for desktop calculators. In 1968,
model, the hopes and fears I felt, developed application-specific micro­ he developed the printing desktop
and my racing heartbeat when I re- processors such as: calculator, in which he introduced
leased that button. ■■ an Intel 8051–based multi-micro­ ROM-based stored programming
processor, composed of one main tech­nology with decimal-plus-bi-
More Innovative Microprocessors processor and ten processor ele­ nary computer architecture.
After the 4004-based calculator ments, for a copier application in After working on the develop-
had been successfully developed, 1985 at Intel Japan ment of the 4000 series of micro-
I moved to Ricoh Corp. There, us- ■■ an x86-compatible low-power micro­ processors, he joined Intel, where
ing NEC’s NEAC-M4 8-b minicom- processor series for a Japa­nese he ­developed the 8080 and sev-
puter, I designed a controller for a word processor appli­cation in 1988 eral peripheral chips as supervis-
high-speed printer and a produc- at VM Technology Corp. ing manager. As manager of high-
tion tester for a drum memory. ■ ■ a 32-b RISC processor–based end microprocessors at Zilog, he
Then I joined Intel in 1972 and de- multi-microprocessor for a doc­ developed the Z80 and Z8000. He
veloped the 8-b 8080 microproces- u­m ent processing system, such received a B.S. in chemistry from
sor, as well as the 8080 peripheral as a digital copier in 1999 at Tohoku University in 1967 and a
LSI chips as supervising engineer TOPS Corp. doctor of engineering degree from
(Figure 7). I moved on to Zilog and
developed the Z80, which later
came to be called the ultimate 8-b
microprocessor. I returned to Ja-
My life as a development engineer was
pan in 1980 after completing the enriched by my decade-long active involvement
development of the 16-b Z8000 in developing innovative microprocessors.
microprocessor.
My life as a development engineer
was enriched by my decade-long
active involvement in developing By the time I had acquired a Tsukuba University in 1992, Ja-
innovative microprocessors, and I doctor of engineering at Tsukuba pan. He published The Birth of the
look back with nostalgia on those University in 1992, I clearly un- Microprocessor: My Recollection,
exciting pioneering days. derstood the things that were im- (Tokyo: Iwanami Shoten Publish-
portant for me in microprocessor ing) in 1987. He received the Kyoto
The Role of Applications development: the instruction set, Prize in 1997, the “Inventor of the
During that decade, I became con- the instruction decoder, and the Microprocessor Unit” Award in
vinced that many innovative prod- hardware architecture that inlcudes 1998 at the 50th Anniversary of
ucts were developed where the internal bus architecture. In 2000, the Semiconductor Industry, and
new generation’s architecture was I moved to Aizu University for the Funai Achievement Award at
required in the application, and teaching and researching computer the Forum on Information Tech-
at the same time it has been quite architecture, designing pipeline nology in 2006.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 45

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Digital Object Identifier 10.1109/MSSC.2009.931982
Reprinted with permission
from Intel

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 by Thomas H. Lee

The path to the microprocessor.

T
he stressful nine-month gesta-
tion had passed both too quickly
and too slowly. Now the wait
was finally over and Federico
Faggin, father, mother, and mid-
wife, expectantly approached his newborn. Hope
tempered with trepidation quickly bubbled over
into elation as waveform after waveform hap-
pily revealed the lusty cries of a healthy infant:
the 4004 was alive and well! It was certainly
a promising start for the microprocessor, but
not even the other parents of the 4004—Stan
Mazor, Ted Hoff, and Masatoshi Shima—could
imagine just how promising. With astonish-
ing speed, its descendants would completely
transform human existence.

The Age of Mechanism

Had we known then what we know now,
the birth of the microprocessor that
January day in 1971 might have been
celebrated the world over. Perhaps, as
with the first transatlantic telegraph
cable and with Telstar, the first com-
munications satellite, the achieve-
ment would have inspired verse and
song. Enthusiastically raucous brass
bands would have accompanied fire-
works and parades. And had caril-
lons competed with that exuberant
cacophony for attention, it would
have been particularly apropos, for

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 sents a primitive but definite form
of data storage, distinct from the
mechanism (execution engine) that
acts on the stored information.
The next evolutionary step ­toward
the computer takes us from Flanders
to France. Basile Bouchon of Lyon
solved a vexing problem in the tex-
tile industry in 1725 by adapting key
aspects of the pin-and-barrel system.
Bouchon’s father was an accomplished
our story traces back in part to the organ builder and familiar with auto-
mechanisms used to automate their mated carillons. The younger Bouchon
playing. reconceived the pin and barrel as a
When the art of modern clock perforated paper cylinder that could
making began to develop in Eu- control the patterns woven by looms.
rope in the 13th and 14th cen- The invention enabled higher speed,
turies, the mechanisms initially Figure 1: Automatic carillon mechanism at better consistency, and the accommo-
Delft. (Courtesy of Adelheid Rech,
marked time by sounding a bell dation of more intricate patterns. The
essentialvermeer.com.)
(typically once or twice an hour), fragility of perforated paper motivat-
rather than providing a continu- barrel, protruding pins strike le- ed Bouchon’s associate, Jean Falcon, to
ous display of time with the now- vers that ultimately ring combina- substitute a chain of sturdy punched
familiar hour and minute hands tions of bells in the corresponding cards for paper in 1728. This arrange-
[1]. These early clocks usually rang sequence. Playing a particular tune ment also had the advantage of easily
a single bell, but a delightful mu- merely involves the insertion of allowing editing of the programmed
sical tradition arose primarily in pins in an appropriate pattern. The patterns, since individual cards could
the “Low Countries” of Holland and simplicity and flexibility of this ar- be exchanged without having to re-
Belgium. Anyone who has exam- rangement greatly facilitates the place the whole set.
ined the mechanism of an old-fash- accommodation of a variety of mu- Bouchon’s inspired adaptation
ioned music box will recognize the sical sequences. Paper maps of the greatly improved throughput and
­b arrel-and-pin arrangement even- pin locations provide a nonvolatile quality, but the process was still
tually devised to automate the play- memory of individual musical se- incompletely automated: a human
ing of the carillon bells (Figure 1). lections and enable rapid setup of had to advance the template manu-
As the clock mechanism rotates the new tunes. The template thus repre- ally, line by line. It was too easy for
a fatigued or distracted weaver to
forget to do so from time to time,
possibly ruining a piece. A fel-
low countryman, Jacques Vaucan-
son, solved that problem logically
enough with an automatic advance
mechanism in 1745. The seemingly
inevitable and obvious next step
of combining Falcon’s card assem-
bly with Vaucanson’s automatic ad-
vance system inexplicably took a
half century. In 1801, Joseph Marie
Jacquard finally took that last step
[2] (see Figure 2).
The Jacquard loom (more prop-
erly, the Jacquard head, as Jacquard
did not modify the loom proper) did
indeed revolutionize the textile in-
dustry, but not in France. Another
(a) (b)
revolution had recently taken place
Figure 2: (a) Loom with Jacquard head, at the Manchester Museum of Science and Industry. there, and it significantly muted the
(b) Closeup of cards. (Courtesy of Wikipedia Commons, George H. Williams.) domestic demand for the patrician

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patterns that Jacquard’s invention Electrons Are Our Friends the Potomac, and just as he had in
made practical. Instead, the ­Jacquard John Shaw Billings was a supervisor establishing the New York Public Li-
loom found a welcome home in Eng- for the 1880 U.S. census, and he saw brary. He’d also proved his powers
land, where it made once-­exotic pat- serious trouble ahead. Manual tab- of persuasion in convincing steel
terns, such as paisley, widely avail- ulation of the census data was slow, magnate Andrew Carnegie to fund
able for the first time. and completing the census took the construction of thousands of
The popularity of Jacquard looms nearly eight years. Billings and his public libraries, so he was the right
had consequences that extended colleagues estimated that the next man to get one of his subordinates,
well beyond textiles. Around 1822 census would take half as many Herman Hollerith, to look into ways
Charles Babbage (later to hold the years longer, so it was evident to all of mechanizing the process to speed
Lucasian professorship of mathemat- that the methods they’d been using up the next census. Hollerith went
ics at Cambridge, as Newton once had reached a scaling limit. Belying to work immediately and in short
had) began developing ideas for a the stereotype of an indifferent, order invented an electrical tabu-
purely mechanical calculating ma- slothful bureaucrat, Billings took lator based on Jacquard’s punched
chine [3], [4]. He was motivated in action, just as he had during the cards (see Figure 4) ([5], [6], also
part by frustration with the rampant U.S. Civil War, where he’d served as see his U.S. patents 395781, 395782
errors in published mathematical medical inspector of the Army of and 395783, filed in September of
­tables. Eliminating the human ele-
ment was essential to achieving his
goal of perfection. His difference en-
gine was to generate tables of loga-
rithms and trigonometric values auto-
matically, using the method of finite
differences to calculate polynomial
­approximations of these functions.
He elaborated on these concepts in
the design of the vastly more power-
ful analytical engine, which used two
sets of Jacquard’s punch cards – one
to specify the operations (program)
and another for the data on which the
program would operate. Neither en-
gine was built in Babbage’s lifetime,
but the concepts underlying their op-
eration are breathtakingly modern.
Particularly noteworthy perhaps is
his explicit recognition of conditional
operators as valuable.
Figure 3: World’s first working Babbage difference engine, on display at the London
A working difference engine was
Science Museum. The printing mechanism is on the left. The operating crank for the Engine is
finally demonstrated in 1991, as seen on the right. (Courtesy of Wikipedia: Difference Engine.)
part of a bicentennial celebration of
Babbage’s birth. It took almost an-
other decade to realize his concepts
for the associated printing mecha-
nism. Figure 3 shows the completed
difference engine on display at the
­London Science Museum. There are
no known plans by anyone any-
where for an attempt to build an
analytical engine.
Babbage died in 1871, just a few
years too soon to see his idea of us-
(a) (b)
ing Jacquard’s (Falcon’s) cards for
data storage adopted by government Figure 4: Hollerith census tabulator, at the Computer History Museum. Dials indicate
bureaucrats desperate to solve a dif- current and total value of individual data fields. Punch cards would be used with computers
ferent set of problems. well into the 1970s.

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1884). The card reader [see Figure Aspects of Babbage’s work also is perhaps especially noteworthy for
4(b)] used a movable “bed of nails” ultimately inspired the creation of its contribution to popular culture:
to make electrical contact through an analog mechanical computer, The proximity to Hollywood helps
card holes to mercury-filled wells the differential analyzer (Figure 5) explain why the UCLA analyzer ap-
in the base. ([7], [8]; ancestors of the MIT differ- pears in movies such as When Worlds
Collide and Earth vs. The Flying Sau-
cers. These films, dating from 1951
Thanks to the speed and accuracy of and 1956, respectively, attest to the
Hollerith’s electrical tabulator, the 1890 iconic status of the analyzer in the
early postwar period.
census was finished in little over half the As powerful and flexible as the
time of the 1880 census. analyzer was, it did suffer from sev-
eral deficiencies. “Programming” the
analyzer involved disassembling the
To save time and money, Hollerith ential analyzer include the work of previous setup and reassembling
chose dimensions for the card that William Thomson (later to become the new configuration of gears and
matched those of the U.S. dollar Lord Kelvin); in turn, Thomson’s linkages, for example. Merely setting
bill at the time, allowing him to use work ­represents a reestablishment up a problem for solution often took
components and whole assemblies of an analog computing tradition days of wrench-work that would’ve
from preexisting machines. Thanks that dates back to the Antikythera been more familiar to automobile
to the speed and accuracy of Hol- mechanism of ­Roman times.) Van- mechanics than to mathematicians.
lerith’s electrical tabulator, the 1890 nevar Bush, ­Harold Hazen, and their Indeed, computing the solution often
census was finished in little over colleagues began working on the took less, sometimes much less, time
half the time of the 1880 census, analyzer at MIT in the late 1920s than it took to set up the analyzer.
and that included a complete sec- and were able to demonstrate an Inevitably, students were pressed
ond run needed to overcome skep- operational unit in the early 1930s. into service as make-do mechanics
ticism about this new way of doing Capable of solving sixth-order dif- to configure, operate, and maintain
things. Hollerith’s Tabulating Ma- ferential equations, the versatile an- the analyzer. One of these students
chine Company eventually became alyzer was suitable for everything was Claude Shannon, who had re-
the International Business Machines from early quantum calculations to cently started his graduate studies
Corporation in 1924, after a series generating ballistics firing tables. at MIT after earning two bachelor’s
of acquisitions and mergers. History The technical success of the MIT degrees (in mathematics and electri-
records that a company called IBM analyzer led to the adoption of the cal engineering) at the University of
enjoyed some success in the com- architecture at a number of other in- Michigan in 1936. By 1937, Shannon’s
puter business. stitutions. The installation at UCLA experiences with the analyzer had
motivated him to invent the tech-
nology that would soon render ob-
solete the analyzer and its mechani-
cal kin: digital electronics. Shannon
was ­familiar with the then-obscure
work of George Boole [9] and real-
ized that Boole’s concepts could be
applied to the analysis and design
of what we now call digital circuits.
A 1938 paper derived from (and
titled the same as) his 1937 mas-
ter’s thesis, “A Symbolic Analysis of
Relay and Switching Circuits,” was
immediately influential [10]. For vir-
tually all readers, it was their first
exposure to the names and power-
ful ideas of Boole and Augustus De
Morgan. Shannon’s paper presented
a rich formalism that transformed
Figure 5: Vannevar Bush (background) examining the differential analyzer in operation. into an engineering discipline what
(Courtesy of the MIT Museum.) had ­previously been an ad hoc art.

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Considering all that has followed in the formal sense, the term is col- development was limited because
from this work, it’s difficult to argue loquially applied to computers that of the secrecy that enshrouded
with the common assessment that would be complete if infinite mem- the work. Indeed, all ten Colossus
it was the most important master’s ory were available.) A reconstructed machines in use by the end of the
thesis of the 20th century. Z3 is on display at the wonderful war, and all associated ­e ngineering
Once binary logic was understood Deutsches Museum in Munich. documents, were deliberately
by a critical mass of engineers, it
was only a matter of time before ful-
ly electronic computers would turn It was certainly a promising start for the
their electromechanical counter- microprocessor, but not even the other parents
parts into museum pieces. Abetting
that transition was the work of Alan
of the 4004—Stan Mazor, Ted Hoff, and
Turing. At ­v irtually the same time Masatoshi Shima—could imagine just how
that ­Shannon was inventing digital promising.
electronics, Turing was establish-
ing some of the foundational ideas
of computer science. Perhaps chief At approximately the same time ­ estroyed after the war, on orders
d
among these was the concept of a as Zuse was demonstrating his from Winston Churchill himself.
universal machine (known today as relay-based Z3, Clifford Berry and The world at large thus knew noth-
a Turing machine) that could imple- John Atanasoff of Iowa State Col- ing of the Bletchley Park achieve-
ment any function that was com- lege were building an electronic ments until the 1970s. ­S urviving
putable. Such a universal machine computer designed to solve sys- alumni of the effort helped to
is now known as a Turing-complete tems of linear equations. As did the reconstruct the ­C olossus from
­computer. The influence of Turn- Z3, the Atanasoff-Berry Computer memory, with success achieved in
ing’s ideas took somewhat longer to (ABC) used binary arithmetic. It 2006 [15].
be felt, but that influence has been also used dynamic memory based A computer of the era that did
no less profound than Shannon’s. on capacitive storage cells, prop- have great influence was the dec-
erly implementing the necessary imal-based ENIAC (electronic nu-
Onward to the Fully refresh ­operations. Robert Dennard merical integrator and computer;
Electronic Computer of IBM would reinvent capacitive dy- see Figure 6). The project that
The demands of the Second World namic memory in integrated circuit gave life to ENIAC began with John
War greatly accelerated the devel- form almost three decades later [12] Mauchly’s prewar desire to build a
opment of virtually all technolo- (his article implies that he was un- weather-forecasting computer. The
gies. Computers both aided, and aware of the ABC’s use of dynamic University of Pennsylvania profes-
were aided by, these developments memory). Although the ABC was not sor redirected his efforts after war
in no small measure. Only electro- programmable, its innovations were broke out to design a computer that
mechanical analog computers had nonetheless influential. The degree would carry out the same sort of
existed before the war. By the war’s of this influence was the subject ballistics calculations that the dif-
end, electronic computers with rec- of protracted litigation that finally ferential analyzer could perform.
ognizably modern characteristics concluded in favor of the ABC team Mauchly understood that an elec-
had come into existence, with fully in 1973. Although the litigation may tronic computer would be able to
digital programmable electronic have ended, the arguments clearly outperform a mechanical one by
computers following soon after. have not [13], [14]. orders of magnitude. Working with
In Germany, Konrad Zuse con- The war naturally also stimu- J. Presper Eckert, the ENIAC became
structed a succession of digital lated intense activity in the Unit- operational at the university’s Moore
computers based on relay logic. His ed Kingdom. At Bletchley Park, a School of Electrical Engineering lab-
third, dubbed the Z3, executed pro- secret effort dedicated to cracking oratories in 1945; it was the first Tur-
grams stored on paper tape and was ­G erman codes produced the Co- ing-complete electronic computer
operational by 1941. It was the first lossus computer in 1944. It holds [2]. Its complement of nearly 18,000
program-controlled digital computer the distinction of being the first vacuum tubes helped account for
possessing all of the essential char- ­programmable digital electronic its 150 kW power consumption (and
acteristics of what we think of as a computer. Somewhat ironically, a mean time between failures of a
modern computer. Specifically, it was however, it was not Turing com- day or two). It could multiply two
the first “Turing complete” machine plete, even though ­Turing worked at ten-digit decimal numbers in a few
[11]. (Although no computer with fi- Bletchley Park. The influence of the milliseconds. A few hundred mul-
nite memory can be Turing complete Colossus on subsequent computer tiplications per second may be

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 IBM 650-series computer (the first
mass-produced computer) printing
out the credits. IBM’s computers
would famously come to dominate
the mainframe world.
The evolution of the computer
during this fertile period is mir-
rored in the rapidly evolving ety-
mology. Until the electronic age, a
computer was a human who did cal-
culations [16]. When devices such as
the analyzer appeared, the qualifier
mechanical had to be added to dis-
tinguish the new from the old. The
arrival of a still-newer technology
was acknowledged by the estab-
lishment of MIT’s Digital Computer
Laboratory in 1951. The subsequent
dominance of digital computers
eventually made the qualifier digital
Figure 6: ENIAC in operation. The rat’s nest of patch cables used to program the computer unnecessary, and the retronym ana-
are clearly visible on the left. (Courtesy of Wikipedia.) log computer was created to distin-
guish the old from the new. Today, a
computer is a digital computer in all
laughable performance today, but it Mauchly and Eckert left the but a very few cases.
astonished at the time. university to start their own com- The links connecting UNIVAC to
ENIAC begat EDVAC (Electron- puter company, the Eckert-Mauchly the 4004 include the first transis-
ic Discrete Variable Automatic Computer Corporation. Through an tor computers, the TX0 and TX2,
­Computer; clearly the Department of ­acquisition in 1950, EMCC became built at MIT’s Lincoln Laboratory,
Cumbersome Acronyms was working the Univac division of Remington and the miniaturization that tran-
sistors made possible. That min-
iaturization in turn kicked off the
The popularity of Jacquard looms had minicomputer revolution, led by
consequences that extended well beyond Digital Equipment Corporation,
whose founders, Ken Olsen and
textiles. Norm Andersen, had worked on the
TX0. Their PDP-1 debuted in 1958,
overtime) at the Moore School. John Rand. The UNIVAC computer gained and its interactive and more per-
von Neumann authored an influen- fame for accurately predicting the sonal type of computing inflamed
tial report on EDVAC, in which he outcome of the 1952 presidential a desire among engineers for still-
elaborated on some of Turing’s ideas. election, where human pollsters smaller, even-more personal com-
Unlike the decimal-based ENIAC, had not. Television network CBS puters. With the invention of the
EDVAC would be a binary digital had chosen to include UNIVAC in integrated circuit soon after DEC’s
computer, and program instructions their broadcast coverage largely as founding, the basic elements were
would share memory with operands. a publicity gimmick and simply dis- in place [17]. After a few genera-
This shared-­memory structure is believed the machine’s predictions tions of Moore’s law, and a small
now known as the von Neumann until hard data revealed that UNI- additional stimulus, the micropro-
architecture, thanks to his sole au- VAC had been correct all along. Lat- cessor would be all but inevitable.
thorship of the report. This assign- er in the broadcast, Walter Cronkite By 1970, with Busicom’s desire to
ment of credit has been a source of apologized on camera. Overnight, make calculators, and Intel’s desire
annoyance to others working on the the idea of an omniscient elec- to sell them chips, the necessary
project, Mauchly and ­Eckert included tronic brain gained currency in conditions were well satisfied.
[14]. Perhaps it is sufficient to note the popular imagination. The 1957
that success has many fathers, and Tracy-Hepburn film, Desk Set, plays Summary
grand successes tend to stimulate on this notion and in fact opens As with all human stories, the path
many claims to paternity. with a sequence that features an to the microprocessor was anything

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 [17] T. Lee, “The (pre)- history of the inte-
grated circuit: A random walk,” IEEE Solid-
State Circuits Newsletter, vol. 12, no. 2,
Bits of art scattered over the globe and across Apr. 2007.

­centuries somehow assembled organically to

drive the narrative of this history. About the Author
Thomas H. Lee (tomlee@ee. stan-
ford.edu) received the S.B., S.M. and
Sc.D. degrees in electrical engineer-
but a straight line. Bits of art scat- graciously taking the time to answer ing, all from the Massachusetts In-
tered over the globe and across many questions. stitute of Technology in 1983, 1985,
­centuries somehow assembled or- and 1990, respectively. He joined
ganically to drive the narrative of References Analog Devices in 1990 where he
this history. The random nature [1] T.H. Lee, “It’s about time: A brief chronol- was engaged in the design of high-
ogy of chronometry,” IEEE Solid-State Cir-
of creation forces us to impose an cuits Newsletter, vol. 13, no. 3, pp. 42–48,
speed clock recovery devices. In
a posteriori order that is arguably July 2008. 1992, he joined Rambus Inc. in
[2] H.H. Goldstine, The Computer from Pas-
more of a Rorschach test than an cal to von Neumann. Princeton, NJ: Princ-
Mountain View, California, where
objective recounting. Instead of eton Univ. Press, 1980. he developed high-speed analog
[3] C. Babbage, “A note respecting the app li-
starting with carillons, we could cation of machinery to the calculation of
circuitry for 500 megabyte/s CMOS
have gone further back in time, to astronomical tables,” Memoirs of the Roy- DRAMs. He has also contributed
al Astronomical Society of London, read 14
Heron of Alexandria, whose virtu- June 1822.
to the development of PLLs in the
osity with mechanism included the [4] “Babbage Difference Engine #2,” (22 Oct. StrongARM, Alpha and AMD K6/K7/
2008) [Online]. Available: http://ed-thelen.
construction of devices that are the org/bab/bab-intro.html
K8 microprocessors. Since 1994, he
direct ancestors of the pin and bar- [5] H. Hollerith, “The electrical tabulating has been a professor of Electrical
machine,” J. Royal Statist. Soc., vol. 57, no.
rel. We also could have examined 4, pp. 678–689, Dec. 1894).
Engineering at Stanford University
the contributions of Ada ­Byron [6] “Herman Hollerith,” (1 Nov. 2008) [On- where his research focus has been
line]. Available: http://www-03.ibm.com/
King, ­Countess of ­Lovelace, and ibm/history/exhibits/builders/builders_
on gigahertz-speed wireline and
her work with Babbage, or about hollerith.html wireless integrated circuits built in
[7] T.H. Lee, “Tales of the continuum: A sub-
the profound ­influence of Turing’s sampled history of analog circuits,” IEEE
­conventional silicon technologies,
ideas, but one must bound the story SSCS Magazine, October 2007. particularly CMOS. He has twice
[8] K. Lundberg, “Vannevar Bush’s differen-
somehow, ­especially in an article of tial analyzer,” (20 Oct. 2008) [Online].
­received the “Best Paper” award at
a few pages. It is hoped that the in- Available: http://web.mit.edu/klund/www/ the International Solid-State Cir-
analyzer/
completeness does not undermine [9] G. Boole, An Investigation of the Laws of
cuits Conference, coauthored a
the basic thesis that, although the Thought. London: Macmillan, 1854. [On- “Best Student Paper” at ISSCC, was
line]. Available: http://www.archive.org/
microprocessor may have been details/investigationofl00boolrich
awarded the Best Paper prize at
­inevitable, the particular path con- [10] C.E. Shannon, Trans. AIEE, vol. 57, pp. CICC, and is a Packard Foundation
713–723, 1938. [Online]. Available: http://
necting it to ­automated carillons d s p a c e . m it .e du / b it s t r e a m / h a n d l e /
Fellowship recipient. He is an IEEE
was probably not unique. If we were 1721.1/11173/34541425.pdf?sequence=1 Distinguished Lecturer of the IEEE
[11] “Konrad Zuse,” Wikipedia, [Online]. Avail-
to rerun the tape of history, it is un- able: http://en.wikipedia.org/wiki/Kon-
Solid-State Circuits Society, and a
likely that events would unfold in rad_Zuse, retrieved 1 Nov. 2008. past Distinguished Lecturer of the
[12] R.H. Dennard, “Revisiting evolution of the
the same manner again. But let the MOSFET dynamic RAM—A personal view
IEEE Microwave Society. He holds
carillons chime in celebration just IEEE Solid-State Circuits Newsletter, vol. 43 U.S. patents and authored The
13, no. 1, pp. 10–25, Jan. 2008.
the same. [13] The Trial, [Online]. Available: http://
Design of CMOS Radio-Frequency In-
www.scl.ameslab.gov/ABC/Trial.html, re- tegrated Circuits (now in its second
trieved 1 Nov. 2008.
Acknowledgments [14] “Q&A: A lost interview with ENIAC
edition) and Planar Microwave Engi-
The author is grateful to Mary co-inventor J. Presper Eckert,” Com- neering, both with Cambridge Uni-
puterworld, [Online]. Available:
­L anzerotti and Katherine Olstein for h t t p : // w w w . c o m p u t e r w o r l d . c o m /
versity Press. He is the coauthor of
professing to believe that this man- printthis/2006/0,4814,108568,00.html, four additional books on RF circuit
retrieved 1 Nov. 2008.
uscript would be completed, despite [15] “Colossus Computer,” (1 Nov. 2008) Wiki-
design and also cofounded Matrix
the total absence of any supporting pedia, [Online]. Available: http://en. Semiconductor (acquired by Sand-
wikipedia.org/wiki/Colossus_computer
evidence. The author is also espe- [16] D.A. Grier, When Computers Were Human.
isk in 2006). He is the founder of
cially grateful to Federico Faggin for Princeton, NJ: Princeton Univ. Press, 2005. ZeroG Wireless.

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by Sam Naffziger

To avoid relegation to commodity status, new

approaches to improvement must be found.

T
he story of processor develop-
ment has been one of spectacu-
lar growth and global impact
since 1971, the year of the first
true microprocessors [1]. Perfor-
mance, integration levels, volumes, and revenue
all increased at exponential rates for decades.
Computational capacity grew by many orders of
magnitude, enabling the explosion in information
technology that has powered the digital age. Pro-
cessor ­architectures and implementations greatly
increased in ­diversity and methods with fierce
competition between options ­during the 1980s
and 1990s.
The 2000s have seen leading-edge, high-perfor-
mance ­architectures whittled down to just a few
players—Intel, AMD, IBM, and Sun. (Although it’s
interesting to note that the vast majority of pro-
cessors shipped are still 8 b microcontrollers, and
the venerable Z80 design from 1976 is still going
strong.) This article will focus on characteristics of
the leading-edge designs, since they tend to drive
the technology and fuel the growth of computing.

Are Processor Performance

Drivers Tapped Out?
The vast improvements in processor computa-
tional capabilities have been fueled by several
factors: improvements in architecture, in pro-
cessor frequency, in the ability to integrate
© photo f/x2

more components on-die, and above all in

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­ rocess technology scaling. What
p
is the ­f uture potential of each of Intel 386
Specint2000 per MHz
these factors? 1.20 Intel 486
Intel Pentium
Intel Pentium 2
Architecture Improvements 1.00 Intel Pentium 3
Intel Pentium 4
Architectural innovations are where Intel Itanium
0.80
much of the attention has gone and Alpha 21064
Alpha 21164
where the largest pitched battles Alpha 21264
0.60
have been fought. CISC, RISC, EPIC, Sparc
and VLIW are all different approach- SuperSparc
0.40 Sparc64
es to squeezing the most instruction Mips
level parallelism out of a given appli- 0.20 HP PA
Power PC
cation (see “Architectural Acronyms AMD K6
0.00 AMD K7
Defined”). Improvements in the pro-
AMD x86-64
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07
cessor’s ability to extract parallelism
have been significant but are limited
Figure 1: Performance per cycle versus time [1].
to just an order of magnitude or so
over the entire lifetime of processor
development. Note the marked flat- Process Technology
tening out of the curve in Figure 1, Architectural The vast improvements in silicon
which indicates the efficiency of an Acronyms Defined process technology, described by
architecture—that is, the ability of a CISC Complex instruction set Moore’s law, have had the single
processor to get more work done on computing largest impact on processor per-
each clock tick. This is an indication formance over time. These im-
RISC Reduced instruction set
that, for single-threaded workloads provements have come in three
computing
(which the term SpecInt in Figure 1 main areas: density increases,
represents), designers are running EPIC Explicitly parallel instruction transistor speed improvements,
out of architectural tricks to increase computing and energy-per-gate reductions.
performance. There have been nu- VLIW Very large instruction word Density is obviously the key to
merous attempts at architectural improving processor integration
breakthroughs to avoid this limit, levels, adding features for per-
such as the EPIC architecture [2], but processor frequency—has been an- formance extraction such as ad-
the limited returns of architecture other important factor fueling the ditional execution units and cache
on performance versus other meth- increase in processor performance. memory. Density has approxi-
ods, and the sheer inertia created by Reducing the gates per cycle im- mately doubled every 24 months
trillions of lines of legacy code sup- proves frequency independently for over 30 years (Figure 3).
port cannot be overcome. of process technology transistor The impact of density on per-
Of course, adding more cores to speeds but requires broad innova- formance is considerably less than
the processor helps some workloads tion across the processor micro­ one for one, however. The second
by running separate programs, or architecture, and especially in main area of process technology
threads, in parallel, and processor circuit design methodology. Huge that impacts performance is, of
designers are aggressively pursuing improvements in this arena were course, transistor speed, which
this approach. The ability of main- made in the 1990s, largely spear- has increased by a couple of or-
stream applications to exploit addi- headed by the DEC Alpha proces- ders of magnitude in the last three
tional processor cores is quite lim- sors. Unfortunately, however, this decades, dramatically improving
ited, however, and since each core dimension of performance improve- processor frequency, as shown in
comes at a significant power cost, the ment is largely tapped out as well, Figure 4, which plots absolute pro-
performance per watt provided by as evidenced by another flattening cessor frequency (inversely pro-
increasing cores actually goes down curve in Figure 2, which shows the portional to gates per cycle and
for most workloads. This imposes a number of basic logic gates that directly proportional to transistor
severe limit on the growth of core- can fit in the architected cycle speed) versus time.
counts in mainstream processors. time. For a given process technol- Critical to exploiting these im-
ogy, this is inversely proportional provements in density and speed
Increased Frequency to the frequency (since each gate has been the reduction in energy per
The reduction in gates per cycle, takes a fixed amount of time) that gate afforded by reduced dimensions
and its corollary—the increase in the processor can achieve. and the classic scaling of CMOS [3].

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 Cycle in FO4
100
Intel 386
Intel 486
Intel Pentium
Intel Pentium 2
Intel Pentium 3
Intel Pentium 4
Intel Itanium
Alpha 21064
Alpha 21164
Alpha 21264
Sparc
SuperSparc
Sparc64
Mips
HP PA
Power PC
AMD K6
AMD K7
AMD x86-64
10
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07

Figure 2: Gates per cycle versus time [1].

Many innovations are coming

Moore’s Law out of the process community,
10,000,000,000 Number of Transistors Doubling such as high-k/metal gate tran-
Every 18 Months sistors [4], copper interconnects,
1,000,000,000 Itanium 2 low-k dielectrics and improve-
(9 MB Cache) ments in lithography. These en-
Number of Transistors on

Number of Transistors Doubling Itanium 2 able continued scaling according

100,000,000
an Integrated Circuit

Every 24 Months
Pentium 4 to Moore’s law (which really just
Itanium
10,000,000 Pentium III addresses density), but the fun-
Pentium II damentals are such that integra-
Pentium
1,000,000 486 tion levels are now increasing
much faster than the energy per
386
286 gate is decreasing. It is this fact
100,000
that has driven the latest power
8086 crisis in the industry and pre-
10,000
8080 cipitated a wave of innovation
2,300 8008
4004 around power management and
1971 1980 1990 2000 2004
reduction technologies. (The ma-
Year jor power crisis in the mid-1980s
caused a rapid shift from NMOS
Figure 3: Moore’s law. to CMOS technologies.)

Larger Development Efforts

Without this, power consumption reduction of power with voltage re- As the processor market grew into
would increase at the same expo- duction, as Figure 5 shows. This ef- tens of billions of dollars, it be-
nential rate as integration and fre- fect has been exploited heavily over came feasible to invest hundreds
quency. One of the strongest effects time, but as with other improvement of millions of R&D dollars into in-
on energy has been the quadratic areas, has largely run out of room. creasingly sophisticated designs.

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(It has been this investment that
produced the improvements just Clock Frequency (MHz)
10,000 Intel 386
described.) As a result, proces- Intel 486
sor design teams have increased Intel Pentium
Intel Pentium 2
over time to sizes that strain the Intel Pentium 3
Intel Pentium 4
limits of practical team dynamics Intel Itanium
1,000 Alpha 21064
and are at the point of diminish-
Alpha 21164
ing returns. This has resulted in Alpha 21264

MHz
the final limitation to continued Sparc
SuperSparc
­p erformance scaling: designing Sparc64
100 Mips
and verifying the vast complexi-
HP PA
ties that surround modern proces- Power PC
sors. As Figure 6 shows, the logic AMD K6
AMD K7
transistor count in processors has AMD x86-64
10
continued to increase over time as
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a result of complex performance-
Year
enhancing features.
Every generation, an array of new
Figure 4: Processor frequency versus time [1].
capabilities debuts while all of the
prior features and special instruc-
tions from the past 25 years con-
tinue to be supported. This logical operating Voltage
6
complexity burden, in combination Intel 386
Intel 486
with the circuit design complexity Intel pentium
5 Intel pentium 2
instigated by process scaling, has
Intel pentium 3
greatly increased the level of design Intel pentium 4
complexity and verification burden 4 Intel Itanium
Alpha 21064
required to produce a modern x86 Alpha 21164
Volts

processor. This is the major factor 3 Alpha 21264

Sparc
that has whittled the field down SuperSparc
to just a handful of players—engi- 2 Sparc64
Mips
neering costs are too high and the hp pA
legacy knowledge levels too deep 1 power pC
AMD K6
for new players to break in. Pre- AMD K7
silicon verification and postsilicon 0 AMD x86-64
validation are both now first-order 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07
limiters of both time to market and Year
feature additions. There is a very
limited budget for improvement Figure 5: Operating voltage versus time [1].
with each generation.

Future Directions adaptive design techniques, and translation, partitioning, security,

If processors are to avoid becom- higher productivity through auto- and so forth, was pulled on-board
ing a commodity where perfor- mation and modularity. with the μVAX II, DEC’s first single-
mance growth flattens and value chip VAX microprocessor. Improve-
is determined simply by price, if Increased Integration ments in translation lookaside buf-
they are to continue to fuel the The latency and bandwidth benefits fers (TLBs), which perform many of
growth of ­i nformation technology, of on-die integration have greatly the MMU functions, and in memory
if they are to continue to drive the improved the number-crunching management have been an impor-
economics of process scaling, then capability of processors over time, tant part of processor design ever
approaches to improvement dif- and processor design history is since. Similarly, the floating-point
ferent from those used in the past full of examples of the integration unit was integrated on-die starting
must be found. These improve- of components that were formerly with the Intel 80486 and Motorola
ments will come in three main implemented as discrete chips. 68040 designs.
areas: greater integration of het- The memory management unit Memory controllers were the next
erogeneous system components, (MMU), which handles memory item to get pulled on-chip, starting

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 So the question is whether there
Logical Complexity is further integration to be exploit-
10,000 ed. The clear answer is yes.
Processor Transistors One reason for this optimism
Expon. (Processor Transistors) comes from the curves in Figure 7,
Transistor Count (Millions)

1,000 which clearly show that—while x86

core performance growth has flat-
tened out—GPU computation ca-
100 pability has been accelerating ever
faster. The reasons for this follow
directly from the prior discussion—
10 processors have run out of parallel-
ism, while process scaling is pro-
viding density, but not speed and
1 energy, improvements. The same is
not true for GPUs. They can exploit
93

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00

02

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07

08
19

19

19

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20
parallel computation almost with-
Year
out limit, and the algorithms are
Figure 6: Processor logic transistor counts (excluding memory) versus year as presented at extremely insensitive to latency. So
ISSCC. Information from http://www.sscs.org/isscc. if the process affords more transis-
tors, the GPU turns that directly into
performance.
Out of power? Just reduce the
300 voltage and frequency, regaining
the lost performance through more
NVIDIA parallelism. This will eventually run
ATI into fundamental voltage-scaling
200 Intel limitations, but there’s still quite
a way to go. These realities are en-
GFLOPS

abling GPU performance to outstrip

that of mainstream processors into
100 the foreseeable future. A key for fu-
ture processor scaling is therefore
to tap into this performance scaling
Dual-Core
through instruction set extensions
0 and tight integration with the in-
2002 2004 2006 creasingly powerful GPU.
Year Other frontiers for integration
are with “SouthBridge” I/O control-
Figure 7: The programmable floating-point performance of GPUs, measured on the lers; these are the chips that bridge
multiply-add instruction (MAD). Counting two floating-point operations per MAD has
bridges the CPU to various I/O de-
increased dramatically over the last four years compared to that of CPUs [5].
vices such as disk drives, displays,
and USB ports (so called because
they are typically drawn at the bot-
(for mainstream x86 processors) performance. GPUs have been an- tom, or “south,” of system schemat-
with the AMD Opteron. Connecting nounced (but not shipped yet) by ics). In particular, Ethernet I/O in-
the dynamic random-access mem- both AMD and Intel. GPUs promise tegration is a promising direction
ory (DRAM) directly to the proces- stand to gain from the same factors for server processors to subsume
sor afforded considerable reduc- that benefited prior integrations all I/O except perhaps SATA (serial
tion in memory latency reduction, attained: reduced latency from advanced technology attachment)
and this improved server workload tight connections to the processor disk interfaces. Then, there is the
performance significantly. The lat- core, improved power efficiency prospect of truly integrating main
est direction for integration is the through on-die connections, and a memory. This task likely requires
­g raphics processing unit (GPU), host of lower-level optimizations advances in three-dimensional die-
which employs highly parallel com- made possible by design leverage stacking capability, and the former
putation units to improve graphics and synergy. presents considerable IP and analog

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design challenges, but similar hur- Figure 9 shows the conceptual voltage adaptation can yield power ef-
dles have been cleared in the past. A premise of adaptive design applied ficiency benefits of 30% or more.
truly integrated single-package pro- to the spreads in leakage that pro- With dramatically increased lev-
cessor solution can be envisioned cessors see through normal manu- els of integration, the ability to com-
as in Figure 8, in which a processor facturing variations. With advanced pletely turn off unused portions of
core (compute die) is stacked with technologies, power limits will be ex- the design will become essential.
all of the requisite system compo- ceeded with parts that are too leaky. An inevitable result of integrating
nents, including SouthBridge (SB), Leaky parts tend to be too slow, since more special-function units, pro-
main memory, and flash disk. This leakage correlates to speed in CMOS cessor cores, and memory is that
integrated structure would provide technology, but leakage is a difficult these units will be employed for
major performance, power efficien- parameter to manage. Adapting sup- only a subset of workloads and us-
cy, and form factor benefits by re- ply voltage to the observed leakage on age modes. The nature of advanced
ducing latency and I/O power. a per-part basis can yield significant process technologies is that unused
Not pictured is the thermal inno- benefits. Given the large variations circuits behave like resistors, trick-
vation that would likely be required present in the manufacturing pro- ling away precious energy. In order
to enable such a structure to oper- cesses of modern processors, simple to ensure that all energy results in
ate reliably. Achieving such an in-
tegration feat will require not only
sophisticated package, thermal, and
assembly technology but also a level
of complexity management and de-
sign efficiency that the industry Heat Sink
Heat Sink
hasn’t achieved to date.
TIM
TIM(Thermal
(ThermalInterface
InterfaceMaterial)
Material)
Adaptive Design Flash
Flash Storage
Storage Die
Die
The raw physics of scaling tradi- Metal
Metal Layers
Layers
tional designs into new process Analog
AnalogDie
Die(SB,
(SB,Power)
Power)
technologies does not result in sig- Metal
MetalLayers
Layers
nificant mainstream performance Memory Die
Metal
Metal Layers
Layers
gains. Variations in workload, envi-
ronmental conditions, and manufac- Compute Die
Metal
MetalLayers
Layers
turing technology all become more
significant at smaller scales. Nev- Package
Package Substrate
Substrate
ertheless, there remains a huge op-
portunity in adapting to these varia-
Figure 8: A single-socket integrated computer with three-dimensional stacking would
tions. The traditional worst-case
provide huge power, density, and performance improvements.
design used to accommodate such
variation result in large unexploited
margins that degrade performance
and performance per watt. An alter-
native is adaptive processors that
Fixed Vdd
are made aware of their environ-
ment and operating conditions by
various sensors. Such parameters ASV
Too
Number of Die

as workload, component utilization,

Leaky
temperature, voltage, and transistor
speed can be tracked. The processor
Too
must then have some ability to re- Slow
spond usefully to the sensor stimu- Vdd
Vdd
lus. This response can take many Raised Lowered
forms: ­altering the supply voltage,
using forward or reverse body bias
to adjust threshold voltage, chang-
ftarget Frequency ftarget
ing clock rates, gating clocks, or
gating off sections of the design en-
tirely with power switches. Figure 9: Benefits of adaptive supply voltage (ASV) [6].

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useful computation, components but the performance cost of this gine of growth in the information
on the processor that are not see- automation has always been too technology industry.
ing use must be not only clock-gated high compared to more customized
off, but must also be disconnected approaches. The primary changes References
[1] M. Horowitz, private communication.
from the supply. This capability is that will now drive new approaches
[2] S. Shankland, “Itanium: A cautionary tale.”
already present in many low-power forward are the following: Available in Tech News at www.ZDNet.
embedded processors and is mak- 1) The processor core itself has com, Dec. 7, 2005.
ing its way into the mainstream. The reached the performance plateau. [3] R. H. Dennard, F. H. Gaensslen, V. L. Ride-
out, E. Bassous, and A. R. LeBlanc, “De-
management of these power gates, 2) Value is added primarily through sign of ion-implanted MOSFETs with very
in combination with voltage adapta- increased integration and chip- small physical dimensions,” IEEE J. Solid-
State Circuits, pp. 668–678, Oct. 1974.
tion, frequency scaling, and so forth level management functions.
[4] K. Mistry et al., “A 45nm logic technol-
is such a complex task that recent A smaller portion of chip-level re- ogy with high-k+metal gate transistors,
high-end processors are now dedi- sources will be allocated to custom strained silicon, 9 cu interconnect layers,
193nm dry patterning, and 100% Pb-free
cating integrated microcontrollers circuits as the number of transistors packaging,” in Proc. Int. Electron Devices
(with as many transistors as the that each designer is responsible for Meeting, 2007.
[5] J. D. Owens, D. Luebke, N. Govindaraju, M.
entire processor of ten years ago) continues to increase. Therefore, Harris, J. Krüger, A. E. Lefohn, and T. Pur-
to the task. These adaptive capabili- much of the processor core innova- cell, “A survey of general-purpose com-
putation on graphics hardware,” Comput.
ties and run-time optimization of tion will be channeled toward de- Graph. Forum, vol. 26, no. 1, pp. 80–113,
processor resources will continue signer productivity improvements Mar. 2007.
to grow in importance and enable and toward modularity that enables [6] T. Chen and S. Naffziger, “Comparison of
adaptive body bias (ABB) and adaptive
additional performance scaling into rapid processor design. supply voltage (ASV) for improving delay
the future. and leakage under the presence of pro-
cess variation,” IEEE Trans. VLSI Systems,
Conclusion vol. 11, no. 5, pp. 888–899, Oct. 2003.
Improving Designer Productivity Many of the traditional measures
The final major trend that will of microprocessor performance
enable processor designs to scale growth and value have reached a About the Author
­performance and drive information plateau in recent years, a fact that Sam Naffziger (Samuel.Naffziger@
growth into the future will have to be calls into question whether the pro- amd.com) received the B.S.E.E. de-
managing designer productivity in the cessor can continue as the driver gree from the California Institute
face of the complexity explosion. There of semiconductor and information of Technology, Pasadena, in 1988
is a practical limit to how large engi- technology growth. It is conceiv- and the M.S.E.E. degree from Stan-
neering teams can grow before indi- able that “good enough” processors ford University, California, in 1993.
vidual productivity drops too low, and will compete in the market only on He joined Hewlett Packard in 1988
management becomes impractical. the basis of price in the same way and spent eight years working on
Multibillion-transistor designs as DRAM or flash memory. various aspects of the PA-RISC
pro­duced by multihundred-engi- I believe, however, that there processor development, including
neer design teams already have a are many opportunities yet to be floating-point out-of-order execu-
lead time of five-plus years from exploited in processor design that tion and circuit methodologies. He
design specification to actually will enable the industry to avoid then became part of the Itanium2
shipping to the market. The chang- that fate for decades to come. Joint Development Team with In-
ing needs of consumers and the in- There is still a tremendous amount tel Corp., Fort Collins, Colorado,
formation technology community, of integration of system compo- and has led the design of both the
along with the rapid evolution of nents to be exploited for improved first Itanium2 processor (McKinley)
process technology, are making performance, power efficiency, and, most recently, the Montecito
such long design cycles increasing- and form factor. Exploitation of design. In 2006, he joined the Mile
ly impractical. the capabilities of dynamically High Design Center of Advanced
New approaches to processor adaptive processor designs has Micro Devices in Fort Collins, work-
design are needed that increase only started, and the application ing on next-generation processor
modularity to enable rapid design of design automation and modu- designs. He holds 72 U.S. patents
turns and that more effectively lar techniques to processor design on processor circuits and architec-
automate the path from high-level will enable more rapid design and ture and has authored over 20 IEEE
specification to transistor-level specialization for a changing mar- publications and presentations. He
implementation. This increase has ket. These directions will continue chairs the International Solid-State
been a goal of processor design to make microprocessor technol- Circuits Conference High-Perfor-
managers for many years, and the ogy a fascinating area for innova- mance Digital Subcommittee and is
pursuit of automation is not new, tion and value creation as the en- an AMD Senior Fellow.

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Applications may
be the edge of science
fiction, but they are
starting to happen,
although the challenges
are formidable.

© comstock & photo f/x2

T
he digital revolution, far from abating, continues with even
greater intensity in new applications in health, media, social
networking, and many other areas of our lives. These applica-
tions will require revolutionary improvements in speed and
capacity in future microprocessors so that they can process
terabytes of information with teraflops of terascale computing power.
Tera is not an exaggeration: trillions of hertz and trillions of bytes will be
by Justin Rattner
needed (Figure 1). In a terascale world, there will be new processing capabili-
ties for mining and interpreting the world’s growing mountain of data, and
for doing so with even greater efficiency.
Examples of applications are artificial intelligence in smart cars and ap-
pliances and virtual reality for modeling, visualization, physics simulation,
and medical training. Many other applications are still on the edge of science
fiction [1]. In these applications, massive amounts of data must be processed.
Three-dimensional (3-D) images in connected visual computing applications
like virtual worlds can include hundreds of hours of video, thousands of doc-
uments, and tens of thousands of digital photos that require indexing and
searching. Terascale computing refers to this massive processing capability
with the right mix of memory and input/output (I/O) capabilities for use in

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 ■■ It improves performance of the
circuit.
Tera-Scale Applications ■■ It reduces power consumption.

If occurrence of all these benefits

Performance Entertainment factors sounds too good to be true,
Travel it is nonetheless. We have enjoyed
and Learning the benefits for many decades now.
As the transistor scales down in
TIPS
size, it has to scale in all dimen-
Personal Media
sions. One major factor in the verti-
Model cal dimension is the scaling of gate
GIPS
Based insulator thickness. Innovation in
Index and Medicine scaling is now a combination of
Multitask Tera-Scale materials and dimension. Although
MIPS
Multimedia the transistor has been seamlessly
Multi-Core scaled over the last few genera-
KIPS Text Single-Core tions, the gate insulation (SiO2) has
Dataset Size become so thin that it has started
Kilobytes Megabytes Gigabytes Terabytes to leak as a result of tunneling cur-
rents. Does this mean the end of
scaling? Skeptics will say so, but
Figure 1: Terascale applications require increased performance and data set sizes. the innovators have invented the
high-k gate insulator with a new
metal gate structure, shown in
Figure 2. Also shown is a seven-
everyday devices, from servers to a patient’s health by interpreting layer copper and low-k dielectric
desktops to laptops. huge volumes of data in a scan and interconnection system. More re-
With a terascale architecture aid doctors in making real-time search (Figure 3) is under way to
computer, the user will partici- decisions. see if compound semiconductor
pate in a rich, immersive real-time Requirements of complex and transistors could provide benefits
collaboration in a virtual environ- compelling applications will pose in transistor scaling and perfor-
ment, with studio quality, photo- many challenges and will offer many mance. The high mobility of com-
realistic 3-D graphics. Or the user opportunities in the future develop- pound semi­­conductors offers the
will manage personal media by ment of microprocessors. potential to make transistors even
automatically ­a nalyzing, tagging, faster. Figure 3 shows additional
and sorting snapshots and home Challenges in Circuits and Processes examples of research, including
videos. Advanced algorithms will The technology scaling described by III-V materials, nanowires, carbon
improve the quality of movies Moore’s law provides three benefits: nanotubes, optical interconnects,
captured on older, low-resolution ■■ It doubles transistor integration and 3-D/trigate devices.
video cameras. An advanced digi- capacity every generation, there- Power supply voltage scaling
tal health application might assess by reducing the cost by half. however, has slowed down because
of a lack of threshold voltage scal-
ing. As supply voltage scales down-
ward, the threshold voltage of the
transistor has to scale down as
well. However, the subthreshold
Metal
leakage of a transistor increases
exponentially with reduction of the
SiGe SiGe High-k threshold voltage—and leakage has
SiGe SiGe
already reached its allowable lim-
its. This slowing down of supply
Silicon
voltage scaling will result in exces-
Copper + Low-k Strained Silicon High-k + Metal Gate sive power consumption. In order
(a) (b) (c) to keep power consumption un-
Figure 2: The new era of scaling: material innovation + dimensional scaling. (a) Copper + der control, circuit designers will
low-k, (b) strained silicon, and (c) high-k + metal gate. be forced to scale supply voltage

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in spite of a loss in performance.
Consequently, the frequency of
3-D FinFET III-V
operation of large designs will not Bonded
Thru-Si Top Thin
­continue to increase at the historic Structure
Via Wafer S
rate. Therefore the bulk of perfor- (TSV) D S
mance gain will have to come from
other means. An example is the use
G
of parallelism to exploit the abun- 5 µm Bottom Wafer
dance of available transistors. Computational Optical
In the past, the metal intercon- Lithography Metal Interconnect
nect system was deemed to be the
performance limiter due to higher h-k
Hig
resistance–capacitance (RC) delay. Ge
However, the lack of supply voltage
scaling is a greater limiter. In fact,
since clock frequencies will not
increase much, logic domains will
shrink in size, and interconnect- Cu
­related issues will be less challeng- Barrier
ing than previously expected.
Variability among transistors has Carbon
FBC Nanotube FET
also become worse because of ran-
dom dopant fluctuations and line
edge roughness. The latter is mostly Figure 3: Research directions in snapshot of semiconductor process and device research.
due to lithography challenges [2]. The
variability manifests itself as variation
in the threshold voltage, resulting in Challenges in Design for the last 20 years, the next 20
instability of static random-access In the last 30 years, Intel has deliv- years will require new approaches.
memory (SRAM) cells and variations ered dramatic performance gains by This is just one of the challenges
in circuit performance. These effects increasing the frequency of its pro- in core (CPU) and “uncore” (inter-
are well known, and work to deal cessors, from 5 MHz to more than faces, memory, and other compo-
with them by variation-tolerant cir- 3 GHz, while at the same time, nents outside the CPU) design for
cuit design is ongoing [3]. improving instructions per ­c ycle. terascale architecture.
As Figure 4 shows, the 193-nm
light source will be the workhorse
for lithography until the extreme ul-
In a terascale world, there will be new
traviolet (EUV) sources become prac-
ticable. The gap between light source processing capabilities for mining and
wavelength and the fine geometries interpreting the world’s growing mountain
being patterned requires a continued
tightening of design rules. While lay-
of data, and for doing so with even greater
out design rules have become more efficiency.
and more restrictive, these restric-
tions are expected to get even worse.
In the presence of severely restric- Recently, power and thermal Continuing to increase the per-
tive design rules, custom layouts will ­issues—such as dissipating heat formance of microprocessor hard-
likely result in a poorer layout than from increasingly densely packed ware within a fixed power budget
an automated layout—a paradigm transistors—have begun to limit will require more than just add-
shift. Design will then become fully the rate at which processor fre- ing cores. Energy efficiency of the
automated, from high-level specifica- quency can be increased. Mobile cores and their execution units
tion to layout. This shift will require clients, with their smaller form must increase commensurately.
tools to optimize the entire platform factors and server energy costs, Approaches such as the continued
itself. Interestingly, such tools will can be expected to increasingly reduction of supply voltage require
also make it easier to “port” process limit platform power and energy both circuit and core microarchi-
technology from one generation to budgets. Although frequency in- tecture research to provide the nec-
the next. creases have been a design staple essary resiliency [4].

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 complexity, and speculation are all
1 1,000
possibilities to achieve a more pow-
Lithography er-efficient, cost-effective terascale
Wavelength architecture. Additional specialized
248 nm
193 nm functions such as vector instruc-
tions will be useful in addressing
highly computation-intensive as-
Micron 0.1 100 nm
pects of emerging workloads.
65 nm Gap
For terascale processing, modu-
Feature 45 nm lar tile-based design methodolo-
Size 32 nm
EUV gies will be required. Monolithic
22 nm designs with their associated com-
13 nm
0.01 10 plexity, speed paths, clock-distri-
1980 1990 2000 2010 2020 bution challenges, and so forth
will be intractable.
Figure 4: The gap between subwavelength lithography and technology scaling.
Uncore Design
Bringing the terascale vision to
fruition requires the integration of
not only a large number of general-
Microprocessor development must ­purpose computing cores but also
meet many technical challenges to realize the uncore—special-purpose com-
puting engines (texture units,
the opportunity that these emerging shader units, and fixed-function
applications present. units, for example), and platform
elements, such as memory and I/O
controllers—into a single die. This
integration requires an on-die fabric
Core Design features that exploit instruction- that has scalable high-bandwidth,
Since Moore’s law predicts a con- level parallelism such as out-of- low-latency, and power-efficient in-
tinued increase in the number of order execution and speculation. terconnections to link the computing
transistors per chip for every new Unfortunately, experience bears and platform elements together. The
process generation, microproces- out diminishing returns expressed fabric must allow them to exchange
sor development must include ap- by Pollack’s rule: performance in- information with each other, access
proaches that exploit the use of crease is roughly proportional to memory, and communicate with the
additional silicon real-estate in the square root of the increase in rest of the system. Given the un-
power-efficient ways. complexity. As Figure 5 shows, core’s central nature, there are cer-
To increase instructions per cy- performance increases with only tain additional requirements such
cle, architects have taken advan- the square root of the area (that as partitionability, fault tolerance,
tage of the increased transistor is, complexity), while power con- validation and testing, regularity
budget Moore’s law provides, add- sumption increases linearly. Hence and flexibility, and design friendli-
ing microarchitectural support for alternative approaches to increase ness that need to be addressed [5].
performance become even more The addition of specialized func-
10 important. tions requires research on the best
Integer Perf (X)

One of the differentiating as- way to incorporate the functionality

Performance ~ Sqrt(Area)
pects of terascale architecture is so that it can be used (and reused)
large-scale core-level parallelism most effectively by software in new
Slope = ~0.5 combined with a core microarchi- and unanticipated ways. Large-grain
1 tecture that is optimized for highly fixed-function acceleration requires
1 10 parallel multithreaded workloads. heavy utilization to justify its inclu-
Area or Power (X)
Use of simultaneous multithread- sion. Finer-grained enhancements
Figure 5: Pollack’s rule: integer ­performance ing (multiple independent threads to the instruction set and reconfigu-
for new microarchitectures increases with of execution to better utilize the re- rable accelerator functionality offer
area. The graph plots integer performance
sources provided by the processor) the programmer more options.
increase against area and power increase
from the previous generation microarchitecture, to deal with memory latencies, re- The diversity of workloads
in the same process technology. ducing or eliminating out-of-order and concentration of computation

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r­ esources in terascale architec- I/O Design separate registers. The cores are in-
ture puts tremendous demands on With increasing levels of integra- order x86 scalar cores with short ex-
the cache hierarchy and coherency tion [8], the terascale microproces- ecution pipelines. Each core has fast
protocol. These demands require a sor truly becomes a full system on a access from the L1 cache and direct
flexible distributed (tiled) cache or- chip. This implies a need to provide connection to each core’s subset of
ganization that can adapt to work- system I/O such as Ethernet and di- the L2 cache. The prefetch instruc-
load demands. Such an organization rectly attached storage, as well as tion can load both the L1 and L2
must place minimal restrictions on interprocessor interconnects such caches. The vector processing unit
the software to fully realize the per- as QuickPath Interconnect (QPI) [9]. (VPU) comes with vector complete
formance potential. The associated
coherency protocol needs to be effi-
cient and scalable. It should also be
flexible in terms of the requirements Writing software to gain the full ­benefits of
it imposes on the building blocks of multicore processing and scale may be the
terascale architecture.
greatest challenge terascale
Memory Design architecture poses.
With substantial increases in the
computation power on a single die,
one faces the challenge of feeding Issues such as resilient distribution, instruction set—scatter/gather for
the device with enough data band- mapping of data flows to cores, and vector load/store—and mask regis-
width. For a small class of applica- a balance of the number of interfac- ters that select lanes to write, result-
tions where the memory footprint is es versus bandwidth of interfaces ing in data-parallel flow control and
small, the memory accesses result must all be resolved. enabling mapping of a separate ex-
in exercising the on-die caches. For ecution kernel to each VPU lane.
the majority of applications, a major Example of a Terascale Architecture
increase in off-chip memory band- The “Larrabee” architecture [10], Challenges in Software
width is required. shown in Figure 6, is Intel’s first Writing software to gain the full
This increase manifests itself in terascale architecture microproces- ­benefits of multicore processing
two ways: sor that is targeted at visual comput- and scale, with increasing paral-
■■ providing power-efficient, high- ing workloads. The cores communi- lelism, may be the greatest chal-
speed off-die I/O cate on a wide ring bus, resulting lenge terascale architecture poses.
■■ providing power-efficient, high- in fast access to memory and fixed- Parallel programming has been the
bandwidth access to dynamic function blocks and ensuring cache province of only a few experts in
random-access memory (DRAM). coherency. The last-level cache (L2) the server and high-­performance
The former has seen steady prog- is partitioned among the cores to computing communities because it
ress in the past decade but not at provide high aggregate bandwidth is difficult to develop and test. Pro-
the required pace. The latter may re- and allow for data replication and gramming even small-scale multi-
quire a new look at the system-level sharing. The Larrabee core has sep- processing (two to four processors)
memory repartition and optimiza- arate scalar and vector units with is a formidable task. The required
tion along with I/O design. Potential
solutions to address memory band-
width challenges include the higher Multithreaded Multithreaded
Display Interface
Fixed Function

density memory for embedded Wide SIMD Wide SIMD

applications, such as scaled float- I$ D$ I$ D$
ing body cell memory [6], and the
Memory Controller

Memory Controller

integration of a large DRAM cache

inside the processor package. Such
L2 Cache
an approach must provide a more
System Interface

efficient I/O channel that allows

Texture Logic

a higher bandwidth than the path

provided by dual in-line memory
Multithreaded Multithreaded
modules (DIMMs), which crosses the Wide SIMD Wide SIMD
package to the motherboard connec- I$ D$ I$ D$
tor. Examples include IBM’s work on
3-D integrated circuits [7]. Figure 6: Block diagram of the Larrabee graphics processing unit (GPU).

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synchronization leads to problems the more common shared memory Terascale architecture’s very high
with deadlock and race conditions model of SMP programming, we computation density combined with
that introduce very subtle, hard- need to provide the tools to sup- its fine granularity (each small core
to-reproduce errors. Tools to as- port programming models that have will have significant processing pow-
sist with multicore and existing been successfully employed in exist- er) will allow the flexibility to dedi-
programming are just beginning to ing parallel programming environ- cate resources to certain functions.
make inroads into this problem. ments. Examples are stream-based Examples are system management
Even with application software computing, map-reduce, and new lan- and single use devices—for example,
that is designed to exploit paral- guage extensions that abstract away appliances using Voice over Inter-
lelism, the system software, from concurrency, such as C for Through- net Protocol (VOIP). The dedicated
firmware through virtual machine put (Ct), a flexible, data-parallel pro- resources allow for an independent
managers and operating system to gramming language [13]. software environment. Together with
the managed run-time environment, The software challenge may also an on-die fabric having hardware per-
must be designed to avoid serializa- be addressed by adding features formance isolation, these resources
tion in ways that prevent scaling. to the processor. Acceleration of provide the quality of service needed
for flawless real-time media.
The modularity of a scalable fab-
With a terascale architecture computer, the user ric designed to support various num-
will participate in a rich, immersive real-time bers and types of compute elements
will allow reduced time to market.
collaboration in a virtual environment, with This support is made possible by
studio quality, photo-realistic 3-D graphics. the shipment of highly segmented
product with intermediate releases
of products that can be differenti-
For example, existing firmware ini- ­software transactional memory [14] ated via a new computation element
tialization sequences with extensive and support for debugging and cor- or core. The development of smaller
rendezvous of the processors are rectness [13] are just two examples building blocks that function within
already very time consuming and of such work. Moving forward, a key a regular fabric will allow for factor-
completely impractical for dozens aspect of microprocessor research ing of validation.
of cores. Operating system code cur- is to find other hardware features Of course, the greatest oppor-
rently optimized for small symmet- that simplify parallel programming. tunities for terascale architecture
ric multiprocessing (SMP, where two come from the continued improve-
or more identical processors con- New Opportunities ment of platform performance that
nect to a single shared main mem- While terascale architecture pres- has been an abundant source of in-
ory) must be carefully recrafted to ents many challenges, it also offers novation for the PC platform. New
scale with many more cores and ex- many unique opportunities as a applications with new capabilities
ploit the benefits of the high-speed consequence of its highly integrated and dramatically better human in-
on-die interconnects among cores. multicore design. One example is terfaces will be enabled by teras-
Legacy software and inherently the increased ability to deal with re- cale architecture.
single-threaded algorithms present liability challenges of future process
another challenge to terascale ar- technology characteristics. With Summary
chitecture. We must explore ways to many cores, the potential to main- We foresee a continuing digital revo-
incorporate heterogeneous general- tain spares will give new options for lution in health, media, social net-
purpose cores, both single-thread dealing with hard errors. Failed or working, and many other areas of
and multithread optimized types, deteriorating cores can be replaced our lives based on new and emerg-
into the architecture [11]. We must by using spares during testing or ing applications. These applications
also research the use of ensembles during the lifetime of the processor. will require revolutionary improve-
of simple cores to accelerate single Multiple cores or hardware threads ments in performance and capabili-
threads through thread-level specu- could be used for redundant com- ties in future microprocessors so
lation and other techniques [12]. putation for error detection. Small that they can process terabytes of
The programming environment cores will have a smaller area of information with teraflops of teras-
we take for granted, languages, de- confinement for defects, thereby re- cale computing power.
bugging, compilers, for example, ducing their impact. When combined In a terascale world, there will
must all be extended to address both with spare cores, this will dramati- be new processing capabilities
task parallelism (i.e., multithread- cally improve yields over designs for mining and interpreting the
ing) and data parallelism. Beyond with fewer, larger cores. world’s growing mountain of data,

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and for doing so with even greater inspire new extensions to micropro- Files/en-us/File/terascale/Whitepaper-
Ct.pdf
efficiency. Intelligent agents could cessor architecture.
[14] Saha, A.-R. Adl-Tabatabai, and Q. Jacob-
advise users in real time on stock The resulting discoveries and son, “Architectural support for software
trades and other financial deci- successes will not only shape the transactional memory,” in Proc. 39th
Annu. IEEE/ACM Int. Symp. Microarchitec-
sions. Such agents could search future of microarchitecture but ture, 2006, pp. 185–196.
massive collections of digital vid- will guide the capabilities of the [15] S. Chen, B. Falsafi, P. B. Gibbons, M. Kozuch,
T.C. Mowry, R. Teodorescu, A. Ailamaki, L.
eos to find specific people and underlying platforms and allow the Fix, G.R. Ganger, B. Lin, and S.W. Schloss-
events, and even edit a new vid- possibilities of the future to be- er, “Log-based architectures for general-
purpose monitoring of deployed code,”
eo based on what the user wants come a reality through revolution- in Proc. 1st Workshop Architectural System
to see. For gamers, there is the ary applications. Support Improving Software Dependability,
San Jose, CA, 2006, pp. 63–65.
obvious benefit of photo-realistic,
real-time graphics. The benefits go References
[1] P. Dubey, “A platform 2015 model: recog-
far beyond gaming: interactive vir- nition, mining and synthesis moves com- About the Author
puters to the era of tera,” Intel Technol. J.,
tual environments are now being vol. 9, no, 2, vi, Feb. 2005.
Justin Rattner (justin.rattner@in-
developed for both collaboration [2] S. Borkar et al., “Parameter variations and tel.com) is vice president and chief
and education, such as learning a impact on circuits and microarchitec- technology officer of Intel Corpora-
ture,” in Proc. ACM/IEEE Design Automa-
language by interacting with vir- tion Conf., Jun. 2003, pp. 338–342. tion. He is also an Intel Senior Fellow
tual native speakers, or learning to [3] S. Borkar, “Tackling variability and reli- and head of Intel’s Corporate Tech-
ability challenges,” IEEE Design Test Com-
deal with medical emergencies on put., vol. 23, no. 6, p. 520, Nov. 2006. nology Group. He directs Intel’s glob-
a simulated human body. [4] H. Kual, M. Anders, S. Mathew, S. Hsu, A. al research efforts in microproces-
Agarwal, R. Krishnamurthy, S. Borkar, “A
Microprocessor development must 320mV 56μW 411 GOPS/watt ultra-low- sors, systems, and communications,
meet many technical challenges to voltage motion-estimation accelerator in including the company’s “disruptive”
65nm CMOS,” in Int. Solid-State Circuits
realize the opportunity that these Conf. Tech. Dig., 2008, pp. 316–616. research activity aimed at replacing
emerging applications present. De- [5] D. N. Jayasimha, B. Zafar, Y. Hoskote, “On- existing dominant technologies. In
die interconnection networks: Why they
vice technology scaling continues are different and how to compare them,”
1989, Rattner was named scientist
to follow Moore’s law, with innova- Microprocessor Technology Lab, Corporate of the year by R&D Magazine for his
Technology Group, Intel Corp. [Online].
tions such as high-k gate insulation Available: http://blogs.intel.com/research/
leadership in parallel and distribut-
ensuring its continuation. However, terascale/ODI_why-different.pdf. ed computer architecture. In Decem-
the slowing of threshold voltage [6] I. Ban et al., “A scaled floating body cell ber 1996, he was featured as person
(FBC) memory with high-K+metal gate on
scaling and power constraints will thin-silicon and thin-BOX for 16-nm tech- of the week by ABC World News for
limit frequency as the basis for in- nology node and beyond,” in Proc. Symp. his visionary work on the Depart-
VLSI Technology, 2008.
creased performance. We must ex- [7] A. W. Topol et al., “Three-dimensional in- ment of Energy’s ASCI Red System.
ploit other means to achieve radical tegrated circuits,” IBM J. Res. Devel., vol. In 1997, he was honored as one of
50, no. 4/5, pp. 491–506, 2006.
increases in performance, such as [8] M. Azimi, N. Cherukuri, D.N. Jayasimha, the Computing 200 and profiled in
chip-level multiprocessing. An on- A. Kumar, P. Kundu, S. Park, I. Schoinas, the book Wizards and Their Wonders
and A. Vaidya, “Integration challenges
die interconnection fabric that pro- and tradeoffs for tera-scale architec- (ACM Press). He has received two
vides the requisite high bandwidth tures,” Intel Technology J., pp. 173–181, Intel Achievement Awards for his
Aug. 2007. [Online]. Available: http://
and low latency must be developed w w w.intel.com/technolog y/itj/2007/ work in high-performance comput-
to interconnect the cores. Feeding v11i3/1-integration/1-abstract.htm. ing and advanced cluster communi-
  [9] “Intel QuickPath Architecture.” [Online].
this level of computation power will Available: www.intel.com/technology/
cation architecture. He is a member
require corresponding increases in quickpath/whitepaper.pdf of the executive committee of Intel’s
power-efficient system memory ac- [10] L. Seiler, D. Carmean, E. Sprangle, T. For- Research Council and serves as the
syth, M. Abrash, P. Dubey, S. Junkins, A.
cess and I/O, requiring innovations Lake, J. Sugerman, R. Cavin, R. Espana, Intel executive sponsor for Cornell
in caches, memory devices, and Ed. Grochowski, T. Juan, and P. Hanrahan, University, where he is a member of
“Larrabee: A many-core x86 architecture
their interconnects. for visual computing,” in Proc. Int. Conf. the External Advisory Board for the
Multicore parallelism is visible to Computer Graphics Interactive Techniques School of Engineering. He is also a
(SIGGRAPH), Los Angeles, 2008.
software and requires multithread- [11] T. Li, D. Baumberger, D.A. Koufaty, and trustee of the Anita Borg Institute
ed concurrent programming—a new S. Hahn, “Efficient operating system for Women and Technology. Before
scheduling for performance-asymmetric
challenge to today’s mainstream pro- multi-core architectures,” in Proc. 2007 joining Intel in 1973, he worked at
grammers. Acceleration of single- ACM/IEEE Conf. Supercomputing, 2007, Hewlett Packard and Xerox. Intel
article 53.
threaded code and legacy-threaded [12] P. Marcuello and A. González, “Thread- named him its first principal en-
binaries will require new technol- spawning schemes for speculative multi- gineer in 1979 and its fourth Intel
threaded architectures,” in Proc. 8th Int.
ogy. New languages, programming Symp. High Performance Computer Archi- Fellow in 1988. He holds B.S. and
models, and methods will be devel- tectures, 2002, pp. 55. M.S. degrees from Cornell Univer-
[13] “Ct: A flexible parallel programming model
oped to better enable parallel pro- for tera-scale architectures.” [Online]. Avail-
sity in electrical engineering and
gramming which will themselves able: http://techresearch.intel.com/User- computer science.

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 people

Teresa Meng to Receive IEEE Donald O. Pederson Award

at ISSCC 2009

T
Teresa Meng will be presented with
the IEEE Donald O. Pederson Award
in Solid-State Circuits at the ISSCC in
February for “pioneering contribu-
tions to the development of
to demonstrate a single-chip GPS
receiver, which was based on the
use of power-optimized distributed
network protocols. She also “de-
veloped architectures and
achieve as much as an order of mag-
nitude improvement in performance.
More recently, her initial work in low
power wireless networks produced
novel results in network MAC pro-
integrated wireless commu- circuit techniques for low- tocols, CMOS imager architectures,
nications systems.” power video on-demand video signal processing, low power
According to her nomina- signal processing, result- electronics and dynamic power con-
tors, Prof. Meng is especial- ing in a single-chip digital trol. She has clearly demonstrated
ly admired for the extraor- camera dissipating only 10 that the greatest impact comes from
dinary breadth of her work mW. Her work on pyramid attacking problems at the system
and recognized internation- vector quantization dem- level, and she has a unique record
ally as an engineer, scholar, Teresa Meng onstrated that these algo- of accomplishment in merging ad-
and entrepreneur of excep- rithms are especially error vanced algorithm development with
tional distinction for innovations resilient while exceeding the actual implementations.”
in architectures, algorithms and compression capabilities Teresa’s leadership
low-power circuit designs for wire- of existing standards. at Atheros “combines
less communication systems. They In 1998, Prof. Meng the best of what we
said, “her research has had a major founded Atheros see in Silicon Val-
impact on both advanced signal C o m ­m u n i c a t i o n s ley: a revolutionary
processing and the implementa- Inc., the first com- vision, aggressive
tion of VLSI circuits and systems. pany to commer- technology that
She has a remarkable ability to in- cialize CMOS 802.11 stretches the enve-
tegrate innovations across a broad WLAN chips, where lope, and great lead-
range of sub-disciplines, exempli- she served as CTO un- ership,” said Stanford
fied by her visionary work on wire- til 2002. Dr. Meng was University President
less communications, which rang- the technical driving force John Hennessy. “From the
es from the development of energy and visionary behind the company, beginning, it was her ability to
efficient distributed network proto- now a market leader in wireless sys- see that the switch to a DSP-inten-
cols to the design of novel appli- tem solutions. sive approach, combined with the
cation-specific integrated circuits Prof. Meng, who is the Reid Weaver increased density and lower cost of
for implementing advance signal Dennis Professor of Electrical Engi- CMOS, could enable a major break-
processing algorithms.” neering at Stanford University, was through in the cost-effectiveness of
In her nomination for the Nation- also praised in the Pederson Award wireless communications,” he said.
al Academy of Engineering award, nomination for “seminal contribu- When Atheros was founded in 1998,
Class of 2007, Prof. Meng was cred- tions to asynchronous circuit design “it was a big leap—most of the ven-
ited for anticipating the growth of for digital signal processing and the ture capitalists and their technical
wireless networking by devising in- transmission of video signals over experts told us that the approach
novative system-level approaches lossy channels. In her research on was ahead of its time and would not
to communication over lossy chan- Viterbi decoders, she demonstrated be viable for five or more years. Te-
nels and was described as the first how parallel arithmetic could be resa was the one who saw that new
combined with radix-4 computa- techniques and methods would al-
Digital Object Identifier 10.1109/MSSC.2008.930945 tion and novel circuit techniques to low this leap to be taken.”

90 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Dr. Meng’s current interests are low-cost, low-power CMOS. When
neural signal processing, implantable ReCIpIeNTS oF THe Ieee Meng founded Atheros, many re-
medical devices, and non-invasive DoNAlD o. peDeRSoN AWARD searchers and engineers did not
stimulation. She has given plenary IN SolID-STATe CIRCUITS believe that an all-CMOS solution
talks at major conferences in the ar- 2008 Asad Abidi could be achieved. Today, that is
eas of signal processing and wireless 2007 Hugo de Man commonplace and virtually no
communications and is the author 2006 Mark A. Horowitz laptops and few desktops are sold
of one book, several book chapters, 2005 Bruce A. Wooley without wireless support.
and over 200 technical articles in 2004 Eric Vittoz Pederson Award nominators
journals and conference programs. 2003 Daniel Dobberpuhl deemed Prof. Meng’s GPS receiver
Dr. Meng, who is a Fellow of the IEEE 2002 Chenming Hu and Ping Ko “the world’s fi rst low-power imple-
and a member of the National Acad- 2001 [No Award] mentation suitable for personal
emy of Engineering, earned M.S. and 2000 Robert H. Krambreck uses. She pioneered the concept
Ph.D. degrees in EECS from UC Berke- and Stephen Law of low-power distributed wireless
ley, and a B.S. degree from National 1999 Kensall D. Wise networking with a vision that em-
Taiwan University. 1998 Nicky Lu braced GPS, WLAN and video on-
Dr. Meng has received many 1997 Robert W. Brodersen demand. Power efficiency improve-
awards and honors, including the 1996 Rudy J. van de Plassche ments in VLSI systems, realized
McKnight Technological Innovations 1995 Lewis M. Terman though architectures and designs
in Neurosciences Award (2007), the 1994 Paul R. Gray initiated by Professor Meng, have
DEMO@15 World-Class Innovator 1993 Kiyoo Itoh achieved 10-100X reductions in en-
Award (2005), the Distinguished 1992 Barrie Gilbert ergy consumption, thus enabling
Lecturer Award from the IEEE Sig- 1991 Frank Wanlass new applications of advanced sig-
nal Processing Society (2004), the 1990 Toshi Masuhara nal processing that have had a sig-
Bosch Faculty Scholar Award (2003), 1989 James D. Meindl nificant impact on both commercial
the Innovator of the Year Award by 1988 Karl Stein enterprise and national security.”
MIT’s Sloan School (2002), the CIO 1987 Robert Widlar Citing her work as an educator,
20/20 Vision Award (2002), and 1986 Barrie Gilbert they said, “Prof. Meng has an out-
was named one of the Top 10 Entre- 1985 Donald O. Pederson standing record of accomplishment
preneurs by Red Herring in 2001. as a teacher and advisor. She is an
In 1988, she received the Eli Jury innovative teacher, and her contri-
Award from the University of Cali- Based on her research into distrib- butions as an advisor and mentor
fornia, Berkeley. In 1989, she re- uted wireless networking and low- are evident in the outstanding stu-
ceived a Best Paper Award from the power GPS, Meng recognized that dents she has supervised. Many of
IEEE Signal Processing Society, an this could be achieved by moving to her graduates have become leaders
NSF Presidential Young in both industry and
Investigator Award, and academia.”
an ONR Young Investiga- The IEEE Donald
tor Award. “The story of Atheros under Teresa’s guidance combines O. Pederson Award,
During her first ten the best of what we see in Silicon Valley: a revolutionary which is administered
years at Stanford, Prof. vision, aggressive technology that stretches the envelope, by the Solid-State Cir-
Meng focused on low- and great leadership.” cuits Society Awards
power circuit and sys- John L. Hennessy, President, Committee, includes a
tem design, video sig- Stanford Universtiy bronze medal, certifi-
nal processing, and cate, and cash honorari-
wireless communi- um, presented at the an-
cations. For wireless nual meeting of the ISSCC
local area networks to move from a DSP-intensive, all CMOS approach. in San Francisco.
highly specialized applications to This approach offered a way to deal
broad deployment, they needed with the noisy and lossy channels —Katherine Olstein
to become more robust, less ex- in ad-hoc home and office environ- SSCS Administrator
pensive, and consume less power. ments, while permitting the use of [email protected]

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 91

K. Bernstein Presents “Double Feature” at SSCS-Denver

I
IEEE Solid-State Circuits Society Dis-
tinguished Lecturer Kerry Bernstein,
a senior technical staff member at
the IBM T.J. Watson Research Center
in Yorktown Heights, New York, de-
livered two lectures on the same af-
ternoon to members of SSCS-Denver
on 9 September, 2008. One lecture
was “New Dimensions in Microarchi-
tecture—3D Integration Technol-
ogy”; the other was “The Rise of an
Electronic Species.”
According to Chapter Chair Alvin
Loke, the meeting was a great hit.
“Besides being an amazing speaker,
what really made our interactions
so enjoyable was that Kerry is such
a down-to-earth and genuine per-
son! We really enjoyed his company.”
To add to the enjoyment of the day,
“Kerry actually reconnected with his Among the assemblage gathered to hear SSCS Dl Kerry Bernstein were: Natalie Barnes (wife
high school best friend from south of Bob Barnes, Denver’s chapter treasurer and vice chair for many years, Bob Barnes (who
Chicago, Humphrey, during his visit,” took this year off to pursue a pilot’s license), Stephen Kosonocky (one of Kerry’s former IBM
colleagues, now at AMD), Don Morris (past chapter speaker on globalization), Chapter Chair
he said.
Alvin loke, Kerry Bernstein, Visvesh Sathe (SSCS-Denver educational Activities officer, Bruce
Doyle (Chapter vice-chair), and Theodorus loke in the arms of his mother, Tin Tin Wee (Chapter
New Dimensions in treasurer and Web master).
Microarchitecture—
3-D Integration Technology talk follows announcements from and inversely, neuro-electronics is
IBM noting our development of this providing elegant tools which equip
Abstract breakthrough technology and its the life sciences. Perhaps, some
Despite generation on generation appearance on IBM’s technology day, machines may indeed become
of scaling, computer chips have roadmap. This talk will introduce organically intelligent, or humans
remained essentially two-dimen- 3-D concepts and their architectur- electronically supplemented. In the
sional. Improvements in on-chip al value and will offer a number of meantime, this new “electronic spe-
wire delay and in the total num- movies and animations showcas- cies” continues to evolve and become
ber of inputs and outputs have ing some of the capabilities that more and more adaptive, capturing
not been able to keep up with im- 3-D-enabled computing may offer increased human capability and
provements to the transistor, and in the future. gives us a lot to think about. This
it’s getting harder and harder to talk will include a number of movie
hide it! Three-dimensional (3-D) On the Rise of an clips demonstrating some of the ca-
chip technologies come in a num- Electronic Species pabilities of artificially intelligent
ber of fl avors but are receiving agents. It will be a wild, interdisci-
much attention lately as a means Abstract plinary ride for future engineers.
of extending CMOS performance. The human brain is vastly more Mr. Bernstein’s slide presenta-
Designing for three dimensions, complex than our best supercomput- tions for both talks may be found at
however, forces us to look at for- ers; yet it can be argued that both http://www.ewh.ieee.org/r5/denver/
merly two-dimensional integration systems evolve towards common sscs/past_events_2008.html.
issues quite differently. IBM as well underlying solutions to fundamen-
as other companies and research tal computer problems. Biologically —Alvin Loke
institutions are developing ways of inspired electronic technologies al- SSCS-Denver Chapter Chair
addressing these challenges. This ready are enabling new products, [email protected]

92 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

SSCS-DL Werner Weber Speaks at SSCS-Dallas
Focuses on the Impact of Economic Trends on MEMs Architectures

O
On 22 October 2008, Dr. Werner Weber
of Infineon Technologies presented
the talk “Industrialization of MEMS” at
a meeting of SSCS-Dallas held at Texas
Instruments, Inc., in Dallas.
About 30 local integrated circuit
designers attended as well as fac-
ulty members and students from
Southern Methodist University.
Microelectromechanical systems
(MEMS) have been a research focus
in academia and industry for many
years. MEMS is an important tech-
nology for the Dallas semiconductor
industry; digital light processing,
for example, which uses MEMS tech- Second from left, Dr. Gonggui Xu, General Chair of SSCS Dallas Chapter. To his left, Dr. Huawen
niques, brings in hundreds of millions Jin, Meeting chair of SSCS Dallas Chapter; Dr. Weibiao Zhang, treasurer of SSCS Dallas Chapter;
of dollars for Texas Instruments. and SSCS Dl Dr. Werner Weber of Infineon Technologies. To his first and third left,
In his talk, Dr. Weber presented Mr. Frank Huang, Intersil Corporation, and Dr. ping Gui, program chair of SSCS Dallas Chapter.
a short overview of the technical
concepts used today and provided gyro sensors, and inkjet printer Many attendees asked deeper and
information about important eco- heads were discussed, as well as broader questions afterwards.
nomic trends in the field. Chief various future applications and
MEMS architectures, such as digital technology concepts. —Dr. Gonggui Xu
mirror devices, bulk acoustic wave Dr. Werner’s talk inspired numer- General Chair, SSCS Dallas Chapter
devices, pressure, acceleration and ous questions during its course. [email protected]

SSCS DL Behzad Razavi Addresses SSCS Taipai Chapter

Shares Expertise on Systematic Transistor and Inductor Modeling for Millimeter-Wave Design

T
The heightened interest in milli-
meter-wave applications such as
broadband wireless links, radars,
and imaging systems has led to
extensive research in CMOS circuit
and architecture design for these
frequencies. However, typical para-
sitic extraction tools used in post-
layout simulations prove inade-
quate because they do not take into
account frequency dependencies
or distributed effects. A systematic
method of modeling the CMOS to About 150 people attended a lecture by prof. Behzad Razavi at National Taiwan University,
enhance the simulation accuracy of Taipei, on 11 September 2008.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 93

 Prof. Razavi began with an in-
troduction to the MOS physical
structure for nanoscale CMOS tech-
nologies. He then described the
parasitic capacitance due to metal-
lization, which was not important
in older CMOS technologies. Follow-
ing that, he proposed a simulation-
based modeling methodology to
provide greater flexibility in the de-
sign and layout of millimeter-wave
CMOS circuits than measurement-
based models do. Furthermore, he
described a physical model for the
metallization capacitances of the
UClA professor Behzad Razavi presents the lecture “Systematic Transistor and Inductor Mod- transistors and new layout tech-
eling for Millimeter-Wave Design” at National Taiwan University, Taipei, 11 September 2008.
niques that exploit these capaci-
tances to improve the circuit per-
millimeter-wave circuits becomes About 150 attendees showed up at formance. He illustrated several
crucial. To address this important Dr. Razavi’s talk, held at National Tai- design examples with operation
issue in high-frequency circuit de- wan University on 11 September, 2008. frequencies from 40 GHz to 130
sign, the SSCS Taipei Chapter in- The numbers from industry and aca- GHz to verify the proposed model
vited Prof. Behzad Razavi of UCLA, demia were about ten and 140, respec- during the course. Many considered
USA to give a talk on the modeling tively, indicating that this topic drew his presentation course valuable for
of nanoscale CMOS technologies. more interest from local universities. their research.

Engineering Textbook Tops 1 Million in Sales

O
On 29 September 2008, the Faculty
of Applied Science and Engineer-
ing of the University of Toronto
unveiled a unique recognition wall
in its Bahen Center Atrium. The
ment, it is important
to note that Canada
graduates only about
11,500 engineers
and the entire world
Microelectronic
Circuits has been
translated into nine
languages and is
used today by eight
imaginative glass structure pays 1 million engineers out of ten students
homage to past and present facul- per year. worldwide in their
ty who have published engineering According to second and third
textbooks. Prominent among this Patrick Lynch, edi- years of electrical
group is IEEE Life Fellow Kenneth torial director at engineering. Since its
C. Smith, Professor Emeritus and Oxford, “This suc- publication in 1982,
alumnus of the university, as well cess is proof of this leading textbook
as the ISSCC Press Relations chair, the enduring and has set the standard
and his co-author Prof. Adel Sedra, significant contri- in excellence and
IEEE Fellow, former University of bution Adel Sedra innovation, and re-
Toronto vice-president and pro- and K.C. Smith have made to en- mains the most current resource for
vost, and currently dean of engi- gineering education worldwide. teaching tomorrow’s engineers how to
neering at the University of Water- Today, their book is the gold stan- analyze and design electronic circuits.
loo. They recently celebrated the dard by which universities and The University of Toronto’s Facul-
1 millionth sale of their textbook industries around the world judge ty of Applied Science and Engineer-
Microelectronic Circuits, in its fifth the quality of an electrical engi- ing has established itself as a leader
edition (Oxford University Press). neer’s education. Oxford Univer- in engineering education, mainly due
To truly understand the signifi- sity Press is immensely proud to to its faculty, who have written hun-
cance of Smith and Sedra’s achieve- work with these authors.” dreds of textbooks that have shaped

94 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

and inspired past, current, and fu-
ture generations of engineering lead-
ers around the world. Their tireless
efforts as outstanding engineering
educators have helped the faculty
achieve an unprecedented number of
awards for education and teaching.
Esclating textbook authorship in
education is probably one of the most
important things that faculty should
be encouraged to support, Smith said
in an interview. “It is regrettable that
the importance of such contributions
to education is generally not recog-
nized by university administrators
and granting agencies. The ‘Recogni- In a ceremony at the University of Toronto on 29 September 2008, Dean Cristina Amon con-
tion Wall’ at the University of Toronto gratulated professor emeritus Kenneth C. Smith (left) and former provost Adel Sedra on the
serves as a tangible and continuing millionth sale of their textbook Microelectronic Circuits.
symbol of our commitment to this im-
portant aspect of education,” he said. For more information on textbooks
From its beginning in 1873, the written by the University of Toronto’s
Faculty of Applied Science and En- Faculty of Applied Science and Engi-
gineering at the University of To- neering professors, please visit: www.
ronto has earned an international engineering.utoronto.ca/information-
reputation for quality teaching and for/textbooks.htm.
is known as a forward-thinking and
crucial resource regarding world —Jennifer Hsu
concerns. It is through the energy of Communications Coordinator
its professors that it has been able to Alumni and Development
produce an environment where indi- Faculty of Applied Science and
viduals with creativity and commit- Engineering University
ment can come together as leaders to of Toronto
fulfill ambitious goals. [email protected]

Tools: Tips for Making Writing Easier

Part 4: Break Out of the Endless Editing Cycle

F
For many business writers, editing be-
comes the most time-consuming task
in the writing process. There are three
main reasons for this: 1) an unsystem-
atic approach to editing that leads to
As we show you in this column,
you can speed up editing by follow-
ing a systematic approach based on
two simple principles:
1) Work from the large picture to
like the figure. There are several
problems with such an unsystem-
atic approach:

procrastination and wasted steps; 2) a the small detail, rather than ran- This article is reprinted from the
feeling of incompetence or insecurity, domly or from small to large. September/October 2003 issue of
leading writers to keep revising until 2) Stop when you reach the last step. the IEEE PCS Newsletter, vol. 47,
they find something that seems safe; no. 5, pp. 11, 13, with permission
and 3) a lack of priorities—in particu- A Common Problem: from the authors and from the
lar, a failure to see when timeliness The Endless Editing Cycle IEEE Professional Communication
becomes more important than turning Many writers follow a haphazard Society newsletter editor.
out a perfect piece. editing cycle that looks something

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 95

■ Each step involves a decision on through grammar and spelling
what to do next. This takes time checks at the end. Ordinarily,
and energy. Avoid the endless cycle there should be no need to go
■ It is hard to find a stopping point
of editing by following a through any second or third
because some late-cycle editing
systemic top-down approach. round of editing.
may require further editing for ■ None of your editing is wasted. For

grammar and spelling. For ex- example, any grammar changes

ample, the belated decision to will be applied only to passages
move points around and create • Use headings and lists for easy you have fi xed for content, orga-
new transitions may call for fi xing reading. nization, and style.
grammar, punctuation, and spell- • Cut out annoying repetition. Next time you are tempted to rush
ing errors in the new transitions. 4) Edit for style and tone. into wild editing, stop for a mo-
■ A lot of editing is wasted. For ex- 5) Fix grammar errors. ment and remember the one-pass
ample, you may fi x many gram- 6) Correct punctuation and spell- approach. It may cut your editing
mar errors in sentences that you ing; proofread. time in half.
later decide to delete because they Notice how this avoids the problems
hold no interest for the readers. inherent in the cyclical approach: Peter and Cheryl Reimold
■ There are no ad hoc decisions to www. Allabout communication.com
Editing in a Systematic be made about the next editing
One-Pass Sequence step— the sequence is purely rou- Cheryl and Peter Reimold have been
Instead of editing haphazardly in a tine. You can concentrate all your teaching communication skills to
never-ending cycle, follow a single ra- effort on editing, rather than on engineers, scientists, and business
tional sequence that moves from the thinking about editing. people for more than 20 years. Their
large picture to the fine detail. Here is ■ It’s clear when to stop editing: firm, PERC Communications (+1 914
the general outline of this process: when you’ve completed the 725 1024, [email protected]), offers
1) Check the general impression. last, most detailed step. For businesses consulting and writing
Will this get the desired result? instance, transitions created services, as well as customized in-
2) Sharpen the message. by reorganizing will be fixed house courses on writing, presenta-
3) Fix the organization: for style and then for grammar tion skills, and on-the-job commu-
• Put the main message first. and spelling when you get to nication skills. Visit their Web site
• Order points according to the that phase. Similarly, any style at http://www.allaboutcommunica-
reader’s needs. changes you make will be put tion.com.

Sansen Sparks Chapter Formation in Oregon

T
Two dozen local design engineers
attended an evening lecture in
Beaverton by SSCS President Willy
Sansen on 1 October 2008. His topic
was “Analog IC Design in Nanometer
CMOS Technologies.”
Known as
the “Silicon For-
markably successful. High-tech em-
ployment in the state reached a peak
of almost 73,000 in 2001 but has de-
clined nearly 20% to 58,000 in 2008.
The Oregon Section is consider-
est” since the ing forming an SSCS Chapter. Local
early 1980s, the members interested in assisting its
Portland met- formation should contact Section
ropolitan area Chair, Gary Hinkle, gary@auxilium-
has hosted pio- inc.com. The state already has a an
neers like Intel, SSCS student branch in Covallis at
Tecktronix, and Oregon State University, about 115
Mentor Graph- km south of Portland.
ics as well as
a nu m b e r of —Anne O’Neill
spi n - of fs or SSCS Executive Director
SSCS president Willy Sansen speaks to the oregon Section on 1 octo- start-ups that [email protected]
ber 2008. have proven re-

96 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 con ference reports

ICMTS Comes to California

T
The IEEE is sponsoring the 22nd
2009 International Conference on
Microelectronic Test Structures (IC-
MTS) on 30 March–2 April to bring
together designers and users of test
rope, Asia, and the United States in a
three-year cycle.
Original papers presenting new
developments in silicon, compound
semiconductor, MEMS, and nanotech-
■■ foundry/fabless interface strate-
gies and design for manufactur-
ing (DFM)
■■ manufacturing of integrated cir-

cuits
structures to discuss recent devel- nology microelectronics test struc- ■■ measurement of manufacturing

opments and future directions for ture research, implementation, and variance
the use of test structures in all areas applications as well as test struc- ■■ device and circuit modeling

of semiconductor technology assess- tures aimed at new materials and de- ■■ device matching

ment. This year’s ICMTS conference vices characterization are presented. ■■ RF measurements

will be held at the Embassy Suites Papers are selected based upon the ■■ measurement utilization strategy

Mandalay Beach Resort in Oxnard, merit of the work and to demonstrate ■■ reliability and product failure

California, USA. the broad spectrum of test structure analysis

Over the years, ICMTS conference design and use by a worldwide com- ■■ nanotechnology, displays, MEMs,

sessions have included test struc- munity. Example areas include: sensors, and emerging devices.
tures concerned with, for example, ■■ technology R&D, yield enhance- All lecture sessions are held
overall circuit yield, device variabil- ment, process integration, and ­sequentially as one track, with
ity, device modeling, and design for production process control ample time for fruitful discussion
manufacturability (DFM), all areas
of interest to the IEEE Solid-State
Circuits Society (SSCS). As such, in
2008, the SSCS began a technical co-
sponsorship of the conference.
Since 1988, ICMTS has provided
a forum for the test structure de-
sign and user community to meet
and discuss important challenges
and report on the most recent de-
velopments in this field. To this end
ICMTS focuses on the design, fabri-
cation, and characterization of test
structures for process and material
evaluation, reliability and process
failure analysis, manufacturing pro-
cess control, device and circuit mod-
eling, sensors and devices as well as
associated measurement techniques
and data analysis. ICMTS is one of
the few international IEEE-sponsored
conferences that move between Eu-

This year’s ICMTS conference will be held at the Embassy Suites Mandalay Beach Resort in
Digital Object Identifier 10.1109/MSSC.2009.931849 Oxnard, California, USA, on 30 March – 2 April 2009.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 97

among delegates to the conference. tual Air Force One used by President ment, and road trips to the central
The Technical Program Commit- Reagan. An optional post-confer- California wine country or along
tee will present a Best Paper award. ence excursion will be announced at the famed Pacific Coast Highway.
A one-day tutorial short course on a l­ater date. For those with further interest
micro­electronic test structures will Oxnard, California provides a in microelectronic test structures,
precede the conference on 30 March. beach front hotel for this year’s past ICMTS conference proceedings
There will be an equipment exhibi- conference and has average year- are available from the IEEE. More
tion room relating to test structure round high temperatures between information can be found at http://
measurements. The conference 66-74 ºF. Located 60 miles north- www.see.ed.ac.uk/ICMTS/.
banquet will be held on Wednesday west of Los Angeles, the Oxnard
night at the Ronald Reagan Presiden- area provides opportunities for —Greg Yeric
tial Museum, including a tour of the whale watching, boat trips to the General Chair, ICMTS 2009
museum and a walk through the ac- Channel Islands National Monu- [email protected]

VLSI-TSA/DAT 2009 to Meet in Hsinchu, Taiwan

Conferences Will Overlap on Two Days with Joint Keynotes

O
On 27–30 April, the 2009 Internation-
al Symposium on VLSI Technology,
Systems, and Applications (VLSI-TSA)
and the International Symposium on
VLSI Design, Auto­mation and Test
other’s capabilities and limitations
while jointly optimizing perfor-
mance,” Dr. De Keersmaecker said.
A joint plenary session and awards
and chief technology officer of NXP,
The Netherlands.

Special VLSI-TSA Sessions

on Power Consumption
(VLSI-DAT) will meet at the Ambas- Two special VLSI-TSA sessions on
sador Hotel in Hsinchu, Taiwan. green devices and on next gen-
SSCS cosponsors both conferences. eration lithography will address
Beginning in 1983 as a biennial the issue of power consumption,
meeting organized by the Indus- which has become the most im-
trial Technology Research Institute portant challenge in VLSI technol-
(ITRI), VLSI-TSA has become one of ceremony on the morning of April ogy today. “Green” devices that
the major VLSI symposia worldwide, 28th will feature keynote addresses consume very little operating and
particularly in the Asia Pacific re- by Dr Fang-Churng Tseng, chair of standby power are being explored.
gion. As the result of explosive de- Taiwan Semiconductor Manufac- Next-generation lithography tech-
velopments in IC design throughout turing Co., Ltd. and Global Unichip nology is instrumental in realiz-
this area, the International Sympo- Corp., Taiwan, and Dr. Rene Pen- ing the continuous improvement
sium on VLSI Design Automation and ning de Vries, senior vice president in density that is demanded by
Test (VLSI-DAT) split from VLSI-TSA Moore’s Law. In a special TSA ses-
in 2006 to focus on research in the sion, experts on next generation
field of IC design, design automation lithography will present the latest
and testing related topics. developments in 32-nm technol-
According to VLSI-TSA General ogy nodes and beyond.
Chair Dr. Roger De Keersmaecker, The VLSI-TSA program will cover
the organizing committees of VLSI- all aspects of VLSI technology, sys-
TSA and VLSI-DAT decided the sym- tems and applications. Pertinent
posia would overlap on 28–29 April facts include the following:
VLSI-TSA/DAT 2009 will present a joint
to stimulate interactions between ■■ There will be two keynote speak-
plenary session and awards ceremony with
the technology and design commu- keynote addresses by Dr. Rene Penning ers, Dr. Mark Pinto, chief technol-
nities; attendees registered for either de Vries, senior vice president and chief ogy officer, senior vice president
symposium will be able to attend technology officer of NXP, The Netherlands, and general manager of the En-
(left) and Dr. Fang-Churng Tseng, chair of
presentations at both during these ergy and Environmental ­Solutions
Taiwan Semiconductor Manufacturing Co.,
two days. “In state-of-the-art chip Ltd. and Global Unichip Corp., Taiwan. (Dr. division of Applied Materials, USA,
development, technology and design Tseng’s photo courtesy of Taiwan Semicon- and Prof. Ken Uchida of the Tokyo
must increasingly be aware of each ductor Manufacturing Co., Ltd.) Institute of Technology, Japan.

98 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

■■ Special sessions will be presented ■■ Two industrial sessions will pres-
on green devices and on next gen- ent up-to date research results:
eration lithography. building the next-generation high-
■■ There will be invited talks on performance CPU and breaking
FEOL, memory, BEOL, and CMOS. through the chip-to-chip intercon-
■■ Two parallel in-depth short cours- nect wall.
es on SIP & 3D IC and nonvolatile ■■ There will be four half-day in-

memory will be presented. depth tutorials.

■■ There are approximately 50 con- Keynote speakers at VLSI-TSA 2009 will ■■ There are approximately 70 contrib-

tributed ­papers. be Dr. Mark Pinto, chief technology officer, uted papers.
senior vice president and general manager
For more details about the con-
of the energy and environmental solutions
VLSI-DAT Industry Sessions on division of Applied Materials, USA (left) and ference agenda, please visit our con-
High Performance CPUs and Prof. Ken Uchida of the Tokyo Institute of ference Web sites at vlsitsa.itri.org.
Chip-to-Chip Interconnection Technology, Japan. tw (for VLSI-TSA) or vlsidat.itri.org.
Under the leadership of Confer- tw (for VLSI-DAT).
ence Cochairs General Director VLSI-DAT will cover all aspects of For registration, please register
Cheng-Wen Wu and Prof. Tzi-Dar VLSI design, automation, and test. at vlsitsa.itri.org.tw (for VLSI-TSA)
Chiueh, Technical Program Chair Pertinent facts include the following: or vlsidat.itri.org.tw (for VLSI-DAT)
Prof. Kuen-Jong Lee, and Cochair ■■ Keynote addresses will be given by upon your preference. Should you
Prof. Tim Cheng, 2009 VLSI-DAT Dr. Fang-Churng Tseng, vice chair have any further questions about
will feature an exciting program of Taiwan Semiconductor Manufac­ registration, please contact the con-
with special sessions on electron- turing Co., Ltd. and Prof. Jan Ra- ference registrar, Ms. Yvonne Chen
ic system level design, high-fre- baey, director of Gigascale Systems at +886-3-5913003 or e-mail HRD@
quency/very low power RF/analog Research Center at the University of itri.org.tw for assistance.
circuits and silicon debugging/ California, Berkeley.
design validation. Industry ses- ■■ There will be three special ses- —Clara Wu and Elodie Ho
sions include “Building the next- sions: high-frequency/very-low Symposia Secretariat
­­Generation High-Performance CPU” voltage RF/analog circuits, silicon [email protected]
and “Breaking Through the Chip-to- debugging/design validation, and [email protected]
Chip Interconnect Wall.” electronic system level.

Associate Editor’s View (continued from page 6)

the world. But China’s stock market of the Taiwan electronics industry. we—at the moment—we still have re-
often moves to its own beat, without However, Taiwan regulates finan- strictions on our people purchasing
regard for broader economic condi- cial activities by setting limits that overseas mutual funds. If the fund has
tions, reflecting the fact that it is still make it impossible for a mainland more than 0.4% invested in the main-
relatively immature. enterprise to go public in Taiwan. land, then it is not supposed to be sold
According to Ping Ko, the presi- However, Eric Chu, vice president in Taiwan. That [has] actually forced
dent and CEO of Silicon Federation of WK Technology Fund, one of the billions, hundreds of billions, out of
International, Inc., a Shanghai-based largest venture capital firms in Tai- Taiwan. We hope to call them back. If
venture capital firm specializing in wan said, “Things are changing and I we change the current rules, I’m sure
the China IC industry, “All factors con- won’t be surprised if a Camen or a BVI many of them [investors] would like
sidered, including investors’ interests company with most operations on the to do the transaction right in Taiwan.
and maturity, stock market regula- mainland can go public in Taiwan in That is why we think if we are able to
tion and management, listing and the foreseeable future.” do that, we may become the assets
maintenance costs, the Taiwan stock Eric could very well be right, if the management center of Asia.”
market is no doubt the best place for newly elected leader of Taiwan, Ma Ambitious as this is, let’s remain
China IC design houses to go public.” Ying-jeou, can actually achieve what hopeful that another exit option
Indeed, most Taiwanese IC compa- he promised during his campaign. In could eventually be made available
nies went public on the Taiwan Stock interviews published by The New York to China IC design companies.
Market, and investors there embraced Times and The International Herald Tri-
these companies, large or small, with bune on 18 June 2008, Mr. Ma said, “We —Pengfei Zhang
great enthusiasm. As a result, the certainly will deregulate our financial Beken Corporation, Shanghai
Taiwan domestic stock market has services industry, and to attract back [email protected]
been a cornerstone of the prosperity the capital that flew out, you know,

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 99

 chap ters

India Council Chapter Formed in April

Focus on India a Primary IEEE Objective

U
Until this spring, India had only one
Solid-State Circuits Society Chapter,
in Bangalore, attached to the Karna-
taka section and serving members in
that region. There was no pan-India
later. Its goals are to serve members
and reach out to wider audiences in
numerous states of the country to
give professionals the opportunity
of inclusiveness.
ences but also to enhance society
membership, generating a volun-
teer force across the country. We
hope to seed and sustain regional
groups that might blossom into
SSCS chapter with jurisdiction over To draw current members and stu- independent chapters. We would
all regions of the country that could dents, faculty and pre-college audi- like to increase academia-indus-
take initiatives, build activities, and ences to Chapter activities, the new try-chapter linkages and empower
create base seeds for future growth, chapter has already pursued many students at pre-college and science
despite the fact that the country has initiatives over different regions of and engineering college levels with
28 states. the country foundational including various technical programs and in-
Seeing this vital gap, an initia- lectures, a National Festival of Sci- frastructural supports to encourage
tive was taken to motivate and mo- ence and Engineering Schools (NFS- their growth. In addition, the chapter
bilize a large band of professionals ES), an SSCS DL lecture program, and hopes to be able to provide mentor-
to join IEEE and SSCS, spearhead- an IEEE STAR program for outreach ing and generate experienced lead-
ing the chapter formation process to women at school levels. To pro- ers to serve IEEE, enabling the huge
with the IEEE India Council and IEEE mote hardware design ­talents at col- community of non-member profes-
headquarters to create the new India lege levels, we have also established sionals and students in the country
Council SSCS Chapter. As a result, several awards with certificates of to witness first-hand the benefits of
the India Council Chapter of the merit for best paper presentations being IEEE and Society members. In-
Solid-State Circuits Society received in the field. dia Council chapter’s ExCom draws
SSCS headquarters’ approval in April Over the next decade, the chap- active member talent from different
2008 and IEEE approval two months ter intends not only to support regions; though its operating head-
technical events such as lectures, quarters and management of its
Digital Object Identifier 10.1109/MSSC.2009.931850 seminars, workshops, and confer- activities across the country center
presently in Delhi.
Under the aegis of IEEE India and
its state Sections, several technical
chapters operate in India, providing
links to thousands of engineering
professionals across the country
and serving the purpose of expos-
ing them to a range of activities
conducted by the chapters within
their jurisdictions. The chapter-
conducted events give attendee
members and non-members the
opportunity to interact, network,
exchange ideas, and get exposed to
world trends to keep abreast of fast
changes, as well as an opportunity
SSCS-India Council’s Chapter founding Chair (right) and Vice-Chair Dr. Madheswaran at the to serve the technical community
head of the table at the chapter’s foundational meeting. and society at large.

100 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

Focus on India a
Primary IEEE Objective
IEEE President Lew Terman has cho-
sen “Focus on India” as a primary
initiative.
Over the past two decades, India
has made substantial progress in all
fields, with economic and industrial
fronts emerging as a dominant force,
not only in the Indian sub-continent
but also in Asia, and over the world
stage. The country has enjoyed a
growth rate of over 8% for the past
few years and is inching towards
On the dais at SSCS-India Council and MEC’s NFSES meeting: Chapter Chair
becoming a major economic power-
Kandala Chari ( third from left) with Ms. Nirmala (Organizing Secretary) and Dr. Madheswaran
house. A huge middle class of over (Principal MEC, Organizing Chairman) at the microphone.
350 million has emerged.
India houses over 350 Fortune
500 companies, having become an
attractive destination for global
multinational companies in vari-
ous domains. Around 150 of these
specialize in electronics, micro-
electronics and nanotechnologies
employing over 80,000 engineers.
India has established a good infra-
structure for electronics hardware
manufacturing and has instituted
promotional policies for boosting
the sector further. The country is
also becoming a knowledge process Chapter Chair Kandala Chari speaking at an SSCS-India Council workshop in Pune, the sec-
outsourcing hub for global supports ond largest city in the state of Maharashtra in western India, with University of Pune faculty
and cost effective R&D and has thriv- members on the dais.
ing IT and communication, space and
nuclear programs, having become dian Institute of Management, and manpower, a large and highly skilled
a global leader in software services the Indian Institute of Information talent pool, a world class infrastruc-
with homegrown firms becoming Technologies. These top-end aca- ture in communication and IT (CIT), a
multinational companies listed un- demic ­institutions provide a world huge untapped local market, robust IP
der NASDAQ. India is also a leading class infrastructure for study and laws and a proven judicial system.
automobile manufacturer in Asia. research. Alumni from many of
As a result, India presents a huge these occupy positions of eminence IEEE SSCS—A Key Enabler
market and growth opportunities within the country and global mul- As India marches on its journey with
for variety of businesses. tinationals. The Delhi region alone a huge scientific work force, the IEEE
has dozens of colleges and an IIT. and SSCS in particular can play key
Top-End Academic Institutions India has 28 states and four admin- roles to the country by bringing
­Provide a World-Class Infrastructure istered regions. experts exposures, mentoring and
for Study and Research By virtue of its thrust for educa- otherwise assisting young talent,
Around 2,500 engineering colleges tion, India has become a dominant hu- and promoting interactions among
generate over 5,00,000 UG and PG man resource creator and knowledge members through their activities
holders in different regions of coun- processor. A huge pool of scientific for continued growth and a positive
try each year. The country has doz- and engineering talent is the back- contribution to society.
ens of word-class academic institu- bone of local industry and global mul-
tions, including the famed Indian tinational companies operating out of —Kandala Chari
Institutes of Technologies (IITs), the the country. India possesses several India Council Chapter Chair
Indian Institute of Science, the In- unique attributes including low cost [email protected]

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 101

Michael Perrott Speaks at Santa Clara Valley Technical Meeting

I
In a presentation for SSCS’s Santa
Clara Valley chapter on 16 October
2008, Dr. Michael H. Perrott discussed
the implementation advantages pro-
vided by digital phase-locked loops
compared to their analog counter-
parts and explored the question of
whether such digital structures can
support high-performance applica-
tions in which low jitter and high PLL
bandwidth is required by discussing
techniques for achieving high perfor-
mance digital fractional-N synthesiz-
ers. Dr. Perrott was an assistant and
then associate professor of electrical
engineering and computer science at
the Massachusetts Institute of Tech-
nology from 2001 to 2008. He is now
with SiTime, a Silicon Valley startup Dr. Michael Perrott of SiTime, Sunnyvale, California, presented a talk on “High Performance
developing silicon timing, clock, and Digital Fractional-N Frequency Synthesizers” to members of SSCS-Santa Clara Valley at their
RF chips, which incorporate micro- October meeting.
electromechanical systems (MEMS)
timing reference devices inside stan- A key question, however, is whether synthesizers, including high resolu-
dard silicon electronic chips, elimi- such digital structures can support tion time-to-digital conversion, digi-
nating the need for quartz crystals. high performance applications in tal quantization noise cancellation,
Dr. Perrott received the B.S. degree and low-jitter divider structures. He
in electrical engineering from New reported that measured results of a
Mexico State University, Las Cruces, prototype demonstrated that < 300
in 1988, and the M.S. and Ph.D. de- A key question, however, fs of rm jitter can be achieved with
grees in electrical engineering and is whether such digital a relatively high PLL bandwidth of
computer science from Massachu- structures can support high 500 kHz. Slides from Dr. Perrott’s
setts Institute of Technology in 1992 performance applications in talk are available online at www.
and 1997, respectively. which low jitter and high PLL ewh.ieee.org/r6/scv/ssc/Oct08.pdf.
bandwidth is required. In November, Dr. Boris Murmann
Abstract addressed the group on “Future Di-
Digital phase-locked loops provide rections in Mixed-signal IC Design.”
many implementation advantages The Santa Clara Valley Chapter chair
compared to their analog counter- which low jitter and high PLL band- is Dan Oprica.
parts by avoiding large capacitors width is required. In his talk, Dr. Per-
for loop filters and the complica- rott addressed this question by dis- —Katherine Olstein
tions of designing analog-intensive cussing techniques to achieve high SSCS Administrator
components such as charge pumps. performance digital fractional-N [email protected]

102 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

SSCS-Scotland Hosts Technical Meeting
Willy Sansen Speaks on Challenges for Analogue Design in Deep Submicron CMOS

As a side meeting to the 38th European

Solid-State Device Research Conference (ES-
SDERC) and the 34th European Solid-State
Circuits Conference (ESSCIRC), which were
held in Edinburgh from 15–19 September
2008, the Scottish chapter of SSCS held
a technical meeting attended by over 50
people from local industry and academia.
Professor Willy Sansen of K.U. Leuven talk-
ed about the Society and about challenges
and opportunities for analogue design in
deep sub-micron CMOS. As always, Prof.
Sansen captivated the audience with his
knowledge and enthusiasm for analogue
design.
From left: SSCS-Scotland members Keith
Findlater, Robert Henderson, John Pennock,
Franck Banag, Seyed Danesh, Prof. Willy
Sansen, Jed Hurwitz, and Jim Brown.
—Jim Brown
SSCS-Scotland Chapter Chair
[email protected]

Seoul Chapter Hosts First Asian-Pacific Solid-State Circuit Workshop

S
SSCS-Seoul organized and hosted
the “1st Asian-Pacific Solid-State Cir-
cuits Workshop,” at Ewha Womans
University, Seoul, Korea. The main
theme of the workshop was high-
novel circuit techniques to find
solutions for applications in both
wireless and wireline.
As a result, the aim of this work-
shop was to refresh participants’
the convenience of the wireless
interface for short distance com-
munication, wireless links will
bring a great flexibility to system
design even for much shorter
speed interface ­circuits. familiarity with novel circuit tech- (several tens of micro-meter to
State-of-the-art solid-state cir- niques and to provide a forum for several millimeter) communi-
cuit industries in the Asia-Pacific the invited speakers to share their cation. Pulse-based inductive-
region have been proliferating very technical talents and their vision coupling interface, which uses
rapidly for several decades. The for future industry. More than 110 micro-inductor arrays is one of
vast usage of the Internet and the students, professors, and engineers the most promising high-speed
development of multimedia sys- from industries and research insti- wireless interfaces for such prox-
tems particularly require the op- tutes attended the workshop. imity communications.
eration speed of integrated circuits The five keynote speakers and their ■■ Design of Backplane Trans-
to increase exponentially. However, respective topics were the following: ceivers and High-Speed Blocks
this increase becomes a major chal- ■■ Pulse-Based Inductive-Coupling by Prof. Jri Lee (NTU, Taiwan)
lenge for the development of data Interface for High-Speed Proxim- This talk presented the design
and telecommunication systems. ity Communication by Prof. Hiroki and analysis of modern wireline
Therefore, prominent circuit de- Ishikuro (Keio University, Japan) transceivers as well as relative
signers have researched various As the RF-ID technology improves high-speed circuit techniques.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 103

 Three backplane transceivers, ■■ Burst-Mode Communication Cir-
conveying duo binary, PAM4, and The aim of this workshop cuits for Future FTTx by Dr.
NRZ data at 20 Gb/s, were de- was to refresh participants’ Yusuke Ohtomo (NTT, Japan)
scribed in detail to help evaluate familiarity with novel circuit As the explosive growth in Inter-
the performance of different data techniques and to provide a net traffic continues, the need for
format. Fabricated in 90-nm CMOS forum for the invited speak- high-speed, low-cost optical ac-
technology, all three transceivers ers to share their technical cess networks has been increas-
achieve error-free ­operation with talents and their vision for ing. Gigabit-­Ethernet passive op-
231-1 PRBS over 40-cm and 10-cm future industry. tical network (GE-PON) systems
FR4 channels. with a total bandwidth of 1 Gb/s
are being introduced for commer-
cial services, and there are cur-
rently more than 10 million fiber-
to-the-home (FTTH) subscribers
in Japan. In a PON system, burst
packet is used for upstream trans-
mission so that optical receiver
circuits have to reshape, retime
and regenerate the packets with
different power and phase within
a short period.
■■ Design Considerations in 40Gbps
Serial Transceiver in CMOS by
Dr. Jaeha Kim (Rambus, USA)
First, architectural decisions
that reflect the circuit and pro-
cess technology limitations
were addressed. Second, vari-
ous circuit techniques that ex-
tend the speed and bandwidth
Attendees at the first Asian-Pacific Solid-State Circuits workshop on 22 August 2008.
of the transmitter, receiver, PLL,
and CDR were described. Finally,
layout issues to fully realize the
circuit performance were cov-
ered. The soundness of these de-
sign decisions was demonstrated
based on the recent results from
a 40 Gbps serial transceiver im-
plemented in 0.13 um CMOS.
■■ Pulse-Based IC Interface for HS
Proximity – Trends of High-Speed
DRAM Interface by Prof. Hong-
June Park (POSTECH, Korea)
The trends of high-speed DRAM
interface were reviewed with
respect to signal integrity, the
signaling techniques, circuit de-
sign issues, and speed-limiting
factors. Conventional DRAM in-
terface schemes, such as DDR,
The organizing committee members and keynote speakers of the 1st Asian-Pacific Solid-State
DDR2, and FBDIMM, were dis-
Circuits Workshop were (from top left) Prof. Jeongjin Roh, Prof. Dong-Hyun Baek, Prof. Jinkoo
Kang, Prof. Kwang-Sub Yoon, Prof. Jinyong Chung, Prof. Taewook Kim, Prof. Shiho Kim, and cussed as well as methods used
Prof. Sung Min Park. From bottom left: Dr. Yusuke Ohtomo, Prof. Jri Lee, Dr. Jaeha Kim, Prof. to increase the date rate. 
Hong-June Park, and Prof. Hiroki Ishikuro.

104 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 soc iet y n e ws

Hajimiri, Hurst, Leenaerts, Kenneth O, and Ian Young

Elected to SSCS AdCom
Nominations Sought for 2010–2012

I
In November 2008 balloting, SSCS
members reelected Ali Hajimiri,
Paul J. Hurst, and Ian Young to sec-
ond terms on the Society’s AdCom
and chose Kenneth O for a first term,
interests are high-speed and RF in-
tegrated circuits.
Dr. Hajimiri is the author of
The Design of Low Noise Oscilla-
tors (Boston, MA: Springer, 1999)
Olympiad, Groningen, Netherlands.
He was a corecipient of the IEEE
Journal of Solid-State Circuits Best
Paper Award of 2004, the Interna-
tional Solid-State Circuits Confer-
as voting members from 1 January and has ­authored and coauthored ence Jack Kilby Outstanding Paper
2009 through 31 December 2011. Dr. more than 100 refereed journal Award, two times corecipient of
Domine Leenaerts, also elected, cur- and conference technical articles. CICC’s best paper awards, and a
rently serves as liaison from IEEE- He holds more­ than two dozen three-time winner of the IBM facul-
CAS to the AdCom. U.S. and European patents. He is a ty partnership award as well as Na-
member of the Technical Program tional Science Foundation CAREER
Meet the New AdCom Members Committee of the International award. He is a cofounder of Axiom
Solid-State Circuits Conference Microdevices Inc.
Ali Hajimiri re- (ISSCC). He has also served as an
ceived the B.S. de- associate editor of the IEEE Jour-
gree in electronics nal of Solid-State Circuits, an as- Paul J. Hurst recei­
engineering from sociate editor of IEEE Transactions ved the B.S., M.S.,
the Sharif Univer- on Circuits and Systems: Part II, a and Ph.D. degrees
sity of Technology member of the Technical Program in electrical engi-
and the M.S. and Ph.D. degrees in Committees of the International neering from the
electrical engineering from the ­Con­ference on Computer Aided University of Cali-
Stanford University in 1996 and ­D esign (ICCAD), guest editor of fornia at Berkeley in 1977, 1979,
1998, respectively. He was a design IEEE Transactions on Microwave and 1983, respectively. From
engineer with Philips Semiconduc- Theory and Techniques, and the 1983 to 1984, he was with the
tors, where he worked on a BiCMOS guest editorial board of the Trans- University of California, Berkeley, as
chip set for GSM and cellular units actions of Institute of Electronics, a lecturer, teaching integrated-circuit
from 1993 to 1994. In 1995, he Information and Communication design courses and working on an
was with Sun Microsystems, where Engineers of Japan (IEICE). MOS delta-sigma modulator. In 1984,
he worked on the UltraSPARC mi- Dr. Hajimiri was selected to the he joined the telecommunications
croprocessor’s cache RAM design top 100 innovators (TR100) list design group of Silicon Systems Inc.,
methodology. During the summer in 2004 and is a fellow of Okawa where he was involved in the design
of 1997, he was with Lucent Tech- ­Foundation. He is a Distinguished of mixed-signal CMOS integrated cir-
nologies (Bell Labs), Murray Hill, Lecturer of both the IEEE Solid-State cuits for voice-band modems.
New Jersey, where he investigated Circuits and Microwave Societ- Since 1986, he has been on the
low-phase-noise integrated oscil- ies. He is the recipient of Caltech’s faculty of the Department of Elec-
lators. In 1998, he joined the Fac- Graduate Students Council Teach- trical and Computer Engineering
ulty of the California Institute of ing and ­Mentoring award as well at the University of California at
Technology, Pasadena, where he is as Associated Students of Caltech Davis, where he is now a profes-
a professor of electrical engineer- Undergraduate Excellence in Teach- sor. His research interests are in
ing and the director of Microelec- ing Award. He was the Gold medal the area of analog and mixed-sig-
tronics Laboratory. His research winner of the National Physics Com- nal integrated-circuit design for
petition and the Bronze Medal win- signal processing and communica-
Digital Object Identifier 10.1109/MSSC.2008.930947 ner of the 21st International Physics tion applications.

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 105

 Research projects have included (2001–2006). He is an elected mem- Circuit Design group. In 1995, he was
work on data converters, filters, ber of the administrative commit- a visiting scholar with the Department
image processing, and adaptive- tee of the IEEE Solid-State Circuits of Electrical Engineering and Computer
­equalizer and timing-recovery Society for 2006–2008. He is a Fel- Science, University of California, Berke-
­circuits for data communications. low of the IEEE. ley. In 1997, he was an invited professor
He is a coauthor of a college text at Ecole Polytechnique Federale de Lau-
book on analog integrated-­circuit sanne, Switzerland. From 1999 to 2006
design. He is also active as a con- Domine M.W. Lee- he was a principal scientist with Philips
sultant to industry. He has served naerts received the Research Laboratories, Eindhoven,
on the program committees for the Ph.D. degree in elec- where he was involved in RF integrated
International Solid-State Circuits trical engineering transceiver design. In 2006, he moved
Conference and the Symposium on from Eindhoven Uni- to NXP Semiconductors, Research as
VLSI Circuits. He was guest editor versity of Technol- senior principal scientist.
for one issue of the IEEE Journal of ogy, The Netherlands, in 1992. From He has published over 150 ­papers
Solid-State Circuits. He served as 1992 to 1999, he was with Eindhoven in scientific and technical journals
­associate editor for the IEEE Journal University of Technology as an associ- and conference proceedings. He
of Solid-State Circuits for five years ate professor with the Micro-Electronic holds several U.S. patents and co-
authored several books, including
­Circuit Design for RF Transceivers
SSCS AdCom Nominations (Boston, MA: Kluwer, 2001).
The Society Nominations Committee begins in March to identify candidates for the Society Dr. Leenaerts served as IEEE Dis-
Administrative Committee. Although the election will occur in the fall of 2009, the slate of eight tinguished Lecturer in 2001–2003
candidates that the Society Bylaws requires for the five slots will be announced this summer. and served as associate editor of
Eight candidates for only five positions allows the electing members of SSCS a choice. Student IEEE Transactions on Circuits and
members are not eligible voters. The summer announcement allows members a month’s time to Systems—Part I (2002–2004) and,
petition for another name to be added to the ballot. Members interested to run or to nominate since 2007, has been an associate
others should send their recommendations to the chair of the Nominating committee, Richard editor for the IEEE Journal of Solid-
C. Jaeger, [email protected], by 28 February. State Circuits. He is currently IEEE
Circuits and Systems Society Mem-
Term of Office ber representative in the IEEE Solid-
•• The term of office is three years beginning 1 January 2010.
State Circuits Society Administrative
•• AdCom members may be reelected to a second consecutive term.
Committee. Dr. Leenaerts serves
•• Members who miss two consecutive AdCom meetings shall be dropped from AdCom in
currently on the Technical Program
the absence of extenuating circumstances. Committee of the European Solid-
State Circuits Conference, the IEEE
Scope
Radio Frequency Integrated Circuits
Elected AdCom members are expected to attend the two administrative meetings each year. Some
(RFIC), and IEEE International Solid-
committee work is carried on by e-mail throughout the year. The AdCom oversees the operations
State Circuits Conference (ISSCC).
of chapters, publications, and conferences including the IEEE Journal of Solid-State Circuits and
He is a Fellow of the IEEE.
IEEE Solid-States Circuits Magazine, the International Solid-State Circuits Conference, the Custom
Integrated Circuits Conference, the VLSI Circuits Symposium, and the Asia Solid-State Circuits Con-
ference. In addition, the Society cosponsors or technically cosponsors a number of other journals
Kenneth O re-
and conferences including the European Solid-State Circuits Conference.
ceived his S.B, S.M,
The AdCom has responsibility for overseeing these and for other potential future technical
and Ph.D degrees in
activities within the Society’s field of i­nterest.
electrical engineer-
Nominees by Petition ing and computer
Those interested to use the petition process must begin no later than 20 July, immediately after science from the
the Nominating Committee’s slate has been announced on the Society Web site (www.ieee.org/ Massachusetts Institute of Tech-
sscs). Contact the SSCS Executive Director Anne O’Neill, [email protected]. Once ­eligibility of nology, Cambridge, in 1984, 1984,
the petition candidate is verified, any Society voting member who wishes to sign such petition and 1989, respectively. From 1989
may do so electronically through online software under the administration of the IEEE Corporate to 1994, he worked at Analog De-
Office. The number of signatures required for a petition candidate is 2% of SSCS voting members vices Inc. developing submicron
at the time the petition process begins. This is expected to be approximately 140 signatures. CMOS processes for mixed sig-
Once a member is posted on the site, he or she will remain up to receive endorsement signa- nal applications and high speed
tures, until a predetermined date in late August or early September when the election begins. bipolar and BiCMOS processes for RF
and mixed signal applications. He
is currently a professor at the Uni-

106 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

versity of Florida, Gainesville. His ment of high speed serial IO circuit guest editor for the April 1997,
­research group (Silicon Microwave technology in the 32 nm logic pro- April 1996, and December 1994
Integrated Circuits and Systems Re- cess and researching chip-to-chip issues of the IEEE Journal of Solid
search Group) is developing circuits optical IO technology. State Circuits. He served on the
and components required to imple- Born in Melbourne, Australia, he SSCS Adcom from 2006 to 2008.
ment analog and digital systems received his bachelor’s and master’s Young is a Fellow of the IEEE. He
­operating between 1 GHz and 1 THz degrees from the University of Mel- has authored or coauthored over 40
using silicon IC technologies. bourne, Australia, in 1972 technical papers.
He was the general chair of the and 1975 and his Ph.D. from The success of the
2001 IEEE Bipolar/BiCMOS Circuits the University of Califor- SSCS depends on Our Next Meeting
and Technology Meeting (BCTM). He nia, Berkeley in 1978, all in the efforts and The success of the
was the guest editor of the special is- electrical engineering. dedication of all its SSCS depends on the
sue on 1996 BCTM in the IEEE Journal Young was a mem- members and on efforts and dedication
of Solid State Circuits. He has served ber of the Sympo- their willingness of all its members and
as an associate editor for IEEE Trans- sium on VLSI Circuits to commit time and on their willingness to
actions on Electron Devices from 1999 Technical Program expertise to benefit commit time and ex-
to 2001. Dr. O has also served as the Committee from the Society and the pertise to benefit the
publication chair of the 1999 Inter- 1991 to 1996, serv- global IC community. Society and the global
national Electron ­Device Meeting. ing as the program IC community. The next
Since 2003, he has been the Solid- committee chair AdCom meeting will be
State Circuits Society Liaison to IEEE in 1995/1996, and the Sympo- at noon on Sunday, 8 February
RFIC Symposium as well as a mem- sium chair in 1997–1998. He was 2009, prior to the ISSCC, at the San
ber of Steering Committee for RFIC a member of the ISSCC Techni- Francisco Marriott. Society sub-
Symposium. He has authored and cal Program Committee from committees will meet that morn-
coauthored nearly 170 journal and 1992 to 2005, serving as the ing. We are looking forward to see-
conference publications as well as Digital Subcommittee chair from ing all of you then.
holds nine patents. Dr. O has re- 1997 to 2003, the Technical Pro- —Richard C. Jaeger
ceived the 1996 NSF Early Career gram Committee vice-chair in SSCS Nominations Chair
Development Award, and 2003 UF 2004 and chair in 2005. He was
Ph.D./Mentor Award. He also held a
UF ­Research Foundation Professor-
ship from 2004 to 2007.

Ian Young is a se-

nior fellow and di-
rector of Advanced
Circuits and Tech-
nology Integration in
the Technology and
Manufacturing Group at Intel Cor-
poration. He does research and de-
velopment of mixed-signal circuits
for microprocessor, communica-
tions, and SOC products along with
process technology development.
Young joined Intel in 1983.
Starting with the development of
circuits for a 1 Mb DRAM, he then
led the design of three generations
of SRAM products and manufactur-
ing test vehicles and developed the
original phase locked loop based
clocking circuit in a microproces-
sor while working on the 50 MHz
Intel486 processor design. He is
currently directing the develop-

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 107

 IEEE n e ws

CEDA Currents

T
The following is reprinted from CEDA
Currents, July/August and September/
October 2008 issues. CEDA Currents is
a publication of the IEEE Council on
Electronic Design Automation. Contri-
to effectively administer the com-
mittee. Because this committee is
just forming, things are changing at
a very rapid pace. To stay updated,
please visit http://grouper.ieee.org/
con compilation and emulation into
businesses that have benefited elec-
tronic designers.
The 2007 award winner was Robert
Brayton (Cadence Distinguished Profes-
butions for future issues can be sent groups/ceda. sor of Electrical Engineering and Com-
to Jose Ayala ([email protected]) or Moreover, CEDA organized a panel puter Science at the University of Cali-
Anand Raghunathan (anand@nec- session on EDA standards for the Elec- fornia, Berkeley), for his demonstrable
labs.com). tronic Design Process (EDP) Workshop impact on the field of electronic design
(held April 2008 in Monterey, Califor- through contributions in EDA.
CEDA Standards Committee nia), promoting the initial approaches Please contact Nanette V. Collins
CEDA has formed a standards com- taken by CEDA in this area. ([email protected]) for further infor-
mittee to promote the development Please contact Rohit Kapur (rohit. mation, and visit http://www.edac.
of standards in the electronic de- [email protected]) or John Dar- org/about_kaufman_award.jsp.
sign automation (EDA) industry and ringer ([email protected]) for further
to act as the administrator for the information. Behavioral Synthesis
working groups under it, which will Making a Comeback?
develop and maintain standards. The seeds of behavioral synthe-
Such standards are beneficial to IC sis— also known as high-level
designers and automation tool de- synthesis—were sown in the early
velopers and users in this industry 1980s. Behavioral synthesis was
because they provide a mechanism introduced as a natural step in the
for defining common semantics. automatic generation of digital cir-
The committee is to be represent- cuits specified at abstraction levels
ed by EDA consortia, semiconductor The Phil Kaufman Award higher than the RTL in the hardware
companies, and associated standards The 2008 Phil Kaufman Award for description. The essential feature
groups, and governed by a chair and Distinguished Contributions to EDA of a behavioral description is that
a steering committee. The latter was presented in October at the 15th designers specify only an applica-
comprises the chair of the working Annual Phil Kaufman Award dinner tion’s high-level behavior, and the
groups under the standards com- and ceremony in Santa Clara, Cali- synthesis tool comes up with the
mittee, and may also include elected fornia. (Nominations for this award best schedule (which operations
members, such as senior managers were accepted until June 30.) This should occur in each clock cycle),
in EDA and representatives from award, jointly sponsored by CEDA a suitable allocation (which library
consortia, the Design Automation and the EDA Consortium, honors elements should be used), and a
Standards Committee (DASC), and individuals who have made a de- suggested binding and mapping
other interested parties. In addition, monstrable impact on the field of (which specific operation should be
the steering committee may select ex EDA in business, industry direction performed on each component in-
officio members to foster continuity and promotion, technology and en- stance). The behavioral-synthesis
and coordination with related groups gineering, or education and men- tool analyzes the application, along
and to exercise any other functions toring. It was established in 1994 with any associated constraints,
necessary (for example, secretary) in honor of deceased EDA industry and generates an optimized data
pioneer Phil Kaufman, who turned path comprising instantiations of
Digital Object Identifier 10.1109/MSSC.2008.930944 innovative technologies such as sili- elements selected from a library

108 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

and a finite-state machine to con-
trol the data path resources.
Early approaches to solve behav- CEDA to Introduce IEEE Embedded Systems Letters
ioral synthesis were extensions of a
New journal to be closely associated with research and industry forums
compiler’s tasks. However, there is a
CEDA has been exploring various ideas for nurturing publications through which it can reach
vital difference: a compiler targets a
out to the community of embedded-systems researchers and provide an excellent outlet for
fixed architecture, whereas a behav-
timely dissemination of technology advances. To guide this effort and solicit community input,
ioral synthesis tool also arrives at
we formed an ad hoc committee about a year ago, which developed a proposal for a new jour-
an application-specific architecture.
nal, discussed by IEEE bodies in two phases. After an intense year-long effort, the IEEE Technical
This difference results in an inter-
Activities Board approved phase II in July 2008.
esting relationship between synthe-
IEEE Embedded Systems Letters will discuss the latest technical advances in embedded sys-
sis and compilers: most compiler
tems and related areas in embedded software. Its emphasis will be on models, methods, and
optimizations are also applicable in
tools that ensure secure, correct, efficient, and robust design of embedded systems and their
synthesis, but the synthesis prob-
applications. CEDA will seek novel research papers in the following areas:
lem has its own exciting variants
•• embedded systems: architectures, automation algorithms, methods, and tools
because the tool itself decides the
•• micro-architectures, customizable processors, signal processing, multiprocessor SOC
target hardware.
and NOC architectures
As soon as RTL specification and
•• VLSI and low power-design for embedded processors and systems
synthesis began finding acceptance
•• compilation and managed runtime environments for embedded systems
in industry design flows, engineers
•• profiling, measurement, and analysis techniques for embedded applications
naturally began investigating the
•• design, specification, and synthesis of embedded systems: specification languages and
next big wave in automated circuit
models
generation, and behavioral syn-
•• hardware-software codesign, codesign methodologies, design exploration tools
thesis was a leading candidate in
•• power aware designs: modeling, analysis, estimation, and power management
the early 1990s. Product offerings
technique
emerged from Cadence Design Sys-
•• embedded-software design: models (programming models, formal models), methods, and
tems, Mentor Graphics, and Synop-
tools for real-time and resource constrained applications
sys. RTL design was itself new, but
•• programming languages and software engineering for embedded or real-time
the promised level of productivity
applications
leap was not really delivered.
•• testing, validation, and verification of embedded software
What went wrong? First, there
•• OS, middleware, and support systems for embedded-system design
was a mismatch of expectations.
•• model-driven software design: formal models, calculus, and code generation
The synthesis tool was designed to
•• component modeling and component-based development methodologies
automate every decision in the be-
•• embedded control systems: design, analysis, and application to cyber-physical systems
havioral design, but the designers
•• embedded systems security
weren’t quite ready—they wanted
•• applications of embedded systems and software: military, avionics, and automotive: case
tight manual control over the gen-
studies, applications of new methodologies and tools to applications with increased sys-
erated design. Second, the timing
tem heterogeneity and scale.
closure problem was leading to a
As with any emerging intellectual discipline, this journal’s areas of focus, special-issue high-
mismatch in pre- and postlayout
lights, and so on will evolve with important technical developments in the associated research
timings, and this would only get
communities. A particular strength of this journal will be its close association with research and
worse at higher abstraction levels.
industry forums.
Third, perhaps the tools could have
Manuscripts for this journal should contain new results, ideas, or innovations that significantly
benefited from improved engineer-
advance the state of the art in embedded systems. They must not be submitted, accepted,
ing; the user interface was clumsy
published, or copyrighted elsewhere. However, because the intent is to quickly announce new
and the ramp-up time was just too
results, more detailed versions of these manuscripts may also appear elsewhere later. Each
high. Fourth, verification method-
manuscript must be no more than four pages, or 2,200 words. The targeted publication time
ologies were thrown in disarray
will be four months from the end of the month in which a manuscript is received, provided the
when the tool rearranged computa-
author promptly responds to all communications and in accordance with instructions from the
tion across clock cycles.
reviewers and editorial staff. To accomplish this goal, the outcome of the review process will
By the early years of the new mil-
be to either accept or reject each manuscript. Only minor modifications that do not warrant
lennium, the technology that had
another review (other than by the associate editor) will be allowed.
once been heralded with much fan-
Jose L. Ayala
fare had become little more than a
CEDA Publications Committee
memory. Synopsys—the last of the
[email protected]
major EDA companies to pursue this
technology—finally ­discontinued its

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 109

behavioral compiler in 2005. High- in the late 1950s and early 1960s that it can be on the chip with the
level synthesis researchers declared and had to go through its patient processor and work at clock rates
victory on the topic and moved wait until the late 1980s before as close as possible to the proces-
ahead to even higher abstraction finding commercial adoption. Com- sor clock rate. But at the University
levels. Somehow, in these pilers were consid- of California, Berkeley, researchers
new ­modeling para- ered an esoteric are concentrating on their hybrid
digms, the first entry to CEDA conferences technology when Josephson-CMOS, second-level 4-Kb
the hardware domain provide excellent op- the idea of auto- memory. The storage is in compact,
would be the RTL; the portunities for those matic code gen- nonvolatile CMOS cells with very
behavioral level was interested in learn- eration was initially low-power-­dissipation supercon-
quietly forgotten. ing about the latest proposed. There is ducting interface circuits. In a col-
Fast-forward to technical trends in no reason why behav- laborative project with Yokohama
2008, and the buzz electronic design ioral synthesis should National University, these research-
surrounding this for- and automation. be exempted from this ers have brought the work to the
gotten ­technology circuitous route. These point of measuring the access time
may seem surpris- are still early days. The (500 ps) for a single bit in a 64-Kb
ing. Commercial products from both real wave is patiently awaited. CMOS array. This year’s goal is to
established EDA players and startups Please contact Preeti Ranjan Pan- determine the access time of a 64-
are now getting traction among de- da ([email protected]) for further Kb memory into which complete
signers. Will the second incarnation information. words can be written at arbitrary
do better at delivering the mythical locations and then subsequently
productivity boost? Perhaps. Clear- Moving Ahead with read. Such a hybrid will be able to
ly, more thought has gone into this Josephson Computation take advantage of advances in CMOS
round. The interface to the user is Recent industry trends clearly es- technology, such as higher density,
different, with many of the current tablish that design tradeoffs have faster operation, and lower voltag-
tools starting with C, C++, and Sys- brought CMOS close to the limits es, and could be readily scaled to
temC descriptions as inputs—indi- of its scalability. The U.S. govern- larger ­capacities.
cating a changed focus on the user. ment is supporting work to ad- Please contact Theodore Van
The approach to architecture genera- dress the fundamental question ­Duzer ([email protected])
tion is also more nuanced. Research of a substitute for silicon (CMOS) for further information.
groups haven’t really come back in in very high-end computing envi-
droves, but they have branched out ronments. Although microproces- Upcoming CEDA Events
into some relevant subareas such as sor firms have turned to parallel CEDA conferences provide excellent
timing and physical awareness. multiple cores, many demanding opportunities for those interested
How does 25 years of behavioral applications require higher-perfor- in learning about the latest techni-
synthesis research get evaluated mance components. cal trends in electronic design and
in terms of its industry impact? A government-sponsored study automation. If you are interested in
Clearly, the second round of excite- explored the potential for supercon- participating or have an idea about
ment in recent times indicates that ducting ultrahigh-clock-speed (50 new topics of interest for our confer-
you can never write off interesting GHz or higher), single-flux quantum ences, please contact William Joyner
ideas. The real motivation behind processing, along with the associ- ([email protected]), CEDA vice
behavioral synthesis is too power- ated memory, fabrication, and pack- president of conferences.
ful to be overlooked. However, it is aging. The report indicated that a
also too early to close the research large five-year project would be re- Reprinted from CEDA Currents,
chapter on the technology. Timing- quired. A precursor to the five-year July/Aug. 08 and Sept./Oct. 08. CEDA
closure issues made the first thrust project is being supported this year, Currents is a publication of the IEEE
a nonstarter, but the problem re- with several groups funded to do Council on Electronic Design Automa-
mains relevant; deep research is- preparatory research. tion. Please send contributions to Jose
sues remain to be addressed. Logic Wholly superconducting memo- Ayala ([email protected]) or Anand
synthesis research began in earnest ry remains an important target so Raghunathan ([email protected]).

110 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

IEEE Seeks Volunteers for Humanitarian Technology Challenge
Partnership with UN to Find Technical Solutions for Challenges Threatening Civilization

T
The Humanitarian Technology
Challenge (HTC) is a partnership
between IEEE and the United Na-
tions Foundation designed to bring
together technical profession-
composed of representatives from
ten humanitarian organizations:
■■ Reliable electricity: availability of

power for electronic devices.

■■ Data connectivity of rural district
visit different clinics and when
they relocate.
IEEE volunteers should be expe-
rienced in the application of tech-
nology to solve humanitarian issues
als and humanitarians to develop health offices: capability of ex- and be willing to commit approxi-
technological solutions for press- changing data among remote field mately two to four hours per week
ing challenges facing humanity. offices and central health facilities. to the project. A conference call/we-
A small number of IEEE members ■■ Local management and tracking bcast for early-stage volunteers was
are needed to help shape the early of supply distribution: ensure that scheduled to take place in late No-
stages of the program, working with supplies are getting to the people vember 2008, to be followed by an
humanitarians to further detail chal- that need them to maximize the in-person conference scheduled for
lenge definitions and outline a solution impact of assistance. the first quarter of 2009, where ad-
process. This is a unique opportunity ■■ Incident tracking: determine loca- ditional volunteers will be needed.
for IEEE volunteers experienced in sys- tions and extent of medical prob- For more information, visit the
tems engineering to work directly with lems in order to focus resources. HTC Web site (www.ieee.org/go/htc).
prominent humanitarian volunteers. ■■ Patient ID and tie to health re- Interested volunteers should con-
The following initial challenges cords: maintain consistent patient tact Harold Tepper, IEEE HTC project
were identified by focus groups records, including when patients manager, at [email protected].

IEEE Competition Seeks to Benefit Humanity

I
In September 2008, IEEE announced
the first IEEE Presidents’ Change the
World Competition for college and uni-
versity students who demonstrate ex-
cellence in the design and implemen-
vited to ­accept their awards in per-
son in June 2009 at the annual IEEE
Honors Ceremony in Los Angeles,
California, USA. In addition, up to
15 semifinalists will compete for a
global celebration of IEEE’s 125th An-
niversary. To enter and for complete
rules and guidelines, please visit
the IEEE 125th Anniversary Web site
at ieee125.org/ChangeTheWorld.
tation of technology that can solve a Peoples’ Choice US$500 award, which
challenge for the benefit of humanity. will be selected by popular vote from Eligibility
The window for submissions extends the contest Web site at ieee125.org/ The contest is open to individual
through 28 February 2009. ChangeTheWorld. IEEE student members or teams of
The goal of the competition is to “The IEEE Presidents’ Change the college and university-students who
challenge individual students or teams World Competition is an exciting way have selected an IEEE student mem-
of students to identify a ­real-world to engage students and help unlock ber as the team lead.
problem and apply engineering, sci- the passion so many of them have for
ence, computing, and leadership skills helping humanity and making a dif- Submissions
to solve it. The contest offers students ference for mankind,” said John Vig, Entries must be submitted using the
a unique opportunity to have their IEEE president chair of the 125th An- form housed on the competition Web
ingenuity and enthusiasm for engi- niversary committee. “This contest site at ieee125.org/ChangeTheWorld.
neering and technology recognized provides the opportunity for students Requirements include the following:
around the globe. worldwide to change at least a small ■■ project title

Winners will receive awards part of the world, to communicate ■■ problem description

ranging from the grand prize of their ideas, express their creativity, ■■ solution

US$10,000 and the distinction of be- entrepreneurship and leadership, and ■■ impact on humanity or a community

ing named “IEEE Student Humanitar- use their engineering and technology ■■ primary leader with name and

ian Supreme,” to prizes of US$5,000, skills to make a positive impact.” contact information (full name,
US$2,500, and US$1,000. Winners of The IEEE Presidents’ Change the college/university, address, phone
the top three prizes also will be in- World Competition is part of the number and e-mail address); other

IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 20 0 9 111

 major student contributors and Judging and rank up to five of the best projects
their contributions Submissions will be evaluated in in their region by 30 March 2009.
■■ other contributors. IEEE’s ten geographic regions by each A global competition judging com-
Incomplete entries will not be IEEE Regional Student Activities Com­ mittee (appointed by the 2009 IEEE
accepted. mittee. Each committee will select president) will then review the entries
selected by the Regional Student Activi-
ties Committee and select and rank 15
Call for Fellow Nominations finalist projects which best meet the
Nominations are being accepted until 1 March 2009 for the 2010 class of IEEE Fellows. competition criteria, by 20 April 2009.
IEEE Fellows are an elite group from around the globe. The IEEE looks to the Fellows for guidance These 15 projects will be posted on the
and leadership as the world of electrical and electronic technology continues to evolve. The ac- competition Web site, and there will be
complishments that are being honored should have contributed importantly to the advancement a campaign to encourage participative
or application of engineering, science and technology, bringing significant value to society. voting for a People’s Choice prize.
Revisions to the IEEE Fellow nomination process have taken place over the past few years, The 2008, 2009, and 2010 IEEE
mainly in an effort to generate more Fellow nominations from industry. Fellow nominees are presidents will evaluate the 15 proj-
now classified as research engineer/scientist, application engineer/practitioner, technical leader, ects and select the prize winners by
or educator. 10 May 2009. In the event that simi-
Candidates for Fellow must hold Senior Member grade at the time the nomination is submitted lar entries are submitted by multiple
and shall have been an IEEE Member in good standing (in any grade) for a period of five years participants, IEEE reserves the right
or more preceding 1 January of the year of election. to select the prize winners based on
Any person, including a nonmember, is eligible to be an IEEE Fellow nominator with a few the listed criteria.
exceptions. The steps, responsibilities and forms are online at www.ieee.org/web/member- Entries will be judged based on the
ship/fellows/fellow_steps.html/ results achieved and their impact on
Nominations, references and endorsements may be submitted electronically. humanity, or, on a community.
Sustainability, reusability, trans-
portability of the results to other parts
of the world, entrepreneurship, origi-
nality, creativity and leadership are im-
Three Advanced Engineering Courses
portant, secondary evaluation factors.
The IEEE Presidents’ Change the
World Competition is part of the
­global celebration of IEEE’s 125th An-
MEAD Microelectronics Inc. niversary. To enter and for complete
rules and guidelines, please visit the
1. Low-Power, Low-Voltage Analog IC Design IEEE 125th Anniversary Web site at
2. Power Management www.ieee125.org/ChangeTheWorld.
3. Practical Approach to Delta-Sigma Design
Instructors
About IEEE’s 125th Anniversary
In 2009, IEEE is commemorating 125
R. Blauschild, P. Brokaw, I. Galton, V. Ivanov, D. Maksimovic, K. Pedrotti, M. Pelgrom,
years of ingenuity and innovation
R. Redl, W. Sansen, R. Schreier, J. Steensgaard, T. Szepesi, G. Temes, E. Vittoz
in engineering and technology with
Course Location events and activities supporting the
Courses will be held March 23-27, 2009 at the anniversary theme “Celebrating 125
University of California Santa Cruz Years of Engineering the Future.”
Jack Baskin Engineering Building
The year-long IEEE celebration in-
Santa Cruz, CA 95064
cludes local and global member
The courses are jointly organized with the John Baskin School of Engineering of
and customer events; the first IEEE
the University of California, Santa Cruz.
Presidents’ Change the World Com-
For additional information contact: petition for students; a global media
MEAD Microelectronics, Inc. Email: [email protected] (technical) or roundtable and webcast featuring
7100 NW Grandview Drive [email protected] (administrative)
emerging, world-changing technolo-
Corvallis, Oregon, 97330
Telephone: (541) 758-0828 gies; the official unveiling of IEEE
Fax: (541) 752-1405 Engineering the Future Day on 13
May 2009; and much more. For more
For programs, fee and registration information, please visit us: www.mead.ch information on the IEEE 125th Anni-
Deadline for early registration is February 14, 2009 versary, visit www.ieee125.org.

112 WINTER 20 0 9 IEEE SOLID-STATE CIRCUITS MAGAZINE

 footer

Where in the World Are the SSCS DLs?

5 1
5 4
6 2 3 1
7
9 8

John Long Ian Galton

Leuven Boston
27 August 2008 18 August 2008
“White Phones, Black Art: The “Mismatch-Shaping DACs for
Evolution of RFIC Design in Silicon Delta-Sigma Data Converters”
Microelectronic Technologies”

© imagesource 2
2
8
7 1

Kerry Bernstein
Behzad Razavi Fort Collins, Colorado
Los Angeles, Taipei 9 September 2008
26 June 2008, 11 September 2008 Clark Nguyen Tom Lee “New Dimensions in
“A New Transceiver Architecture Japan New York Microarchitecture—
for the 60-GHz Ban” 24 April 2008 8 November 2008 3D Integration Technology”
“Systematic Transistor and Induc- “Integrated Micromechanical “A Wildly Nonlinear History of “The Rise of an Electronic
tor Modeling for Millimeter-Wave Circuits for RF Front-Ends,” in the Wireless,” in this issue on page 102. Species,” in this issue on page 92.
Design,” in this issue on page 93. SSCS News, Summer 2008

3 2
4 6
9

Mircea Stan Simon Wong

Vojin Oklobdjiza Betty Prince Austin Fort Collins, Colorado
Nis, Belgrade Shanghai December 2008 14 August 2008
14, 16 May 2008, 6 June 2008 17 October 2008 “High Performance Low Power “Scalability of RF CMOS”
“Future of Microprocessors: “Trends in Embedded Non-Volatile VLSI Design”
Retrospective and Challenges” Memories”
“Directions in Computer Engineering” Bangalore and Delhi
Istanbul 10,12 November 2008
29 May 2008 “Trends in Solar Energy and Solar 9
3
“Low-Power Design and Energy- Photovoltaics”
Delay Relationship in Digital Circuits”

9
9
Kofi Makinwa
Werner Weber Bangalore and Delhi
Dallas 10, 12 November 2008
22 October 2008 “Designing Smart Sensors
“Industrialization of MEMS” in Standard CMOS”
Tadahiro Kuroda
David Su Bangalore and Delhi
Bangalore and Delhi 10,12 November 2008
10, 12 November 2008 “Low Power CMOS Design –
“Designing CMOS Wireless Challenges and Opportunities in
System-on-a-Chip” System LSI”
“Introduction to CMOS RF Power
Amplifier and Designing CMOS Information about the Solid-State Circuits Society DL Program and our roster of speakers
Wireless System-on-a-Chip are available at sscs.org/Chapters/dl.htm.
Materials edited by Katherine Olstein, SSCS News Editor
Digital Object Identifier 10.1109/SSC.2009.931851