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Practice Questions - Unit6

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11 views17 pages

Practice Questions - Unit6

Uploaded by

divyanshu9009.chib
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Practice Questions on Unit 6

Q1. Design an SR flip-flop to JK flip flop with circuit diagram.

Ans.
Q2. . Design a JK to SR flip flop with circuit diagram.

Ans.
Q3. Design a SR to D flip flop with circuit diagram.

Ans.

Q4. Describes the conversion of SR to JK flip flop with circuit diagram.


Registers:

Q1.
Q2. Johnson counter

Solution:

Q3.
Q4.
Q5.
1. Design 2 bit Asynchronous UP counter?

When two FFs are connected in series and output of one FF is act as clock for 2nd FF. So the state
of 2nd FF will change only when output and 1st FF is logic 1 and falling edge occur. The output
frequency of Q1 is f/4(if f is clock frequency).
It can generate 4 different unique states. This is known as divide by 4 circuits or mod 4 ripple
counter.
Here output is taken as Q1(MSB) Q0(LSB).

By this, we can conclude that –

If there are n FFs then the output frequency will be divide by 2n. Also generate 2n unique states.

So the frequency division basically forms counting state.


Here we are seeing that the output of the 1st FF act as clock for 2nd FF. Suppose the FF takes 30ns
for generating output(i.e. propagation delay because of gates). Therefore, the output of second FF
will be obtained after 60 ns. So the propagation delay is ripples through the FFs and becomes more
when the number of FFs increases.

Design 2 bit asynchronous down counter


Q3: Design synchronous Mod 12 counter using JK flip flop.
Q2: Design Mod-4 up-down synchronous counter and explain working (two solutions below using JK,
D FF
MCQ questions on 6 Unit

1. The SR latch is formed using which of the following logic gates?


A) AND gates
B) OR gates
C) NOR gates
D) XOR gates
Answer: C

2. In an active-high SR latch, what condition causes the latch to enter an invalid state?
A) S=1, R=1
B) S=0, R=0
C) S=0, R=1
D) S=1, R=0
Answer: A

3. Which of the following is true about SR latch?


A) It has a clock input.
B) It requires a set and reset input.
C) It is edge-triggered.
D) None of the above.
Answer: B

2. D Latch

4. The D latch eliminates the invalid state of which flip-flop?


A) T flip-flop
B) JK flip-flop
C) SR flip-flop
D) None of the above
Answer: C

5. When is the output of a D latch updated?


A) On every clock edge
B) On a low enable signal
C) When the enable signal is high
D) None of the above
Answer: C

6. The D latch has how many inputs?


A) 1
B) 2
C) 3
D) 4
Answer: B

3. D Flip-Flop
7. Which of the following is true about a D flip-flop?
A) It is level-sensitive
B) It is edge-triggered
C) It requires both enable and clock signals
D) None of the above
Answer: B

8. A D flip-flop transfers input to output on which clock edge?


A) Rising edge
B) Falling edge
C) Both edges
D) Level-sensitive
Answer: A

9. A D flip-flop stores how many bits of data?


A) 1
B) 2
C) 4
D) 8
Answer: A

4. JK Flip-Flop

10. The JK flip-flop eliminates the invalid state of which flip-flop?


A) D flip-flop
B) SR flip-flop
C) T flip-flop
D) None of the above
Answer: B

11. What happens when both J and K inputs are 1 in a JK flip-flop?


A) The output is set to 1.
B) The output toggles.
C) The output is cleared.
D) Invalid state occurs.
Answer: B

12. The characteristic equation of a JK flip-flop is:


A) Q(next) = JQ' + K'Q
B) Q(next) = JQ + K'Q'
C) Q(next) = J + KQ
D) Q(next) = JQ + KQ'
Answer: A

5. T Flip-Flop

13. The T flip-flop toggles its output when:


A) T=0
B) T=1
C) Clock is low
D) Clock is high
Answer: B

14. Which flip-flop can be converted into a T flip-flop?


A) D flip-flop
B) SR flip-flop
C) JK flip-flop
D) All of the above
Answer: D

15. The T flip-flop is also known as:


A) Toggle flip-flop
B) Transfer flip-flop
C) Transparent flip-flop
D) None of the above
Answer: A

6. Master-Slave JK Flip-Flop

16. The master-slave configuration is used to:


A) Remove race-around condition
B) Reduce propagation delay
C) Eliminate invalid states
D) None of the above
Answer: A

17. The output of the master is transferred to the slave when the clock is:
A) Rising edge
B) Falling edge
C) High level
D) Low level
Answer: B

18. How many flip-flops are used in a master-slave JK flip-flop?


A) 1
B) 2
C) 3
D) 4
Answer: B

7. Flip-Flop Conversion

19. A D flip-flop can be derived from which flip-flop?


A) JK flip-flop
B) SR flip-flop
C) T flip-flop
D) All of the above
Answer: A

20. Which gate is required to convert a JK flip-flop into a T flip-flop?


A) XOR gate
B) AND gate
C) OR gate
D) NOT gate
Answer: A

21. The input logic for converting SR flip-flop to JK flip-flop requires:


A) NAND gates
B) XOR gates
C) AND gates
D) None of the above
Answer: C

8. Shift Registers

22. A shift register is primarily used for:


A) Storage
B) Data transfer
C) Signal amplification
D) Oscillation
Answer: B

23. Which shift register shifts data in both directions?


A) SISO
B) SIPO
C) PISO
D) Bidirectional shift register
Answer: D

24. The Johnson counter is derived from which type of shift register?
A) Serial-in Serial-out
B) Serial-in Parallel-out
C) Ring counter
D) Parallel-in Parallel-out
Answer: C

9. Counters

25. An asynchronous counter is also known as:


A) Ripple counter
B) Synchronous counter
C) Decade counter
D) None of the above
Answer: A
26. The modulus of a 4-bit counter is:
A) 4
B) 8
C) 16
D) 32
Answer: C

27. A synchronous counter eliminates which problem of asynchronous counters?


A) Propagation delay
B) Glitch
C) High power consumption
D) None of the above
Answer: A

28. A ring counter with 4 flip-flops has how many states?


A) 4
B) 8
C) 16
D) 1
Answer: A

29. In a Johnson counter, the total states are:


A) Equal to the number of flip-flops
B) Twice the number of flip-flops
C) Half the number of flip-flops
D) None of the above
Answer: B

30. Which counter counts up and down?


A) Asynchronous counter
B) Synchronous counter
C) Bidirectional counter
D) None of the above
Answer: C

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