JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

M.TECH. (DIGITAL SYSTEMS & COMPUTER ELECTRONICS)

COURSE STRUCTURE AND SYLLABUS

I Year – II Semester
Category Course Title Int. Ext. L P C
marks marks
Core Course IV Advanced Computer Architecture 25 75 4 -- 4
Core Course V Digital Signal Processors and Architectures 25 75 4 -- 4
Core Course VI Real Time Operating Systems 25 75 4 -- 4
Core Elective III CPLD and FPGA Architectures and Applications 25 75 4 -- 4
Network Security and Cryptography
System on Chip Architecture
Core Elective IV Low Power VLSI Design 25 75 4 -- 4
Design for Testability
Device Modeling
Open Elective II Software Defined Radio 25 75 4 -- 4
Adhoc Wireless Networks
Scripting Languages
Laboratory II Embedded Systems Lab 25 75 -- 4 2
Seminar II Seminar 50 -- -- 4 2
Total Credits 24 8 28

1
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

ADVANCED COMPUTER ARCHITECTURE

UNIT- I:
Fundamentals of Computer Design
Fundamentals of Computer design, Changing faces of computing and task of computer designer,
Technology trends, Cost price and their trends, measuring and reporting performance, quantitative
principles of computer design, Amdahl’s law.
Instruction set principles and examples- Introduction, classifying instruction set- memory addressing-
type and size of operands, operations in the instruction set.

UNIT – II:
Pipelines
Introduction ,basic RISC instruction set ,Simple implementation of RISC instruction set, Classic five
stage pipe line for RISC processor, Basic performance issues in pipelining , Pipeline hazards,
Reducing pipeline branch penalties.
Memory Hierarchy Design
Introduction, review of ABC of cache, Cache performance , Reducing cache miss penalty, Virtual
memory.

UNIT - III:
Instruction Level Parallelism the Hardware Approach
Instruction-Level parallelism, Dynamic scheduling, Dynamic scheduling using Tomasulo’s approach,
Branch prediction, high performance instruction delivery- hardware based speculation.
ILP Software Approach
Basic compiler level techniques, static branch prediction, VLIW approach, Exploiting ILP, Parallelism
at compile time, Cross cutting issues -Hardware verses Software.

UNIT – IV:
Multi Processors and Thread Level Parallelism
Multi Processors and Thread level Parallelism- Introduction, Characteristics of application domain,
Systematic shared memory architecture, Distributed shared – memory architecture, Synchronization.

UNIT – V:
Inter Connection and Networks
Introduction, Interconnection network media, Practical issues in interconnecting networks, Examples
of inter connection, Cluster, Designing of clusters.
Intel Architecture
Intel IA- 64 ILP in embedded and mobile markets Fallacies and pit falls

TEXT BOOKS:
1. John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach, 3rd
Edition, An Imprint of Elsevier.

REFERENCE BOOKS:
1. John P. Shen and Miikko H. Lipasti, Modern Processor Design : Fundamentals of Super
Scalar Processors
2. Computer Architecture and Parallel Processing ,Kai Hwang, Faye A.Brigs., MC Graw Hill.,
3. Advanced Computer Architecture - A Design Space Approach, Dezso Sima, Terence
Fountain, Peter Kacsuk ,Pearson ed.

2
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES

UNIT-I:
Introduction to Digital Signal Processing:
Introduction, A digital Signal – Processing system, the sampling process, Discrete time sequences,
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), linear time-invariant systems,
Digital filters, Decimation and interpolation.
Architectures for Programmable DSP devices:
Basic Architectural features, DSP computational building blocks, Bus Architecture and Memory, Data
addressing capabilities, Address generation UNIT, programmability and program execution, speed
issues, features for external interfacing.

UNIT-II:
Programmable Digital Signal Processors:
Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX
processors, memory space of TMS320C54XX processors, program control, TMS320C54XX
instructions and programming, On-Chip peripherals, Interrupts of TMS320C54XX processors, Pipeline
operation of TMS320C54XX processors.

UNIT-III:
Architecture of ARM Processors:
Introduction to the architecture, Programmer’s model- operation modes and states, registers, special
registers, floating point registers, Behaviour of the application program status register(APSR)-Integer
status flags, Q status flag, GE bits, Memory system-Memory system features, memory map, stack
memory, memory protection unit (MPU), Exceptions and Interrupts-what are exceptions?, nested
vectored interrupt controller(NVIC), vector table, Fault handling, System control block (SCB), Debug,
Reset and reset sequence.
Technical Details of ARM Processors:
General information about Cortex-M3 and cortex M4 processors-Processor type, processor
architecture, instruction set, block diagram, memory system, interrupt and exception support,
Features of the cortex-M3 and Cortex-M4 Processors-Performance, code density, low power, memory
system, memory protection unit, interrupt handling, OS support and system level features, Cortex-M4
specific features, Ease of use, Debug support, Scalability, Compatibility.

UNIT-IV:
Instruction SET:
Background to the instruction set in ARM Cortex-M Processors, Comparison of the instruction set in
ARM Cortex-M Processors, understanding the assembly language syntax, Use of a suffix in
instructions, Unified assembly Language (UAL), Instruction set, Cortex-M4-specific instructions, Barrel
shifter, Accessing special instructions and special registers in Programming.
UNIT-V:
Floating Point Operations:
About Floating Point Data,Cortex-M4 Floating Point Unit (FPU)- overview, FP registers overview,
CPACR register, Floating point register bank, FPSCR, FPU->FPCCR, FPU-> FPCAR, FPU-
>FPDSCR, FPU->MVFR0, FPU->MVFR1.

TEXTBOOKS:
1. Digital Signal Processing- Avtar Singh and S. Srinivasan, CENGAGE Learning, 2004.
2. The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors by Joseph Yiu, Elsevier
Publications, Third edition.
REFERENCES:
1. ARM System Developer’s Guide Designing and Optimizing System Software by Andrew N.
SLOSS, Dominic SYMES, Chris WRIGHT, Elsevier Publications, 2004.

3
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

REAL TIME OPERATING SYSTEMS

UNIT – I:
Introduction
Introduction to UNIX/LINUX, Overview of Commands, File I/O,( open, create, close, lseek, read,
write), Process Control ( fork, vfork, exit, wait, waitpid, exec).

UNIT - II:
Real Time Operating Systems
Brief History of OS, Defining RTOS, The Scheduler, Objects, Services, Characteristics of RTOS,
Defining a Task, asks States and Scheduling, Task Operations, Structure, Synchronization,
Communication and Concurrency.
Defining Semaphores, Operations and Use, Defining Message Queue, States, Content, Storage,
Operations and Use

UNIT - III:
Objects, Services and I/O
Pipes, Event Registers, Signals, Other Building Blocks, Component Configuration, Basic I/O
Concepts, I/O Subsystem

UNIT - IV:
Exceptions, Interrupts and Timers
Exceptions, Interrupts, Applications, Processing of Exceptions and Spurious Interrupts, Real Time
Clocks, Programmable Timers, Timer Interrupt Service Routines (ISR), Soft Timers, Operations.

UNIT - V:
Case Studies of RTOS
RT Linux, MicroC/OS-II, Vx Works, Embedded Linux, and Tiny OS.

TEXT BOOK:
1. Real Time Concepts for Embedded Systems – Qing Li, Elsevier, 2011

REFERENCE BOOKS:
1. Embedded Systems- Architecture, Programming and Design by Rajkamal, 2007, TMH.
2. Advanced UNIX Programming, Richard Stevens
3. Embedded Linux: Hardware, Software and Interfacing – Dr. Craig Hollabaugh

4
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

CPLD AND FPGA ARCHITECURES AND APPLICATIONS

(Core Elective –III)

UNIT-I:
Introduction to Programmable Logic Devices:
Introduction, Simple Programmable Logic Devices – Read Only Memories, Programmable Logic
Arrays, Programmable Array Logic, Programmable Logic Devices/Generic Array Logic; Complex
Programmable Logic Devices – Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD
Implementation of a Parallel Adder with Accumulation.

UNIT-II:
Field Programmable Gate Arrays:
Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block Architectures,
Programmable Interconnects, Programmable I/O blocks in FPGAs, Dedicated Specialized
Components of FPGAs, Applications of FPGAs.

UNIT -III:
SRAM Programmable FPGAs:
Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000 and
XC4000 Architectures.

UNIT -IV:
Anti-Fuse Programmed FPGAs:
Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and ACT3
Architectures.

UNIT -V:
Design Applications:
General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a Robot
Manipulator, A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and
Accumulators with the ACT Architecture.

TEXT BOOKS:
1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International
Edition.
2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage Learning.
REFERENCE BOOKS:
1. Field Programmable Gate Arrays - John V. Oldfield, Richard C. Dorf, Wiley India.
2. Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/Samiha Mourad,
Pearson Low Price Edition.
3. Digital Systems Design with FPGAs and CPLDs - Ian Grout, Elsevier, Newnes.
4. FPGA based System Design - Wayne Wolf, Prentice Hall Modern Semiconductor Design
Series.

5
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

NETWORK SECURITY AND CRYPTOGRAPHY

(Core Elective –III)

UNIT- I:
Introduction : Attacks, Services and Mechanisms, Security attacks, Security services, A Model for
Internetwork security, Classical Techniques: Conventional Encryption model, Steganography,
Classical Encryption Techniques.
Modern Techniques : Simplified DES, Block Cipher Principles, Data Encryption standard, Strength of
DES, Block Cipher Design Principles.

UNIT- II:
Encryption : Triple DES, International Data Encryption algorithm, Blowfish, RC5, Characteristics of
Advanced Symmetric block cifers.
Conventional Encryption
Placement of Encryption function, Traffic confidentiality, Key distribution, Random Number
Generation.

UNIT - III:
Public Key Cryptography
Principles, RSA Algorithm, Key Management, Diffie-Hellman Key exchange, Elliptic Curve
Cryptograpy.
Number Theory
Prime and Relatively prime numbers, Modular arithmetic, Fermat’s and Euler’s theorems, Testing for
primality, Euclid’s Algorithm, the Chinese remainder theorem, Discrete logarithms.

UNIT- IV:
Message Authentication and Hash Functions
Authentication requirements and functions, Message Authentication, Hash functions, Security of
Hash functions and MACs.
Hash and Mac Algorithms
MD File, Message digest Algorithm, Secure Hash Algorithm.
Digital signatures and Authentication protocols: Digital signatures, Authentication Protocols, Digital
signature standards.
Authentication Applications: Kerberos, Electronic Mail Security: Pretty Good Privacy, S/MIME.

UNIT – V:
IP Security
Overview, Architecture, Authentication, Encapsulating Security Payload, Key Management. Web
Security: Web Security requirements, Secure sockets layer and Transport layer security, Secure
Electronic Transaction.
Intruders, Viruses and Worms: Intruders, Viruses and Related threats.
Fire Walls: Fire wall Design Principles, Trusted systems.

TEXT BOOKS:
1. Cryptography and Network Security: Principles and Practice - William Stallings, Pearson
Education.
2. Network Security Essentials (Applications and Standards) by William Stallings Pearson
Education.

REFERENCE BOOKS:
1. Fundamentals of Network Security by Eric Maiwald (Dreamtech press)
2. Network Security - Private Communication in a Public World by Charlie Kaufman, Radia
Perlman and Mike Speciner, Pearson/PHI.
3. Principles of Information Security, Whitman, Thomson.
4. Network Security: The complete reference, Robert Bragg, Mark Rhodes, TMH
5. Introduction to Cryptography, Buchmann, Springer.

6
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

SYSTEM ON CHIP ARCHITECTURE

(Core Elective –III)

UNIT –I:
Introduction to the System Approach:
System Architecture, Components of the system, Hardware & Software, Processor Architectures,
Memory and Addressing. System level interconnection, An approach for SOC Design, System
Architecture and Complexity.

UNIT – II:
Processors
Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts
in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline
Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions,
VLIW Processors, Superscalar Processors.

UNIT – III:
Memory Design for SOC:
Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache
Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of
Cache, Split – I , and D – Caches , Multilevel Caches, Virtual to real translation , SOC Memory
System , Models of Simple Processor – memory interaction.

UNIT - IV:
Interconnect Customization and Configuration
Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models,
Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An
overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto
Reconfigurable devices, Instance- Specific design, Customizable Soft Processor, Reconfiguration -
overhead analysis and trade-off analysis on reconfigurable Parallelism.

UNIT – V:
Application Studies / Case Studies
SOC Design approach, AES algorithms, Design and evaluation, Image compression – JEPG
compression.

TEXT BOOKS:
1. Computer System Design System-on-Chip by Michael J. Flynn and Wayne Luk, Wiely India Pvt.
Ltd.
2. ARM System on Chip Architecture – Steve Furber –2nd Eed., 2000, Addison Wesley Professional.
REFERENCE BOOKS:
st
1. Design of System on a Chip: Devices and Components – Ricardo Reis, 1 Ed., 2004, Springer
2. Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded
Technology) – Jason Andrews – Newnes, BK and CDROM
3. System on Chip Verification – Methodologies and Techniques –Prakash Rashinkar, Peter
Paterson and Leena Singh L, 2001, Kluwer Academic Publishers.

7
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

LOW POWER VLSI DESIGN

(Core Elective –IV)

UNIT –I:
Fundamentals:
Need for Low Power Circuit Design, Sources of Power Dissipation – Switching Power Dissipation,
Short Circuit Power Dissipation, Leakage Power Dissipation, Glitching Power Dissipation, Short
Channel Effects –Drain Induced Barrier Lowering and Punch Through, Surface Scattering, Velocity
Saturation, Impact Ionization, Hot Electron Effect.

UNIT –II:
Low-Power Design Approaches:
Low-Power Design through Voltage Scaling – VTCMOS circuits, MTCMOS circuits, Architectural
Level Approach –Pipelining and Parallel Processing Approaches.
Switched Capacitance Minimization Approaches:
System Level Measures, Circuit Level Measures, Mask level Measures.

UNIT –III:
Low-Voltage Low-Power Adders:
Introduction, Standard Adder Cells, CMOS Adder’s Architectures – Ripple Carry Adders, Carry Look-
Ahead Adders, Carry Select Adders, Carry Save Adders, Low-Voltage Low-Power Design Techniques
–Trends of Technology and Power Supply Voltage, Low-Voltage Low-Power Logic Styles.

UNIT –IV:
Low-Voltage Low-Power Multipliers:
Introduction, Overview of Multiplication, Types of Multiplier Architectures, Braun Multiplier, Baugh-
Wooley Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier.

UNIT –V:
Low-Voltage Low-Power Memories:
Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of
SRAM, Memory Cell, Precharge and Equalization Circuit, Low-Power SRAM Technologies, Basics of
DRAM, Self-Refresh Circuit, Future Trend and Development of DRAM.

TEXT BOOKS:
1. CMOS Digital Integrated Circuits – Analysis and Design – Sung-Mo Kang, Yusuf Leblebici, TMH,
2011.
2. Low-Voltage, Low-Power VLSI Subsystems – Kiat-Seng Yeo, Kaushik Roy, TMH Professional
Engineering.

REFERENCE BOOKS:
1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC
Press, 2011
2. Low Power CMOS Design – Anantha Chandrakasan, IEEE Press/Wiley International, 1998.
3. Low Power CMOS VLSI Circuit Design – Kaushik Roy, Sharat C. Prasad, John Wiley & Sons,
2000.
4. Practical Low Power Digital VLSI Design – Gary K. Yeap, Kluwer Academic Press, 2002.
5. Low Power CMOS VLSI Circuit Design – A. Bellamour, M. I. Elamasri, Kluwer Academic Press,
1995.
6. Leakage in Nanometer CMOS Technologies – Siva G. Narendran, AnathaChandrakasan,
Springer, 2005.

8
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

DESIGN FOR TESTABILITY

(Core Elective –IV)

UNIT -I:
Introduction to Testing:
Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends
affecting Testing, Types of Testing, Fault Modeling: Defects, Errors and Faults, Functional Versus
Structural Testing, Levels of Fault Models, Single Stuck-at Fault.

UNIT -II:
Logic and Fault Simulation:
Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms
for True-value Simulation, Algorithms for Fault Simulation, ATPG.

UNIT -III:
Testability Measures:
SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan
Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan Design, Variations of Scan.

UNIT -IV:
Built-In Self-Test:
The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation,
Response Compaction, Built-In Logic Block Observers, Test-Per-Clock, Test-Per-Scan BIST
Systems, Circular Self Test Path System, Memory BIST, Delay Fault BIST.

UNIT -V:
Boundary Scan Standard:
Motivation, System Configuration with Boundary Scan: TAP Controller and Port, Boundary Scan Test
Instructions, Pin Constraints of the Standard, Boundary Scan Description Language: BDSL
Description Components, Pin Descriptions.

TEXT BOOK:
1. Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits - M.L.
Bushnell, V. D. Agrawal, Kluwer Academic Pulishers.

REFERENCE BOOKS:
1. Digital Systems and Testable Design - M. Abramovici, M.A.Breuer and A.D Friedman, Jaico
Publishing House.
2. Digital Circuits Testing and Testability - P.K. Lala, Academic Press.

9
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

DEVICE MODELLING
(Core Elective –IV)

UNIT -I:
Introduction to Semiconductor Physics:
Review of Quantum Mechanics, Boltzman transport equation, Continuity equation, Poisson equation.
Integrated Passive Devices:
Types and Structures of resistors and capacitors in monolithic technology, Dependence of model
parameters on structures

UNIT -II:
Integrated Diodes:
Junction and Schottky diodes in monolithic technologies – Static and Dynamic behavior – Small and
large signal models – SPICE models
Integrated Bipolar Transistor:
Types and structures in monolithic technologies – Basic model (Eber-Moll) – Gunmel - Poon model-
dynamic model, Parasitic effects – SPICE model –Parameter extraction

UNIT -III:
Integrated MOS Transistor:
NMOS and PMOS transistor – Threshold voltage – Threshold voltage equations – MOS device
equations – Basic DC equations second order effects – MOS models – small signal AC
characteristics – MOS FET SPICE model level 1, 2, 3 and 4

UNIT -IV:
VLSI Fabrication Techniques: An overview of wafer fabrication, Wafer Processing – Oxidation –
Patterning – Diffusion – Ion Implantation – Deposition – Silicon gate nMOS process – CMOS
processes – n-well- p-well- twin tub- Silicon on insulator – CMOS process enhancements –
Interconnects circuit elements

UNIT -V:
Modeling of Hetero Junction Devices: Band gap Engineering, Band gap Offset at abrupt Hetero
Junction, Modified current continuity equations, Hetero Junction bipolar transistors (HBTs), SiGe

TEXT BOOKS:
1. Introduction to Semiconductor Materials and Devices – Tyagi M. S, 2008, John Wiley Student
Edition.
2. Solid State Circuits – Ben G. Streetman, Prentice Hall, 1997

REFERENCE BOOKS:
nd
1. Physics of Semiconductor Devices – Sze S. M, 2 Edition, Mcgraw Hill, New York, 1981.
2. Introduction to Device Modeling and Circuit Simulation – Tor A. Fijedly, Wiley-Interscience,
1997.
3. Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC
Press, 2011

10
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

SOFTWARE DEFINED RADIO

(Open Elective-II)

UNIT -I:
Introduction: The Need for Software Radios, What is Software Radio, Characteristics and benefits of
software radio- Design Principles of Software Radio, RF Implementation issues- The Purpose of RF
Front – End, Dynamic Range- The Principal Challenge of Receiver Design – RF Receiver Front- End
Topologies- Enhanced Flexibility of the RF Chain with Software Radios- Importance of the
Components to Overall Performance- Transmitter Architectures and Their Issues- Noise and
Distortion in the RF Chain, ADC and DAC Distortion.

UNIT -II:
Profile and Radio Resource Management: Communication Profiles- Introduction, Communication
Profiles, Terminal Profile, Service Profile , Network Profile, User Profile, Communication Profile
Architecture, Profile Data Structure, XML Structure, Distribution of Profile Data, Access to Profile
Data, Management of Communication Profiles, Communication Classmarks, Dynamic Classmarks for
Reconfigurable Terminals, Compression and Coding, Meta Profile Data

UNIT -III:
Radio Resource Management in Heterogeneous Networks: Introduction, Definition of Radio
Resource Management, Radio Resource Units over RRM Phases, RRM Challenges and
Approaches, RRM Modelling and Investigation Approaches, Investigations of JRRM in
Heterogeneous Networks, Measuring Gain in the Upper Bound Due to JRRM, Circuit-Switched
System, Packet-Switched System, Functions and Principles of JRRM, General Architecture of JRRM,
Detailed RRM Functions in Sub-Networks and Overall Systems

UNIT -IV:
Reconfiguration of the Network Elements: Introduction, Reconfiguration of Base Stations and
Mobile Terminals, Abstract Modelling of Reconfigurable Devices, the Role of Local Intelligence in
Reconfiguration, Performance Issues, Classification and Rating of Reconfigurable Hardware,
Processing Elements, Connection Elements, Global Interconnect Networks, Hierarchical Interconnect
Networks, Installing a New Configuration, Applying Reconfiguration Strategies, Reconfiguration
Based on Comparison, Resource Recycling, Flexible Workload Management at the Physical Layer,
Optimised Reconfiguration, Optimisation Parameters and Algorithms, Optimization Algorithms,
Specific Reconfiguration Requirements, Reconfiguring Base Stations, Reconfiguring Mobile Terminals

UNIT -V:
Object – Oriented Representation of Radios and Network Resources: Networks- Object Oriented
Programming- Object Brokers- Mobile Application Environments- Joint Tactical Radio System.
Case Studies in Software Radio Design: Introduction and Historical Perspective, SPEAK easy-
JTRS, Wireless Information Transfer System, SDR-3000 Digital Transceiver Subsystem, Spectrum
Ware, CHARIOT.

TEXT BOOKS:
1. Software Defined Radio Architecture System and Functions- Markus Dillinger, Kambiz Madani,
WILEY 2003
2. Software Defined Radio: Enabling Technologies- Walter Tuttle Bee, 2002, Wiley Publications.
REFERENCE BOOKS:
1. Software Radio: A Modern Approach to Radio Engineering - Jeffrey H. Reed, 2002, PEA
Publication.
2. Software Defined Radio for 3G - Paul Burns, 2002, Artech House.
3. Software Defined Radio: Architectures, Systems and Functions - Markus Dillinger, Kambiz
Madani, Nancy Alonistioti, 2003, Wiley.
4. Software Radio Architecture: Object Oriented Approaches to wireless System Enginering –
Joseph Mitola, III, 2000, John Wiley & Sons.

11
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

AD-HOC WIRELESS NETWORKS

(Open Elective II)

UNIT - I:
Wireless Local Area Networks
Introduction, wireless LAN Topologies, Wireless LAN Requirements,
Physical Layer- Infrared Physical Layer, Microwave based Physical Layer Alternatives, Medium
Access Control Layer- HIPERLAN 1 Sublayer, IEEE 802.11 MAC Sublayer and Latest
Developments-802.11a, 802.11b, 802.11g
Personal Area Networks: Introduction to PAN technology and Applications, Bluetooth -specifications,
Radio Channel, Piconets and Scatternets, Inquiry, Paging and Link Establishment, Packet Format,
Link Types, Power Management, Security, Home RF -Physical and MAC Layer

UNIT - II:
MAC Protocols
Introduction, Issues in Designing a MAC protocol for Ad Hoc Wireless Networks, Design goals of a
MAC Protocol for Ad Hoc Wireless Networks, Classifications of MAC Protocols, Contention - Based
Protocols, Contention - Based Protocols with reservation Mechanisms, Contention – Based MAC
Protocols with Scheduling Mechanisms, MAC Protocols that use Directional Antennas, Other MAC
Protocols.

UNIT - III:
Routing Protocols
Introduction, Issues in Designing a Routing Protocol for Ad Hoc Wireless Networks, Classification of
Routing Protocols, Table –Driven Routing Protocols, On – Demand Routing Protocols, Hybrid Routing
Protocols, Routing Protocols with Efficient Flooding Mechanisms, Hierarchical Routing Protocols,
Power – Aware Routing Protocols.

UNIT – IV:
Transport Layer Protocols
Introduction, Issues in Designing a Transport Layer Protocol for Ad Hoc Wireless Networks, Design
Goals of a Transport Layer Protocol for Ad Hoc Wireless Networks, Classification of Transport Layer
Solutions, TCP Over Ad Hoc Wireless Networks, Other Transport Layer Protocol for Ad Hoc Wireless
Networks.

UNIT – V:
Quality of Service in Ad Hoc Wireless Networks:
Introduction, Real Time Traffic Support in Ad Hoc Wireless Networks, QoS Parameters in Ad Hoc
Wireless Network, Issues and Challenges in providing QoS in Ad Hoc Wireless Networks,
Classification of QoS Solutions: MAC Layer Solutions, Cluster TDMA, IEEE 802.11e, DBASE,
Network Layer Solutions, QoS Routing Protocols, Ticket Based QoS Routing Protocol, Predictive
Location Based QoS routing protocol, Trigger Based Distributed QoS Routing Protocol, QoS enabled
AODV Routing Protocol, Bandwidth QoS Routing Protocol, On Demand QoS Routing Protocol, On
Demand Link-State Multipath QoS Routing Protocol, Asynchronous Slot Allocation Strategies. QoS
Frameworks for Ad Hoc Wireless Networks.

TEXT BOOKS:
1. Wireless Networks -P Nicopolitidis and M S Obaidat, Wiley India Edition 2003.
2. Ad Hoc Wireless Networks: Architectures and Protocols - C. Siva Ram Murthy and B.S.Manoj,
2004, PHI.
3. Wireless Ad- hoc and Sensor Networks: Protocols, Performance and Control - Jagannathan
Sarangapani, CRC Press.

12
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

SCRIPTING LANGUAGES
(Open Elective II)

UNIT -I:
Introduction to Scripts and Scripting:
Characteristics and uses of scripting languages, Introduction to PERL, Names and values, Variables
and assignment, Scalar expressions, Control structures, Built-in functions, Collections of Data,
Working with arrays, Lists and hashes, Simple input and output, Strings, Patterns and regular
expressions, Subroutines, Scripts with arguments.

UNIT -II:
Advanced PERL:
Finer points of Looping, Subroutines, Using Pack and Unpack, Working with files, Navigating the file
system, Type globs, Eval, References, Data structures, Packages, Libraries and modules, Objects,
Objects and modules in action, Tied variables, Interfacing to the operating systems, Security issues.

UNIT -III:
TCL:
The TCL phenomena, Philosophy, Structure, Syntax, Parser, Variables and data in TCL, Control flow,
Data structures, Simple input/output, Procedures, Working with Strings, Patterns, Files and Pipes,
Example code.

UNIT -IV:
Advanced TCL:
The eval, source, exec and up-level commands, Libraries and packages, Namespaces, Trapping
errors, Event-driven programs, Making applications 'Internet-aware', 'Nuts-and-bolts' internet
programming, Security issues, running untrusted code, The C interface.

UNIT -V:
TK and JavaScript:
Visual tool kits, Fundamental concepts of TK, TK by example, Events and bindings, Geometry
managers, PERL-TK.
JavaScript – Object models, Design Philosophy, Versions of JavaScript, The Java Script core
language, Basic concepts of Pythan.
Object Oriented Programming Concepts (Qualitative Concepts Only): Objects, Classes,
Encapsulation, Data Hierarchy.

TEXT BOOKS:
1. The World of Scripting Languages- David Barron, Wiley Student Edition, 2010.
2. Practical Programming in Tcl and Tk - Brent Welch, Ken Jones and Jeff Hobbs.,
Fourth edition.
th
3. Java the Complete Reference - Herbert Schildt, 7 Edition, TMH.

REFERENCE BOOKS:
1. Tcl/Tk: A Developer's Guide- Clif Flynt, 2003, Morgan Kaufmann SerieS.
nd
2. Tcl and the Tk Toolkit- John Ousterhout, 2 Edition, 2009, Kindel Edition.
3. Tcl 8.5 Network Programming book- Wojciech Kocjan and Piotr Beltowski, Packt
Publishing.
4. Tcl/Tk 8.5 Programming Cookbook- Bert Wheeler

13
 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech – I Year – II Sem. (DSCE)

EMBEDDED SYSTEMS LABORATORY

Note: Minimum of 10 Experiments have to be conducted

1. Write a simple program to print “hello world”

2. Write a simple program to show a delay.
3. Write a loop application to copy values from P1 to P2
4. Write a c program for counting the no of times that a switch is pressed & released.
5. Illustrate the use of port header file (port M) using an interface consisting of a keypad and
liquid crystal display.
6. Write a program to create a portable hardward delay.
7. Write a c program to test loop time outs.
8. Write a c program to test hardware based timeout loops.
9. Develop a simple EOS showing traffic light sequencing.
10. Write a program to display elapsed time over RS-232 link.
11. Write a program to drive SEOS using Timer 0.
12. Develop software for milk pasteurization system.

14