CSE 431

Computer Architecture
Fall 2004

Lecture 03: MIPS ALU Design Review

Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg431

[Adapted from Computer Organization and Design,

Patterson & Hennessy, © 2005, UCB]

CSE431 L03 MIPS ALU Design Review. 1 Irwin, PSU, 2004

 Review: MIPS Organization
Processor
Memory
1…1100
src1 Register File src1
addr 5 3 data
src2 32 2
addr 5 registers
dst ($zero - $ra) read/
addr 5 src2
write data data write
3 3 2 30
2 3
addr
2 32 bits word
2 s
br
3
read data
offset Add
3 PC 3 Add 2 3 3
2 2 3 2 2
4 write 0…1100
Fetch 3 2
PC = PC+4 2 data
3 0…1000
2 4 5 6 7 0…0100
3
Exec Decode
ALU 0 1 2 3 0…0000
2 3
32 word address
3 2
2 bits (binary)
byte address
(big Endian)

CSE431 L03 MIPS ALU Design Review. 2 Irwin, PSU, 2004

 Review: MIPS ISA
Category Instr Op Code Example Meaning
Arithmetic add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3
(R & I subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3
format) add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6
or immediate 13 ori $s1, $s2, 6 $s1 = $s2 v 6
Data load word 35 lw $s1, 24($s2) $s1 = Memory($s2+24)
Transfer store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1
(I format) load byte 32 lb $s1, 25($s2) $s1 = Memory($s2+25)
store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s1
load upper imm 15 lui $s1, 6 $s1 = 6 * 2 16
Cond. br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L
Branch br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L
(I & R
format) set on less than 0 and slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else
42 $s1=0
set on less than 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else
immediate $s1=0
Uncond. jump 2 j 2500 go to 10000
Jump jump register 0 and 8 jr $t1 go to $t1
(J & R
format) jump and link 3 jal 2500 go to 10000; $ra=PC+4
CSE431 L03 MIPS ALU Design Review. 3 Irwin, PSU, 2004
 Addressing Modes Review
1. Register addressing
op rs rt rd funct Register
word operand
2. Base addressing
op rs rt offset Memory
word or byte operand
base register
3. Immediate addressing
op rs rt operand
4. PC-relative addressing
op rs rt offset Memory
branch destination
Program Counter (PC) instruction
5. Pseudo-direct addressing
op jump address Memory
| jump destination
Program Counter (PC) | instruction
CSE431 L03 MIPS ALU Design Review. 4 Irwin, PSU, 2004
 Because ease of use is the purpose, this ratio of
function to conceptual complexity is the
ultimate test of system design. Neither
function alone nor simplicity alone defines a
good design.
The Mythical Man-Month, Brooks, pg. 43

CSE431 L03 MIPS ALU Design Review. 5 Irwin, PSU, 2004

 Review: Signed Binary Representation
2’sc binary decimal
-23 = 1000 -8
-(23 - 1) = 1001 -7
❑ Negate
1010 -6
1011 -5
1100 -4
1101 -3
1011
1110 -2
and add a 1 1111 -1
0000 0
1010
0001 1
0010 2
complement all the bits
0011 3
0100 4
0101 5
❑ Note: negate and 0110 6
invert are different! 23 - 1 = 0111 7
CSE431 L03 MIPS ALU Design Review. 6 Irwin, PSU, 2004
 MIPS Number Representations
❑ 32-bit signed numbers (2’s complement):
0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten maxint
0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten
...

0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten
0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten
1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten
1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten
...

minint
1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten
1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten

❑ Converting 16-bit values into 32-bit values

● copy the most significant bit (the sign bit) into the other bits
0010 -> 0000 0010
1010 -> 1111 1010
● sign extend versus zero extend (lb vs. lbu)

CSE431 L03 MIPS ALU Design Review. 7 Irwin, PSU, 2004

 Goal: Design a ALU for the MIPS ISA
zero ovf
❑ Must support the Arithmetic/Logic
operations of the ISA 1
1
add, addi, addiu, addu A
32
sub, subu, neg
ALU result
mult, multu, div, divu, sqrt 32
sll, srl, sra B
32 4
and, andi, nor, or, ori, xor, xori
m (operation)
beq, bne, slt, slti, sltiu, sltu

❑ Special handling for

● sign extend – addi, addiu andi, ori, xori, slti, sltiu
● zero extend – lbu
● no overflow detected – addu, addiu, subu, multu, divu, sltiu, sltu

CSE431 L03 MIPS ALU Design Review. 8 Irwin, PSU, 2004

 Building a 1-bit Binary Adder
carry_i A B carry_in carry_out S
n 0 0 0 0 0
0 0 1 0 1
A 1 bit 0 1 0 0 1
Full S 0 1 1 1 0
B Adder
1 0 0 0 1
1 0 1 1 0
carry_ou 1 1 0 1 0
t 1 1 1 1 1

S = A ⊕ B ⊕ carry_in (odd parity function)

carry_out = A&B | A&carry_in | B&carry_in

(majority function)

❑ How can we use it to build a 32-bit adder?

❑ How can we modify it easily to build an adder/subtractor?
CSE431 L03 MIPS ALU Design Review. 9 Irwin, PSU, 2004
 Building 32-bit Adder
c 0 =carry_in
A0 1-bit ❑ Just connect the carry-out of
FA S0
B0 the least significant bit FA to
c1 the carry-in of the next least
A1 1-bit significant bit FA and connect . . .
FA S1
B1
c2
A2 1-bit ❑ Ripple Carry Adder (RCA)
FA S2
B2
c3 ● advantage: simple logic, so small
(low cost)
...

● disadvantage: slow and lots of

c 31 glitching (so lots of energy
A 31 1-bit consumption)
FA S31
B31
c 32=carry_out

CSE431 L03 MIPS ALU Design Review. 10 Irwin, PSU, 2004

 Building 32-bit Adder/Subtractor
add/sub c 0 =carry_in
❑ Remember 2’s
A0 1-bit
complement is just FA S0
● complement all the bits B0 c1
control A1 1-bit
(0=add,1=sub) B 0 if control = 0, FA S1
B0 !B 0 if control = 1 B1
c2
A2 1-bit
FA S2
● add a 1 in the least
significant bit B2 c3

...
A 0111 → 0111
B - 0110 → + 1010 c 31
A 31 1-bit
FA S31
B31
c 32=carry_out

CSE431 L03 MIPS ALU Design Review. 11 Irwin, PSU, 2004

 Tailoring the ALU to the MIPS ISA
❑ Need to support the logic operation (and,nor,or,xor)

❑ Need to support the set-on-less-than instruction (slt)

● stores a 1 in rd if rs < rt and 0 otherwise
● use subtraction: (a - b) < 0 implies a < b

❑ Need to support test for equality (bne, beq)

● use subtraction: (a - b) = 0 implies a = b

❑ Need to add the overflow detection hardware

❑ Reminder: immediates are sign extended outside the

ALU with wiring (i.e., no logic needed)

CSE431 L03 MIPS ALU Design Review. 12 Irwin, PSU, 2004

 Modifying the ALU Cell for Logic Operations
❑ Logic operations operate on individual bits
$t2 = 0…0 0000 1101 0000
$t1 = 0…0 0011 1100 0000
and $t0, $t1, $t2 $t0 = 0…0 0000 1100 0000

add/sub carry_i op
n
❑ Modify the adder
to handle logic A
operations
resul
t

1-bit
FA
B

add/sub carry_ou
CSE431 L03 MIPS ALU Design Review. 13 t Irwin, PSU, 2004
 Modifying the ALU Cell for slt
add/sub carry_i op
n
A

resul
t
1-
B bit
FA
less

add/sub carry_ou
t

CSE431 L03 MIPS ALU Design Review. 14 Irwin, PSU, 2004

 Modifying the ALU for slt A0
❑ First perform a
subtraction (A - B) result
0
● $s0 = A and $s1 = B B0 +

less
❑ Make the result 1 if
A1
the subtraction yields
a negative result
result
● if $s0<$s1 set $t0=1 1
B1 +

❑ Make the result 0 if 0 less

the subtraction yields . . .

a positive result A 31
● tie the most
significant sum result3
bit (sign bit) to B31 +
1

the low order less 0 less

input set
CSE431 L03 MIPS ALU Design Review. 15 Irwin, PSU, 2004
 op
add/sub
A0 Modifying the ALU for Equality
result ❑ First perform
0 subtraction
B0 +

less

A1

result
1

...
B1 + zero
0 less

. . . ❑ Insert additional logic

A 31 to detect when all result
bits are zero
result3 ● Note zero is a 1
B31 + 1 when result is all
0 less
zeros
set
CSE431 L03 MIPS ALU Design Review. 16 Irwin, PSU, 2004
 Overflow Detection
❑ Overflow: the result is too large to represent in the
number of bits allocated
❑ Overflow occurs when
● adding two positives yields a negative
● or, adding two negatives gives a positive
● or, subtract a negative from a positive gives a negative
● or, subtract a positive from a negative gives a positive

❑ On your own: Prove you can detect overflow by:

● Carry into MSB xor Carry out of MSB

0 1 1 1 1 0
0 1 1 1 7 1 1 0 0 –4
+ 0 0 1 1 3 + 1 0 1 1 –5
1 0 1 0 –6 0 1 1 1 7
CSE431 L03 MIPS ALU Design Review. 17 Irwin, PSU, 2004
 op
add/sub
A0 Modifying the ALU for Overflow
result ❑ Modify the most
0 significant cell to
B0 +
determine overflow
less
output setting
A1

result
1

...
B1 + zero
0 less

. . . ❑ Disable overflow bit

A 31 setting for unsigned
arithmetic
result3
+
B31 1

0 less overflow
set u op
CSE431 L03 MIPS ALU Design Review. 18 Irwin, PSU, 2004
 But What about Performance?
❑ The critical path (the logic carry_in
path that determines the A0 0
1- result
speed of the circuit) of B0 bit
0
ALUcarry_out
ripple-carry adder is down carry_in
0
A1 1-
the carry chain 1
result
B1 bit
1
ALUcarry_out
carry_in
1
❑ For an n-bit adder where the A2 2 1- result
carry logic per ALU takes CP B2 bit
2
ALUcarry_out
time units that’s n*CP carry_in
2
A3 3 1-
● For CP = 0.010ns (10ps) that’s result
B3 bit
- 0.16ns for 16-bits ALU
3

- 0.32ns for 32-bits carry_out

...
3
● A 5GHz machine has a clock cycle
time of 200ps, so you’ve way carry_inn-1
missed your timing target! An-1 1- resultn-1
B n-1 bit
ALU
carry_ou
CSE431 L03 MIPS ALU Design Review. 19 Irwin, PSU, 2004
t
 Review: 1-bit Binary Adder
carry_i A B carry carry_ S carry
n _in out status
0 0 0 0 0 kill
A 1 bit 0 0 1 0 1 kill
Full S 0 1 0 0 1 propagate
B Adder 0 1 1 1 0 propagate
1 0 0 0 1 propagate
carry_ou 1 0 1 1 0 propagate
t 1 1 0 1 0 generate
1 1 1 1 1 generate

❑ The key to fast addition is a low latency carry network

❑ What matters is whether in a given position a carry is
● generated g = A & B
● propagated p = A ⊕ B

❑ Giving a carry recurrence of carry_out = g | p&carry_in

CSE431 L03 MIPS ALU Design Review. 20 Irwin, PSU, 2004
 Unrolling the Carry Recurrence
❑ Expanding the recurrence carry_out = g | p&carry_in
c0 = carry_in
c1 = g 0 | p 0&c0
c2 = g 1 | p 1&c1 = g 1 | p 1&g0 | p 1&p0&c0
...

ci+1 = g i | p i&gi-1 | … | pi&pi-1 …&p1&g0 | p i&pi-1…&p0&c0

❑ Note that all the p’s and g’s can be formed in parallel,
then all the carries can be formed in parallel,
then all the sums can be formed in parallel.
● approximately 3*CP, so 0.030ns for any size adder

❑ Except for fan-in and fan-out (real world) limitations on

computing the carries!
CSE431 L03 MIPS ALU Design Review. 21 Irwin, PSU, 2004
 Parallel Prefix Adders (PPAs)
❑ First define carry operator € g’ p’’ g
on (g,p) signal pairs ’ ’p
’
€
p = p’’& p’
❑ € is associative, i.e., g = g’’ |
p’’&g’
[(g’’’,p’’’) € (g’’,p’’)] € (g’,p’) = (g’’’,p’’’) € [(g’’,p’’) € (g’,p’)]

€ €

€ €

❑ And since € is associative, we can combine them pairwise

in any order we want
● but note that it is not commutative (but it doesn’t matter!)
CSE431 L03 MIPS ALU Design Review. 22 Irwin, PSU, 2004
 Parallel Prefix Adders, Con’t
❑ Given p and g terms for each bit position, computing all
the carries is equal to finding all the prefixes of
(g0,p0) € (g 1,p1) € (g 2,p2) € … € (g 30,p30) € (g 31,p31)
in parallel

❑ Measures to consider
p, g logic (1 unit delay)
● tree cell height (time)
● tree cell area; number of € cells
● cell fan-in and fan-out
parallel prefix logic tree
(1 unit delay per level) ● max wiring length
● wiring congestion
● delay path variation (glitching)

sum logic (1 unit delay)

CSE431 L03 MIPS ALU Design Review. 23 Irwin, PSU, 2004

 A 4-bit Example
❑ The unrolled carry equations
c 0 = carry_in c 1 = g0 | p 0 &c0 c 2 = g1 | p 1 &c1 = g 1 | p 1 &g 0 | p 1 &p 0 &c0
c3 = c 3 =
reminder €
g = g’’ |
g3 g2 g1 g0 p’’&g’
p3 p2 p1 p0 c 0 p = p’’& p’

€ € € €
g= g= g= g = g 0 | p 0 &c0 = c 1
p= p= p= p = p 0 &c0
€ € €
g= g=
p= p=
€
g=
p=
g=
p=
c4 c3 c2 c1
CSE431 L03 MIPS ALU Design Review. 24 Irwin, PSU, 2004
 A 4-bit Example
❑ The unrolled carry equations
c 0 = carry_in c 1 = g0 | p 0 &c0 c 2 = g1 | p 1 &c1 = g 1 | p 1 &g 0 | p 1 &p 0 &c0
c 3 = g2 | p 2 &c2 = g 2 | p 2 &g 1 | p 2 &p 1 &g 0 | p 2 &p 1 &p 0 &c0
c 4 = g3 | p 3 &c3 = g 3 | p 3 &g 2 | p 3 &p 2 &g 1 | p 3 &p 2 &p 1 &g 0 | p 3 &p 2 &p 1 &p 0 &c0
reminder €
g3 g2 g1 g0 g = g’’ |
p3 p2 p1 p0 p’’&g’
c0
p = p’’& p’
€ € € €
g = g 3 | p 3 &g2 g = g 2 | p 2 &g1 g = g 1 | p 1 &g0 g = g 0 | p 0 &c0 = c 1
p = p 3 &p2 p = p 2 &p1 p = p 1 &p0 p = p 0 &c0
€ € €
g = g 3 | p 3 &g2 | p 3 &p2 &(g 1 | p 1 &g0 ) g = g 1 | p 1 &g0 | p 1 &p0 &c0 = c 2
p = p 3 &p2 &p1 &p0 p = p 1 &p0 &c0
€
g = g 2 | p 2 &g1 | p 2 &p1 &(g 0 | p 0 &c0 ) = c 3
p = p 2 &p1 &p0 &c0
g = g 3 | p 3 &g2 | p 3 &p2 &g1 | p 3 &p2 &p1 &g0 | p 3 &p2 &p1 &p0 &c0 = c4
p = p 3 &p2 &p1 &p0 &c0
c4 c3 c2 c1
CSE431 L03 MIPS ALU Design Review. 25 Irwin, PSU, 2004
 A 16-bit Kogge-Stone Parallel Prefix Adder
g15 g14 g13 g12 g11 g10 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0
p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 c in

€ € € € € € € € € € € € € € € €

€ € € € € € € € € € € € € € €
Parallel Prefix
Computation

T = log 2n
€ € € € € € € € € € € € €

€ € € € € € € € €

€ c 15 c 14 c 13 c 12 c 11 c 10 c9 c8 c7 c6 c5 c4 c3 c2 c1

c 16
Tadd = T setup + (log 2n) t € + T sum = 0.060ns for 32-bits
CSE431 L03 MIPS ALU Design Review. 26 Irwin, PSU, 2004
 Shift Operations
❑ Also need operations to pack and unpack 8-bit
characters into 32-bit words
❑ Shifts move all the bits in a word left or right
sll $t2, $s0, 8 #$t2 = $s0 << 8 bits
srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits

op rs rt rd shamt funct
❑ Notice that a 5-bit shamt field is enough to shift a 32-
bit value 25 – 1 or 31 bit positions

❑ Such shifts are logical because they fill with zeros

CSE431 L03 MIPS ALU Design Review. 27 Irwin, PSU, 2004

 Shift Operations, con’t
❑ An arithmetic shift (sra) maintain the arithmetic
correctness of the shifted value (i.e., a number shifted
right one bit should be ½ of its original value; a
number shifted left should be 2 times its original
value)
● so sra uses the most significant bit (sign bit) as the bit
shifted in
● note that there is no need for a sla when using two’s
complement number representation
sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits
❑ The shift operation is implemented by hardware
separate from the ALU
● using a barrel shifter (which would takes lots of gates in
discrete logic, but is pretty easy to implement in VLSI)

CSE431 L03 MIPS ALU Design Review. 28 Irwin, PSU, 2004

 MIPS Multiply Instruction
❑ Multiplies generate a double precision result (product)
mult $s0, $s1 # hi||lo = $s0 * $s1

op rs rt rd shamt funct

● Low-order word of the product is left in processor register lo

and the high-order word is left in register hi
● Instructions mfhi rd and mflo rd are provided to move the
product to (user accessible) registers in the register file

❑ Multiplies are also done by dedicated hardware and are

much more complex (and much slower) than adders
❑ Dividers are even more complex and even slower

CSE431 L03 MIPS ALU Design Review. 29 Irwin, PSU, 2004

 MIPS Floating Point
❑ Need to add slides on MIPS floating point representation
and a little about how floating point arithmetic is done

CSE431 L03 MIPS ALU Design Review. 30 Irwin, PSU, 2004

 Review: MIPS ISA, so far
Category Instr Op Code Example Meaning
Arithmetic add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3
(R & I add unsigned 0 and 33 addu $s1, $s2, $s3 $s1 = $s2 + $s3
format) subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3
subt unsigned 0 and 35 subu $s1, $s2, $s3 $s1 = $s2 - $s3
add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6
add imm. unsigned 9 addiu $s1, $s2, 6 $s1 = $s2 + 6
multiply 0 and 24 mult $s1, $s2 hi || lo = $s1 * $s2
multiply unsigned 0 and 25 multu $s1, $s2 hi || lo = $s1 * $s2
divide 0 and 26 div $s1, $s2 lo = $s1/$s2, rem. in hi
divide unsigned 0 and 27 divu $s1, $s2 lo = $s1/$s2, rem. in hi
Logical and 0 and 36 and $s1, $s2, $s3 $s1 = $s2 & $s3
(R & I or 0 and 37 or $s1, $s2, $s3 $s1 = $s2 | $s3
format) xor 0 and 38 xor $s1, $s2, $s3 $s1 = $s2 xor $s3
nor 0 and 39 nor $s1, $s3, $s3 $s1 = !($s2 | $s2)
and immediate 12 andi $s1, $s2, 6 $s1 = $s2 & 6
or immediate 13 ori $s1, $s2, 6 $s1 = $s2 | 6
xor immediate 14 xori $s1, $s2, 6 $s1 = $s2 xor 6

CSE431 L03 MIPS ALU Design Review. 31 Irwin, PSU, 2004

 Review: MIPS ISA, so far con’t
Category Instr Op Code Example Meaning
Shift sll 0 and 0 sll $s1, $s2, 4 $s1 = $s2 << 4
(R srl 0 and 2 srl $s1, $s2, 4 $s1 = $s2 >> 4
format) sra 0 and 3 sra $s1, $s2, 4 $s1 = $s2 >> 4
Data load word 35 lw $s1, 24($s2) $s1 = Memory($s2+24)
Transfer store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1
(I format) load byte 32 lb $s1, 25($s2) $s1 = Memory($s2+25)
load byte unsigned 36 lbu $s1, 25($s2) $s1 = Memory($s2+25)
store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s1
load upper imm 15 lui $s1, 6 $s1 = 6 * 2 16
move from hi 0 and 16 mfhi $s1 $s1 = hi
move to hi 0 and 17 mthi $s1 hi = $s1
move from lo 0 and 18 mflo $s1 $s1 = lo
move to lo 0 and 19 mtlo $s1 lo = $s1

CSE431 L03 MIPS ALU Design Review. 32 Irwin, PSU, 2004

 Review: MIPS ISA, so far con’t
Category Instr Op Code Example Meaning
Cond. br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L
Branch br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L
(I & R set on less than 0 and slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else
format) 42 $s1=0
set on less than 0 and sltu $s1, $s2, $s3 if ($s2<$s3) $s1=1 else
unsigned 43 $s1=0
set on less than 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else
immediate $s1=0
set on less than 11 sltiu $s1, $s2, 6 if ($s2<6) $s1=1 else
imm. unsigned $s1=0
Uncond. jump 2 j 2500 go to 10000
Jump jump and link 3 jal 2500 go to 10000; $ra=PC+4
(J & R
format) jump register 0 and 8 jr $s1 go to $s1
jump and link reg 0 and 9 jalr $s1, $s2 go to $s1, $s2=PC+4

CSE431 L03 MIPS ALU Design Review. 33 Irwin, PSU, 2004

 Next Lecture and Reminders
❑ Next lecture
● Addressing and understanding performance
- Reading assignment – PH, Chapter 4

❑ Reminders
● HW1 due September 21 th
● Evening midterm exam scheduled
- Tuesday, October 19 th , 20:15 to 22:15, Location 112 Kern
- Please let me know ASAP (via email) if you have a conflict

CSE431 L03 MIPS ALU Design Review. 34 Irwin, PSU, 2004