2 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.

 LAB MANUAL FOR LOGIC DESIGN LAB
Objective: To understand the digital logic and create various systems by
using these logics.
1. Introduction to digital electronics lab- nomenclature of digital ICs,
specifications, study of the data sheet, concept of V cc and ground, verification
of the truth tables of logic gates using TTL ICs.
2. Implementation of the given Boolean function using logic gates in both
SOP and POS forms.
3. Verification of state tables of RS, JK, T and D flip-flops using NAND &
NOR gates.
4. Implementation and verification of Decoder/De-multiplexer and Encoder
using logic gates.
5. Implementation of 4x1 multiplexer using logic gates.
6. Implementation of 4-bit parallel adder using 7483 IC.
7. Design, and verify the 4-bit synchronous counter.
8. Design, and verify the 4-bit asynchronous counter.
9. Mini Project.

3 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
4 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,
DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 EXPERIMENT - 1

Aim:-
Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of
the data sheet, concept of Vcc and ground, verification of the truth tables of logic gates
using TTL ICs.

Apparatus Required:-
Digital lab kit, single strand wires, breadboard, TTL IC’s

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function, which it
performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan out or it may refer to anon-ideal physical device.

The main hierarchy is as follows:-

1. Basic Gates

2. Universal Gates

3. Advanced Gates

5 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Basic Gates
1. AND gate: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-

Input A Input B Output

1 1 1

1 0 0

0 1 0

0 0 0

IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify the
statement:-

Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 1

6 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 IC 7432

3. NOT gate: -Function of NOR gate is to reverse the nature of the input .It
converts true input to false and vice versa. Following table justifies the statement :-

Input Output

1 0

0 1

IC 7404

7 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Universal Gates
1. NAND gate: -Function of NAND gate is to give true output when one of the
two provided input are false. In the remaining output is true case .Following table
justifies the statement :-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1

IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input
are false. In all the other cases output remains false. Following table justifies the
statement :-

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1

8 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 IC 7402
Advanced Gates
1. XOR gate: - The function of XOR gate is to give output true only when both the
inputs are true. Following table explain this:-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136

9 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Procedure:-
 Place the breadboard gently on the observation table.
 Fix the IC which is under observation between the half shadow line of
breadboard, so there is no shortage of voltage.
 Connect the wire to the main voltage source (Vcc) whose other end is connected
to last pin of the IC (14 place from the notch).
 Connect the ground of IC (7th place from the notch) to the ground terminal
provided on the digital lab kit.
 Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using
connecting wires.(In accordance to IC provided).

 Connect output pins to the led on digital lab kit.

 Switch on the power supply.

 If led glows red then output is true, if it glows green output is false, which is
numerically denoted as 1 and 0 respectively. The Color can change based on the
IC manufacturer it’s just verification of the Truth Table not the color change.

Result:-
All gates are verified. Observed output matches theoretical concepts.

Precautions:-
 All connections should be made neat and tight.
 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.

Pre Experiment Questions:-

1. What is a logic gate?

Ans: Logic gate is a physical device implementing a Boolean function and performs

Logical operation on one or more logic inputs and produces a single logic output.

2. What are universal gates?

Ans: NAND and NOR gates are called universal gates as any type of logic gates or logic

Functions can be implemented by these gates.

10 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 3. What are basic gates?

Ans: AND, OR, Not are called basic gates.

4. State De-Morgan’s theorem.

Ans: (x+y)l = xlyl

(xy)l = xl + yl

5. What is the primary motivation for using Boolean algebra to simplify

logic expressions?

Ans: (1) Boolean algebra reduces the number of inputs required.

(2) It will reduce number of gates

(3) It makes easier to understand the overall function of the circuit.

Post Experiment Questions:-

1. Which of the logical operations is represented by the + sign in Boolean

algebra? Ans: OR gate

2. Which of the two input logic gate can be used to implement an inverter

circuit? Ans: Ex-NOR gate

3. Which are the logic gates whose all output entries are logic 1 except for one
entry there is logic 0?

Ans: NAND and NOR gate

4. TTL operates from a 5 volt supply.

5. When the output of a NOR gate is high?

Ans : If all the inputs are low

11 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 EXPERIMENT- 3

Aim: -Verification of state tables of

1. R-S flip-flop
2. J - K flip-flop
3. T Flip-Flop
4. D Flip-Flop

Using NAND and NOR gates.

Apparatus:- IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

Theory: -In case of sequential circuits the effect of all previous inputs on the
outputs is represented by a state of the circuit. Thus, the output of the circuit at any time
depends upon its current state and the input. These also determine the next state
of the circuit. The relationship that exists among the inputs, outputs, present states
and next states can be specified by either the state table or the state diagram.

State Table: -The state table representation of a sequential circuit consists of

three sections labelledpresent state next stateand output. T he p r e sen t s t a t e
d e s i gn a t e s t h e s t a t e o f f l i p - f l op s be f o re t h e occurrence of a clock
pulse. The next state shows the states of flip-flops after the clock pulse, and the
output section lists the value of the output variables during the present state.

Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop.It can store
either 0or 1. Flip-flops are classifieds according to the number of inputs.

R-S Flip-Flop:- The circuit is similar to SR latch except enable signal is replaced by
clock pulse.

12 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Logic Diagram

Characteristic table for S-R flip flop

D Flip-Flop:-The modified clocked SR flip-flop is known as D-flip-flop.From the truth

tableof SR flip-flop we see that the output of the SR flip-flop is in unpredictable state
when the inputsare same and high. In many practical applications, these input conditions
are not required. These inputconditions can be avoided by making then complement of
each other.

Logic Diagram

13 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Characteristic table for D flip flop

J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output.

The RSflip-flop circuit may be re-joined if both inputs are 1 than also the outputs are
complement of each other.

Logic Diagram

Characteristic table for J-K flip flop

14 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is modification of
the J-K f l i p - f l op . Bot h t h e J K i np ut s of t h e J K f l i p - f l o p a r e h e
ld at
l o gic 1 an d t h e c l oc k s i gn a l continuous to change.

Logic Diagram

Characteristic table for T flip flop

Procedure:-
1. Co nn e c t i o n s a r e m a d e as p er ci rc ui t di a gr a m.
2. Verify truth-tables for various combinations of input .

RESULT: -Study and verified truth-tables of various flip-flops.

15 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
Precaution:-
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc
5. The circuit should be off before change the connections.6.After
completing the experiment switch off the supply to apparatus.

Pre Experiment Questions:-

1) What is a latch?

Ans: Storage elements that operate with signal levels are referred to as latches.

2) What is a flip flop?

Ans: Storage elements controlled by a clock transitions are called flip flop.

3) Differentiate between a latch and a flip flop.

Latch Flip flop
1) A latch checks all its inputs 1) Flip flop samples its inputs and
continuously and changes its changes its outputs only at a time
outputs accordingly at any time. as determined by a clocking
signal.
2) No clock is used 2) A clock is used

4) Differentiate between combinational and sequential circuits.

Combinational circuits. Sequential circuits.

1) A circuit whose output is 1) It depends on present and past

dependent only on the inputs at history of the inputs
that instant
2) Easy to design 2) Harder to design
3) More expensive circuit 3) Cheaper circuit

5) What happens to the JK flip flop if the J input is treated as an inverter is wired
between J and K inputs?
Ans: JK flip flop becomes D flip flop

Post Experiment Questions:-

1) How is a JK flip flop made to
toggle? Ans : If J=1 and K=1

16 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.
 2) When a JK flip flop isis in a no change
condition? Ans: If J=0 and K=0

3) Which is the basic sequential building block in which the output follows the data
input as long as the enable input is active?

Ans: D latch

4) Define the characteristic equation of a flip flop.

Ans: The algebraic description of the next state of the flip flop is called characteristic

equation.

5) How many stable states a flip flop has?

Ans: 2 stable states

17 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

DRONACHARYA GROUP OF INSTITUTIONS, GR. NOIDA.