JSPM’s

Imperial College of Engineering and Research, Wagholi, Pune.

(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

Q.1) Draw and explain flag structure of 8051 in detail. [5] (Oct 2022)
Flag Register in 8051
The 8051 microcontroller includes a special-purpose register known as the Program Status
Word (PSW) register, which contains several flags. The PSW register is an 8-bit register
located at address 0xD0 in the memory. Here’s the detailed structure of the PSW register:

 Carry Flag (CY):

Bit 7: This flag indicates whether a carry was generated out of the most significant bit during an
arithmetic operation.
Set: When the result of an addition operation produces a carry or when a borrow is needed in a
subtraction operation.
Cleared: When there is no carry or borrow.
 Auxiliary Carry Flag (AC):
Bit 6: This flag is used mainly in BCD (Binary-Coded Decimal) operations.
Set: When there is a carry from bit 3 to bit 4 during addition or a borrow from bit 4 to bit 3
during subtraction.
Cleared: When there is no such carry or borrow.
 User Flag 0 (F0):
Bit 5: This is a user-defined flag. It’s not used by the 8051’s hardware but can be used by the
programmer for various purposes.
 Register Bank Select Bits (RS1, RS0):
Bits 4 and 3: These bits select one of the four register banks in the internal RAM.

RS1(Bit 4) RS0 (Bit 4) Register Bank Address

0 0 Register Bank 0 (R0-R7 at addresses 0x00-0x07)
0 1 Register Bank 1 (R0-R7 at addresses 0x08-0x0F)
1 0 Register Bank 2 (R0-R7 at addresses 0x10-0x17)
1 1 Register Bank 3 (R0-R7 at addresses 0x18-0x1F)

 Overflow Flag (OV):

Bit 2: This flag indicates whether an overflow has occurred during arithmetic operations.
Set: When the result of a signed arithmetic operation (addition or subtraction) exceeds the
range that can be represented with the given number of bits.
Cleared: When there is no overflow.
 User Defined Flag (UD):
Bit 1: This is another user-defined flag. Like F0, it's not used by the hardware but can be utilized
by programmers for specific purposes.
 Parity Flag (P):
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
Bit 0: This flag indicates the parity of the result of the most recent operation. It shows whether
the number of 1s in the result is odd or even.
Set: When the number of 1s is even (even parity).
Cleared: When the number of 1s is odd (odd parity).
PSW Register Usage
Program Control: The flag register (PSW) is used in conjunction with conditional jumps and
other instructions to control the flow of the program based on the results of arithmetic and
logical operations.
Interrupts: Certain flags can influence the behavior of interrupts, particularly the Carry and
Overflow flags.

Q.2) Write an embedded C program to transmit character ‘D’ Serially at baud rate of
4800. [5] (Oct 2022)
Solution:
#include <reg51.h>
void main(void)
{
TMOD=0x20; //use Timer 1, mode 2
TH1=0xFA; //4800 baud rate
SCON=0x50;
TR1=1;
while (1)
{
SBUF=‘D’; //place value in buffer
while (TI==0);
TI=0;
}}
Q.3) Explain the functional diagram of Timer in 8051. [5] (Oct 2022)
Timer 0 & Timer 1:
Timers used to provide accurate time delay based upon application.
Both are 16 bit timer.
It can used as timer / counter .
These are up counter .
Timer 0 register of 16 bit is classified by two 8 bit registers TH0 & TL0
First we load the TL0 , after is get overflow then TH0 is loaded .
It has physical internal address Timer are up counter.
Timer : count internal clock
counter : count external clock pulses
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

 16-bit Timer Counter:

TL0/TL1: The low byte of Timer 0/1.
TH0/TH1: The high byte of Timer 0/1.
 Mode Selection:
Mode 0: 13-bit Timer mode.
Mode 1: 16-bit Timer mode.
Mode 2: 8-bit Auto-Reload mode.
Mode 3: Split Timer mode (only for Timer 0).
 Timer Control Register (TCON):
TFx: Timer overflow flag, set when the timer overflows.
TRx: Timer run control bit, used to start or stop the timer.
IE0/IE1: External interrupt flags.
 Timer Mode Register (TMOD):
Gate: Controls whether the timer is controlled by external hardware or software.
C/T: Selects between Timer mode and Counter mode.
M1/M0: Selects the mode of operation (Mode 0, Mode 1, Mode 2, or Mode 3).
 16-bit Timer Counter:
TL0/TL1: The low byte of Timer 0/1.
TH0/TH1: The high byte of Timer 0/1.
 Mode Selection:
Mode 0: 13-bit Timer mode.
Mode 1: 16-bit Timer mode.
Mode 2: 8-bit Auto-Reload mode.
Mode 3: Split Timer mode (only for Timer 0).
 Timer Control Register (TCON):
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
TFx: Timer overflow flag, set when the timer overflows.
TRx: Timer run control bit, used to start or stop the timer.
IE0/IE1: External interrupt flags.
 Timer Mode Register (TMOD):

Gate: Controls whether the timer is controlled by external hardware or software.

C/T: Selects between Timer mode and Counter mode.
M1/M0: Selects the mode of operation (Mode 0, Mode 1, Mode 2, or Mode 3).

Q.4) Explain the interrupt structure of 8051 with vector address. [5] (Oct 2022) (Sep
2023)
Interrupts are basically the events that temporarily suspend the main program, pass the
control to the external sources and execute their task.
It then passes the control to the main program where it had left off.
8051 has five interrupts. These interrupts are INT0, INT1, TO , T1 , TI/RI.
All of the interrupts can be enabled or disabled by using the IE (interrupt enable) register.
The interrupt addresses of these interrupts are like below –

Interrupt Address

INT0 0003H

INT1 000BH

T0 0013H

T1 001BH

TI/RI 0023H

Interrupt Enable (IE)Register

This register can be used to enable or disable interrupts programmatically.
This register is an SFR.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

BitAddress AF AE AD AC AB AA A9 A8

Bit Details EA X X ES ET EX1 ET0 EX0

1

The address is A8H. This byte is bit addressable. So it can be programmed by the user.
The bits in this register has a different meaning. The register structure is looking like this
This register can be used to enable or disable interrupts programmatically.
This register is an SFR.
The address is A8H. This byte is bit addressable. So it can be programmed by the user.
The bits in this register has a different meaning. The register structure is looking like this

Bit High Value(1) Low Value(0)

Details

EA Least significant 5 bits can decide Disable all five interrupts. It just
enable or disable of these five ignores the rest five bits.
interrupts.

ES Enable Serial Port Interrupt Disable Serial Port Interrupt

ET1 Enable Timer1 interrupt Disable Timer1 interrupt

EX1 Enable external interrupt 1 (INT1) Disable external interrupt 1 (INT1)

ET0 Enable Timer0 interrupt Disable Timer0 interrupt

EX0 Enable external interrupt 0 (INT0) Disable external interrupt 0 (INT0)

Interrupt Priority (IP) Register

All of these five interrupts can be in one or two interrupt level.
The priority levels are level 1 and level 0.
Priority level 1 indicates the higher priority, and level 0 indicates lower priority.
This IP register can be used to store the priority levels for each interrupt.
This is also a bit addressable SFR. Its address is B8H.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

BitAddress BF BE BD BC BB BA B9 B8

Bit Details X X X PS PT1 PX1 PT0 PX0

Bit Details High Value(1) Low Value(0)

PS Set 1 level priority of Serial port Set 0 level priority of Serial port
interrupt interrupt

PT1 Set 1 level priority of Timer1 interrupt Set 0 level priority of Timer1
interrupt

PX1 Set 1 level priority of external Set 0 level priority of external

interrupt 1 (INT1) interrupt 1 (INT1)

PT0 Set 1 level priority of Timer0 interrupt Set 0 level priority of Timer0
interrupt

Q.5) Explain functioning of Port 3 in details for 8051. [5] (Oct 2022)
Port 3 in the 8051 microcontroller is a versatile I/O port that can serve multiple functions
beyond just simple digital I/O. Understanding its functionality involves looking at both its
basic I/O capabilities and its additional special functions. Here’s a detailed explanation of Port
3:
Overview of Port 3
 Address: Port 3 is an 8-bit bi-directional port and is located at memory address 0xB0 in
the 8051's internal I/O address space.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
 Pins: Port 3 consists of 8 pins: P3.0 through P3.7.
 Control: Each pin in Port 3 can be individually configured as an input or output, and they
have additional special functions.
Special Functions of Port 3
Port 3 is not just an I/O port; it has several special functions assigned to each of its pins. These
functions are related to various hardware features of the 8051 microcontroller. Here’s a
detailed breakdown of these functions:
Pin Function Description
P3.0 RXD Serial Receive Data input for UART communication.
P3.1 TXD Serial Transmit Data output for UART communication.
P3.2 INT0 External Interrupt 0 input.
P3.3 INT1 External Interrupt 1 input.
P3.4 T0 Timer 0 external input (capture or gate mode).
P3.5 T1 Timer 1 external input (capture or gate mode).
P3.6 WR External Data Memory Write signal.
P3.7 RD External Data Memory Read signal.
Functional Details
1. UART Communication (P3.0 and P3.1):
o RXD (P3.0): This pin is used for receiving serial data. It is the input line for the
UART (Universal Asynchronous Receiver/Transmitter).
o TXD (P3.1): This pin is used for transmitting serial data. It is the output line for
the UART.
2. External Interrupts (P3.2 and P3.3):
o INT0 (P3.2): This pin is used to trigger an external interrupt 0. It can be
configured to trigger on a low level, falling edge, or rising edge.
o INT1 (P3.3): This pin is used to trigger an external interrupt 1. It can be
configured similarly to INT0.
3. Timer Inputs (P3.4 and P3.5):
o T0 (P3.4): This pin is used for Timer 0 external input. It can be used for
capturing external events or for gating Timer 0.
o T1 (P3.5): This pin is used for Timer 1 external input. Like T0, it can be used for
capturing external events or for gating Timer 1.
4. Memory Control (P3.6 and P3.7):
o WR (P3.6): This pin is used as a Write signal to external memory. It indicates
when the 8051 is writing data to external memory.
o RD (P3.7): This pin is used as a Read signal from external memory. It indicates
when the 8051 is reading data from external memory.
Configuration and Usage
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
To use Port 3 for its special functions, you generally need to configure the corresponding
peripheral or interrupt in the microcontroller.

Q.6) Write an embedded C program to display hex counter on LEDs connected to port 2.
[5] (Oct 2022)
#include <reg51.h> // Include the header file for the 8051 microcontroller
void delay (unsigned int time) // Function to provide a delay
{
unsigned int i, j;
for (i = 0; i < time; i++)
{
for (j = 0; j < 1275; j++); // Adjust loop count for desired delay
}}
void main(void) // Main function
{ unsigned char counter;
while (1)
{
for (counter = 0x00; counter <= 0xFF; counter++)
{
P2 = counter; // Display the counter value on Port 2
delay(1000); // Delay to make the count visible
}} }
Q.7) Draw and explain internal memory organization of 8051. [5] (Sep 2023)
The 8051 microcontroller has a specific internal memory organization, which includes several
different types of memory areas. Understanding this organization is crucial for efficient
programming and utilization of the 8051's resources. Here’s a detailed breakdown and
diagram of the internal memory organization of the 8051 microcontroller.
Internal Memory Organization of 8051
The 8051 microcontroller has three main types of internal memory:
1. Program Memory (ROM): This is used to store the executable code.
Data Memory (RAM): This is used for data storage and variable manipulation during program
execution.
Special Function Registers (SFRs): These are used to control and monitor the
microcontroller’s peripherals and features.
Here’s a detailed breakdown of each memory type:
1. Program Memory (ROM)
Size: Typically 4 KB in a standard 8051, located at addresses 0x0000 to 0x0FFF.
Purpose: Stores the executable code (program instructions).
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
Characteristics: This memory is read-only. It cannot be modified during normal operation
(though some variants support Flash memory which can be reprogrammed).
2. Data Memory (RAM)
Size: 128 bytes in the standard 8051 microcontroller.
Address Range: 0x00 to 0x7F.
Divided Into:
Register Bank: 4 banks of 8 registers each (R0 to R7).
Bit Addressable Area: 16 bytes (from 0x20 to 0x2F).
Scratchpad RAM: 80 bytes (from 0x30 to 0x7F).
3. Special Function Registers (SFRs)
Size: 128 bytes, located at addresses 0x80 to 0xFF.
Purpose: Used to control and monitor peripherals and features such as timers, serial
communication, interrupts, and I/O ports.
Characteristics: Each SFR has a specific function, and their addresses are predefined.
Internal Memory Map: graphical representation of the internal memory map of the 8051:
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

Detailed Memory
1. Program Memory (ROM):
o Address range: 0x0000 to 0x0FFF
o Contains the machine code instructions.
2. Data Memory (RAM):
o Register Banks:
 Bank 0: Registers R0 to R7 (0x00 to 0x07)
 Bank 1: Registers R0 to R7 (0x08 to 0x0F)
 Bank 2: Registers R0 to R7 (0x10 to 0x17)
 Bank 3: Registers R0 to R7 (0x18 to 0x1F)
o Bit Addressable Area:
 Address range: 0x20 to 0x2F
 16 bytes that can be addressed bit by bit.
o Scratchpad RAM:
 Address range: 0x30 to 0x7F
 General-purpose RAM for temporary data storage.
3. Special Function Registers (SFRs):
o Address range: 0x80 to 0xFF
o Includes control and status registers such as:
 I/O Ports: P0, P1, P2, P3
 Timers: TMOD, TCON, TH0, TL0, TH1, TL1
 Serial Communication: SCON, SBUF
 Interrupts: IE, IP
 Control Registers: PCON, PSW
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

Q.8) Calculate hexadecimal count to generate delay of 50 msec using Timer 1, mode 1,
use clock frequency = 11.0592MHz. [5] (Sep 2023)

Q.9) What are the different modes of operation of serial communication in 8051 Explain
SMOD registers? [5] (Sep 2023)
The 8051 microcontroller supports serial communication via its UART (Universal
Asynchronous Receiver/Transmitter) interface. The UART in the 8051 operates in several
modes, each suitable for different serial communication needs. Additionally, the SMOD (Serial
Mode) bits play a crucial role in configuring the UART's operation.
Serial Communication Modes in 8051
The UART in the 8051 microcontroller supports four different modes of operation. These
modes are configured using the Serial Control (SCON) register:
1. Mode 0: Shift Register Mode
o Characteristics:
 8-bit data shift register.
 No start or stop bits; data is shifted in and out serially.
 Data format: 8 bits.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
 Baud rate: Fixed at the clock frequency divided by 32.
o Use Case: Used for communication with devices that have a fixed serial protocol.
2. Mode 1: 8-bit UART Mode
o Characteristics:
 8-bit data frame with start and stop bits.
 Data format: 1 start bit, 8 data bits, 1 stop bit.
 Baud rate: Variable, can be set by Timer 1.
o Use Case: The most commonly used mode, suitable for general-purpose
asynchronous communication.

3. Mode 2: 9-bit UART Mode

o Characteristics:
 9-bit data frame with start and stop bits.
 Data format: 1 start bit, 9 data bits, 1 stop bit.
 Baud rate: Variable, can be set by Timer 1.
o Use Case: Useful when 9-bit data communication is required.
4. Mode 3: 9-bit UART with Variable Baud Rate
o Characteristics:
 Similar to Mode 2, but allows for variable baud rates using Timer 1.
 Data format: 1 start bit, 9 data bits, 1 stop bit.
 Baud rate: Can be set to different rates by Timer 1.
o Use Case: Allows for flexible baud rate configurations while using 9-bit data
format.
SMOD (Serial Mode) Register
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
In the standard 8051 architecture, the term SMOD does not explicitly refer to a dedicated
register. Instead, the baud rate is typically controlled by Timer 1, and the SCON register is
used to select the mode of operation.
However, the concept of SMOD is sometimes used in extended or enhanced 8051
microcontrollers to denote a bit or setting that affects the baud rate. For example:
SMOD Bit: In some variants of the 8051, an SMOD bit (often found in the PCON register) is used
to double the baud rate of the UART. Setting the SMOD bit changes the divisor for the baud rate
calculation.

Q.10) Compare RISC and CISC processor. [5] (Sep 2023)

Below are a few differences between RISC and CISC:

CISC RISC

Very few instructions are present. The

A large number of instructions are
number of instructions is generally less than
present in the architecture.
100.

Some instructions with long execution No instruction with a long execution time
times. These include instructions that due to a very simple instruction set. Some
copy an entire block from one part of early RISC machines did not even have an
memory to another and others that integer multiply instruction, requiring
copy multiple registers to and from compilers to implement multiplication as a
memory. sequence of additions.

Variable-length encodings of the Fixed-length encodings of the instructions

instructions. are used.
Example: IA32 instruction size can Example: In IA32, generally all instructions
range from 1 to 15 bytes. are encoded as 4 bytes.

Multiple formats are supported for

specifying operands. A memory Simple addressing formats are supported.
operand specifier can have many Only base and displacement addressing is
different combinations of displacement, allowed.
base, and index register.

CISC supports array. RISC does not support an array.

Arithmetic and logical operations only use

Arithmetic and logical operations can be
register operands. Memory referencing is
applied to both memory and register
only allowed by loading and storing
operands.
instructions.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution

CISC RISC

Implementation programs are hidden

Implementation programs exposed to
from machine-level programs. The ISA
machine-level programs. Few RISC machines
provides a clean abstraction between
do not allow specific instruction sequences.
programs and how they get executed.

Condition codes are used. No condition codes are used.

Registers are being used for procedure

The stack is being used for procedure arguments and return addresses. Memory
arguments and returns addresses. references can be avoided by some
procedures.

Successful pipeline with one instruction

Unsuccessful pipeline
per cycle

Heavy use of RAM More efficient use of RAM

Q.11) Enlist various modes of operation of Timer & Explain in details. [5] (Sep 2023)
The 8051 microcontroller has two timers/counters: Timer 0 and Timer 1. Each of these
timers can operate in various modes. The modes determine how the timers count and how
they can be used. Below are the various modes of operation for these timers and a detailed
explanation of each mode.
Timer Modes of Operation
The 8051 timers can be configured in the following modes:
1. Mode 0: 13-bit Timer Mode
2. Mode 1: 16-bit Timer Mode
3. Mode 2: 8-bit Auto-Reload Mode
4. Mode 3: Split Timer Mode (only for Timer 0 in some variants of the 8051)
Detailed Explanation of Each Mode
1. Mode 0: 13-bit Timer Mode
 Description: In Mode 0, the timer functions as a 13-bit timer. The timer is essentially a
16-bit register, but only 13 bits are used for counting. The lower 5 bits (TLx) and the
upper 8 bits (THx) are used to form the 13-bit counter.
 Operation:
o The timer counts from 0x0000 to 0x1FFF.
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
(Approved by AICTE, Delhi & Govt. of Maharashtra, affiliated to SPPU,
Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
Previous SPPU Insem Question Paper Solution
o When the timer overflows from 0x1FFF, it rolls over to 0x0000.
 Baud Rate: The timer frequency is the system clock frequency divided by 12, and the
baud rate is set by Timer 0.

Mode 1: 16-bit Timer Mode

 Description: In Mode 1, the timer operates as a 16-bit timer. It uses both the high byte
(THx) and the low byte (TLx) of the timer register.
 Operation:
o The timer counts from 0x0000 to 0xFFFF.
o When the timer overflows from 0xFFFF, it rolls over to 0x0000.
 Baud Rate: The timer frequency is the system clock frequency divided by 12, and the
baud rate can be set using Timer 1.

Mode 2: 8-bit Auto-Reload Mode

 Description: In Mode 2, the timer operates as an 8-bit timer with automatic reload
capability. The timer uses only the low byte (TLx) for counting, while the high byte
(THx) holds the reload value.
 Operation:
 JSPM’s
Imperial College of Engineering and Research, Wagholi, Pune.
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Pune)
Gat.No.720,Pune-Nagar road,Wagholi,Pune,412207
Department of Electronics and Telecommunication Engineering
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o The timer counts from 0x00 to 0xFF.
o After reaching 0xFF, it automatically reloads the value from THx and continues
counting.
 Baud Rate: Useful for generating precise baud rates, as the timer can be reloaded
automatically at regular intervals.

Mode 3: Split Timer Mode

 Description: Mode 3 is available only for Timer 0 in some enhanced versions of the
8051 microcontroller. In this mode, Timer 0 is split into two 8-bit timers: Timer 0 (TL0)
and Timer 0 (TH0). Timer 0 operates in 8-bit mode while Timer 1 operates in Mode 1 or
Mode 2.
 Operation:
o In this mode, Timer 0 is effectively split into two separate timers, each
functioning as an 8-bit timer.
 Baud Rate: Timer 1 is used for generating baud rates in the same way as Mode 2.