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Practice Problems on Adders, Subtractors Multiplexer and
Decoder
1. Design 4-bit Full Adder /Subtractor
2. Simplified expression of half adder carry is ___________________ A. c=xy+x B. c=y+x C. c=xy+y D. c=xy 3. Implement half adder circuit using 4: 1 MUX or multiplexers only 4. Implement the Boolean Function using 8:1 /4:1 mux with MSB and LSB methods • F (A, B, C, D) = ∑m(0,1,2,3,4,9,13,14,15) • F (P, Q, R, S) = ∑m(0,1,2,3,11,12,14,15) • F (P, Q, R, S) = πM(0,1,3,7,9,10,11,13,14,15) • F (A, B, C, D) = ∑m(0,1,2,3,5,7,10,11,12) +∑d(2,4,8,9) • Y=ABC+A’B’D+BC’D+AC’D’ 5. Implement Full subtractor using 4:1 mux 6. Implement 3:8 decoder for • f(x,y,z)= ∑m(0,4,5,6) • f1(x,y,z)= ∑m(1,5,7) • f2(x,y,z)= ∑m(2,3,4,5,6) 7. In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is
8. The Boolean function f implemented in the figure using two input multiplexers is