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Pre-Lab 2

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38 views3 pages

Pre-Lab 2

Uploaded by

SILENT KILLER GAMING
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TECH 158 - Digital Electronics (Winter 2024)

Lab #2: Ripple Counters

OBJECTIVES:
 Construct a 4-bit ripple up-counter with J-K flip-flops
 Construct a 4-bit ripple down-counter with J-K flip-flops
 Construct a MOD-12 counter using a 4-bit asynchronous counter IC

MATERIALS:
[1] 74LS93 4-bit Asynchronous Counter [2]74LS73 Dual J-K Flip-Flops
[1]74LS00 Quad NAND Gates

INFORMATION:
Ripple counters
Except for the least significant bit (LSB) each flip-flop of a ripple counter uses either Q or Q’ output of an adjacent
flip-flop as its clock input. As a consequence, there is a delay between the clock inputs of two adjacent flip-flops.
For counters consist of a large number of flip-flops, this delay does accumulate, which is a major drawback of
ripple counters. On the other hand, even though all FFs are permanent toggles, the counting sequence is
automatically controlled since either Q or Q’ output of a flip-flop is used as the clock input of the next flip-flop.
That is, each flip-flop sees an active clock edge only when necessary. Therefore, there is no need to have external
gating to ensure a proper counting sequence. For example, Fig. 1 shows the counting sequence of a 3-bit ripple
up counter. The flip-flop, which corresponds to 20 is clocked by an external clock source, Cp0, whereas 21 uses Q
of 20 as its clock input and 22 Q of 21. Notice that the falling edge of each clock input is the active edge. Thus, 20
toggles at each falling edge of Cp0. 21 toggles only when 20 is logic one. 22 toggles only when both 20 and 21 are
logic HIGH.

Fig. 1 Counting sequence of a 3-bit ripple up counter


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TECH 158 - Digital Electronics (Winter 2023)
Lab #2: Ripple Counters

Design of truncated counters


Modulus of a counter is the number of different binary states included in the counting sequence. Thus, the full
modulus of an n-bit counter is 2n. For instance, we can construct a MOD-16 counter by using 4 flip-flops, the
counting sequence of which includes 16 binary states from 00002 (0) to 11112 (15). On the other hand, a
truncated counter recycles before reaching its terminal count. External gating circuits are required to reset the
counter to its initial value. For instance, if we are to design a MOD-10 counter, we need 4 flip-flops because we
can represent only up to 8 binary states with 3 flip-flops. However, the full modulus of a 4-bit counter is 16. Thus
we need to design a gating circuit, which will reset the counter to 0 as soon as the counter reaches 10. The final
counting sequence should be 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 8 -> 9 -> (10) 0 -> 1 -> 2 …… Note that the output
of 10 appears only very briefly and is not included in the counting sequence.

Pre-lab Assignments:
1. Label each pin of 74LS73 and 74LS93.

Table 1. Pin configuration of 74LS73


Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Function VCC GND Q1’

Table 2. Pin configuration of 74LS93


Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Function

2. Draw the circuit diagram of a 4-bit ripple down-counter constructed with 2 74LS73 IC’s. The counter should be initialized
to zero (00002) at the power up. Assume that we have an external clock source (CLK) and an active-LOW reset signal (POR).
Remember the counter output is read from Q outputs, not Q outputs.

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TECH 158 - Digital Electronics (Winter 2023)
Lab #2: Ripple Counters

3. What change(s) do we have to make to construct an up-counter instead? Note that we are not changing the IC’s.

4. If we replace the J-K flip-flops above with ones that operate at the rising edge of the clock input, what change(s) do we
have to make to retain the up-counting sequence?

5. Shown below is a mod-16 counter constructed with a 74LS93, a 4-bit asynchronous counter. 74LS93 consists of a mod-
2 counter and a mod-8 counter. In case of the mod-2 counter, Ain is the clock input and QA the counter output. In case of
the mod-8 counter, Bin is the clock input and QB, QC, QD are the 3-bit counter output. Both R01 and R02, which are active-
HIGH reset inputs, should be HIGH to reset both counters. A mod-16 counter is constructed by connecting QA (the mod-2
counter output) to Bin (the clock input to the mod-8 counter).
Here, let’s try to design a mod-12 counter by using one 74LS93 and one 74LS00 NAND gate IC. The NAND gate circuit
consists of 3 NAND gates and produces a HIGH output when the counter output reaches 12 (11002). Its output is then
connected to both R01 and R02 to reset the counter back to zero. Let’s assume that the Clear signal shown below becomes
HIGH briefly at the power-up and then remains LOW. When designing a mod-12 counter, the Clear signal should not be
connected directly to R01 and R02. Instead, it should be supplied to the NAND gate circuit so that the counter is reset to
zero when either the Clear is HIGH, typically at the power up, or the counter output reaches 12. Modify the circuit diagram
below to show the circuit diagram of a mod-12 counter.

Name: Student No.:

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