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Retiming: Reduce Clock Period by Shortening Critical Path Reduce The Number of Registers

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24 views17 pages

Retiming: Reduce Clock Period by Shortening Critical Path Reduce The Number of Registers

5

Uploaded by

dowoc61946
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RETIMING

• Retiming is a transformation technique used to change


the locations of delay elements in a circuit without
affecting the input/output characteristics of the circuit.
The main objectives of retiming usually are

• Reduce clock period by shortening critical path

• Reduce the number of registers

1
NO CHANGE IN FUNCTIONAL
BEHAVIOR AFETER RETIMING

w(n)=ay(n-1)+by(n-2) 𝑤! = 𝑎𝑦 𝑛 − 1
y(n)=w(n-1)+x(n) 𝑤" = 𝑏𝑦 𝑛 − 2
=ay(n-2)+by(n-3)+x(n) 𝑦 𝑛 = 𝑤! 𝑛 − 1 + 𝑤" 𝑛 − 1 + 𝑥 𝑛
= ay(n-2)+by(n-3)+x(n)

2
RETIMING FORMULATION
• Retiming value, r

r(N) – the number of delay elements transferred from


the output side to the input side of node N

3D r(N) = 2 D
3D 5D
N N

2D

A retiming solution is r(n) for all N, n= 1 to N.


3
PROPERTIES OF RETIMING
r(U) r(V) retiming
w wr
U V U V

w(e)=weight or delay of edge e wr=w+r(V)-r(U)

• After retiming, all edges must have either zero or positive


delay
𝑤# (𝑒) ≥ 0

• This suggests that a valid retiming solution should have


w 𝑒 + 𝑟 𝑉 − 𝑟(𝑈) ≥ 0
r(V) − 𝑟 𝑈 ≥ −𝑤(𝑒)
r(U)-r(V)≤w(e)

• A valid retiming solution can be found by solving a system of


inequalities derived from the DFG
4
OTHER PROPERTIES OF RETIMING
• The weight of the retiming path p=V0àV1à….Vk is given
by wr(p)=w(p)+r(Vk)-r(V0)
• Retiming does not change the number of delays in a
cycle
• Retiming does not alter the iteration bound in a DFG
• Adding the constant value j to the retiming value of
each node does not alter the number of delays in the
edges of the retiming graph

5
APPLICATION OF A RETIMING SOLUTION
𝑟 1 − 𝑟(3) ≤ 1
𝑟 1 − 𝑟(4) ≤ 2
𝑟 3 − 𝑟(2) ≤ 0
𝑟 4 − 𝑟(2) ≤ 0
𝑟 2 − 𝑟(1) ≤ 1

A retiming solution:
𝑟 1 =0
𝑟 2 =1
𝑟 3 =0
𝑟 4 =0

6
SOLVING SYSTEM OF INEQUALITIES BY
SHORTEST PATH ALGORITHM
• Given M inequalities in N variables where inequality is
of the form 𝑟! − 𝑟" ≤ 𝑘 for integer values of k
• Draw a constraint graph
• Draw the node i for each of the N variables ri, i=1,2,…,N
• Draw the node N+1
• For each inequality 𝑟! −𝑟" ≤ 𝑘, draw the edge jài of length k
• For each node i, i=1,2,…, n, draw the edge N+1ài from the node N+1
to node i with length 0
• Solve using a shortest path algorithm
• The system of inequalities have a solution iff the constraint graph
contains no negative cycles
• If a solution exists, one solution is where ri is the minimum length
path from the node N+1 to node i

7
EXAMPLE
𝑟 1 − 𝑟(2) ≤ 0
𝑟 3 − 𝑟(1) ≤ 5
𝑟 4 − 𝑟(1) ≤ 4
𝑟 4 − 𝑟 3 ≤ −1
𝑟 3 − 𝑟(2) ≤ 2

A solution from finding the


shortest path from node 5 to
each other node:
𝑟 1 =0
𝑟 2 =0
𝑟 3 =0
𝑟 4 = −1
8
GRAPHICAL METHOD OF FINDING RETIMING
SOLUTION
• Cutset retiming rules
• If the graph is divided into 2 disconnected graph G1 and G2 by the cutset
• Adding k delays to each edge from G1 to G2
• Removing k delays from each edge from G2 to G1
k=1

• A feasible cutset
𝑤# 𝑒!," ≥ 0 ⇒ 𝑤 𝑒!," + 𝑘 ≥ 0 − min
"
𝑤(𝑒) ≤ 𝑘 ≤ min
"
𝑤(𝑒)
%! →%# %# →%!
𝑤# 𝑒",! ≥ 0 ⇒ 𝑤 𝑒",! − 𝑘 ≥ 0
9
PIPELING IS A SPECIAL CASE OF RETIMING
Feed-forward Cutset:

k=2

10
RETIMING TOGETHER WITH SLOW-DOWN

Slow-down by N or N-slow – replace each delay by N delays

After cutset retiming:


Assuming tadd=1u.t.
tmultiply=2u.t.
Critical path = 6u.t.
Sample period reduced
from 105u.t. to 12u.t.

11
RETIMING TO REDUCE CLOCK PERIOD
• Retiming can be performed to achieve a particular clock
period i.e. to ensure the critical path is not longer than c
• To find a retiming solution, we need to compute two tables
• W[U,V] = number of registers on the minimum weight path from
UàV
• D[U,V] = maximum delay over all paths with W[U,V] registers
• Knowing W[U,V], the system of inequalities meeting the
path constraint 𝑟 𝑈 − 𝑟 𝑉 ≤ 𝑊 𝑈, 𝑉 can be derived
• Knowing D[U,V], more inequalities can be added by
considering the critical path constraint
• Change 𝑤! (𝑈, 𝑉) ≥ 0 to 𝑤! (𝑈, 𝑉) ≥ 1 to ensure there is at least on
register is added to reduce those paths with D[U,V]>c
• 𝑤 𝑈, 𝑉 + 𝑟 𝑉 − 𝑟 𝑈 ≥ 1
• 𝑟 𝑈 − 𝑟 𝑉 ≤ 𝑤 𝑈, 𝑉 − 1
12
EXAMPLE

𝑟 1 − 𝑟(2) ≤ 0
𝑟 1 − 𝑟(3) ≤ 1
𝑟 2 − 𝑟(3) ≤ 1
𝑟 1 − 𝑟(4) ≤ 2 𝑟 2 − 𝑟(4) ≤ 2
𝑟 2 − 𝑟(1) ≤ 1
𝑟 3 − 𝑟(1) ≤ 0
𝑟 3 − 𝑟(2) ≤ 0
𝑟 3 − 𝑟(4) ≤ 2
𝑟 4 − 𝑟(2) ≤ 0 𝑟 4 − 𝑟(1) ≤ 0
𝑟 4 − 𝑟(3) ≤ 1

13
SOLVING THE SYSTEM OF INEQUALITIES

• Solution is
r(1)=r(2)=r(3)=r(4)=0

• No change to the DFG as the clock period required has


already been met
14
REPEAT THE EXAMPLE WITH c=2
𝑟 1 − 𝑟(2) ≤ 0
𝑟 1 − 𝑟(3) ≤ 1
𝑟 1 − 𝑟(3) ≤ 0
𝑟 1 − 𝑟(4) ≤ 2
𝑟 1 − 𝑟(4) ≤ 1
𝑟 2 − 𝑟(1) ≤ 1
𝑟 2 − 𝑟(3) ≤ 1
𝑟 3 − 𝑟(2) ≤ 0
𝑟 2 − 𝑟(4) ≤ 2
𝑟 4 − 𝑟(2) ≤ 0
𝑟 3 − 𝑟(1) ≤ 0
𝑟 3 − 𝑟 2 ≤ −1 The solution is
r(1)=-1, r(2)=0, r(3)=-1, r(4)=-1
𝑟 3 − 𝑟(4) ≤ 2
𝑟 4 − 𝑟(1) ≤ 0
𝑟 4 − 𝑟 2 ≤ −1
𝑟 4 − 𝑟(3) ≤ 1

15
RETIMING FOR REGISTER MINIMIZATION
D

D
N N
D

• Register sharing • Register reduction through


• When a node has multiple node delay transfer from
fan-out with different multiple input edges to
number of delays, the output edges (r(N)<0)
registers can be shared so
that only the branch with • Should be done only when
the maximum number of clock cycle constraint is
delays will be needed not violated

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