A Tod Converters
A Tod Converters
STUART BALL
f e a t u r e
Analog-to-Digital
Converters
The usual method of bringing analog inputs into a microprocessor is to use an
analog-to-digital converter (ADC). Here are some tips for selecting such a part and
calibrating it to fit your needs.
A
n analog-to-digital converter (ADC) accepts 5V/256 = 0.0195V or 19.5mV
an analog input—a voltage or a current—
and converts it to a digital value that can be Our 8-bit converter represents the analog input as a digital
read by a microprocessor. Figure 1 shows a word. The most significant bit of this word indicates
simple voltage-input ADC. This hypotheti- whether the input voltage is greater than half the reference
cal part has two inputs: a reference and the (2.5V, with a 5V reference). Each succeeding bit represents
signal to be measured. It has one output, an 8-bit digital half the range of the previous bit.
word that represents the input value. Table 1 illustrates this point. Adding the voltages corre-
The reference voltage is the maximum value that the sponding to each set bit in 0010 1100, we get:
ADC can convert. Our example 8-bit ADC can convert values
from 0V to the reference voltage. This voltage range is divid- .625 + .156 + .078 = .859 volts
ed into 256 values, or steps. The size of the step is given by:
The resolution of an ADC is determined by the refer-
Vref/256 ence input and by the word width. The resolution defines
the smallest voltage change that can be measured by the
where Vref is the reference voltage. The step size of the con- ADC. As mentioned earlier, the resolution is the same as the
verter defines the converter’s resolution. For a 5V refer- smallest step size, and can be calculated by dividing the ref-
ence, the step size is: erence voltage by the number of possible conversion values.
For the example we’ve been using tors required, they tend to be power Successive approximation converter
so far, the resolution is 19.5mV. This hogs, drawing significant current. A A successive approximation convert-
means that any input voltage below 10-bit flash ADC may consume half an er uses a comparator and counting
19.5mV will result in an output of 0. amp. logic to perform a conversion. The
Input voltages between 19.5mV and A variation on the flash converter is first step in the conversion is to see if
39mV will result in an output of 1. the half-flash, which uses an internal the input is greater than half the ref-
Between 39mV and 58.6mV, the out- digital-to-analog converter (DAC) and erence voltage. If it is, the most sig-
put will be 2. subtraction to reduce the number of nificant bit (MSB) of the output is
Resolution can be improved by internal comparators. Half-flash con- set. This value is then subtracted
reducing the reference input. verters are slower than true flash con- from the input, and the result is
Changing that from 5V to 2.5V gives a verters but faster than other types of checked for one quarter of the refer-
resolution of 2.5/256, or 9.7mV. ADCs. We’ll lump them into the flash ence voltage. This process continues
However, the maximum voltage that converter category. until all the output bits have been set
can be measured is now 2.5V instead
of 5V.
The only way to increase resolution
FIGURE 1 Simple ADC
without reducing the range is to use
an ADC with more bits. A 10-bit ADC
has 210, or 1,024 possible output Input
codes. So the resolution is 5V/1,024,
or 4.88mV; a 12-bit ADC has a 1.22mV Output Bits (8)
resolution for this same reference.
Reference Voltage (Vref)
Types of ADCs
ADCs come in various speeds, use dif-
ferent interfaces, and provide differ- 1
ing degrees of accuracy. The most
common types of ADCs are flash, suc-
.8
Reference Voltage (Vref)
Flash ADC .6
The flash ADC is the fastest type avail-
able. A flash ADC uses comparators, .4
one per voltage step, and a string of
resistors. A 4-bit ADC will have 16 com- .2
parators, an 8-bit ADC will have 256
comparators. All of the comparator
outputs connect to a block of logic 32 64 96 128 160 192 224 255
that determines the output based on Output Value (Decimal)
which comparators are low and which
are high.
The conversion speed of the flash
TABLE 1 Example conversion, on an 8-bit ADC
ADC is the sum of the comparator
delays and the logic delay (the logic
Bit: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RUPERT ADLEY
or reset. A successive approximation sampling the input, the conversion Sample and hold
ADC takes as many clock cycles as takes many clock cycles. For a given ADC operation is straightforward
there are output bits to perform a clock rate, the sigma-delta converter is when a DC signal is being converted.
conversion. slower than other converter types. Or, But if the input signal varies by more
to put it another way, for a given con- than one least significant bit (LSB)
Sigma-delta version rate, the sigma-delta converter during the conversion time, the ADC
A sigma-delta ADC uses a 1-bit DAC, fil- requires a faster clock. will produce an incorrect (or at least
tering, and oversampling to achieve Another disadvantage of the sigma- inaccurate) result. One way to
very accurate conversions. The conver- delta converter is the complexity of reduce these errors is to place a low-
sion accuracy is controlled by the input the digital filter that converts the duty pass filter ahead of the ADC. The fil-
reference and the input clock rate. cycle information to a digital output ter parameters are selected to ensure
The primary advantage of a sigma- word. The sigma-delta converter has that the ADC input does not change
delta converter is high resolution. The become more commonly available by more than one LSB within a con-
flash and successive approximation with the ability to add a digital filter or version cycle.
ADCs use a resistor ladder or resistor DSP to the IC die. Another way to handle changing
string. The problem with these is that inputs is to add a sample-and-hold
the accuracy of the resistors directly ADC comparison (S/H) circuit ahead of the ADC.
affects the accuracy of the conversion Figure 2 shows the range of resolu- Figure 3 shows how a sample-and-hold
result. Although modern ADCs use tions available for sigma-delta, succes- circuit works. The S/H circuit has an
very precise, laser-trimmed resistor sive approximation, and flash convert- analog (solid state) switch with a con-
networks, some inaccuracies still per- ers. The maximum conversion speed trol input. When the switch is closed,
sist in the resistor ladders. The sigma- for each type is shown as well. As you the input signal is connected to the
delta converter does not have a resis- can see, the speed of available sigma- hold capacitor and the output of the
tor ladder but instead takes a number delta ADCs reaches into the range of buffer follows the input. When the
of samples to converge on a result. the successive approximation ADCs, switch is open, the input is disconnect-
The primary disadvantage of the but is not as fast as even the slowest ed from the capacitor.
sigma-delta converter is speed. flash ADCs. What the tables do not The figure shows the waveform for
Because the converter works by over- show is the tradeoff between speed S/H operation. A slowly rising signal is
In a perfect world, the hold capacitor would have no leakage and the
buffer amplifier would have infinite input impedance, Since some impedance is in series
so the output would remain stable forever. with the hold capacitor when sam-
pling, the effect is the same as a low-
pass RC filter. This limits the maxi-
mum frequency that the S/H can
FIGURE 3 Sample and hold acquire. This is called the full power
bandwidth, and is specified in kilohertz
Buffer or megahertz.
As mentioned, the electronic
Input Signal To ADC switch is imperfect and some of the
input signal appears at the output,
Sample/Hold Control
Hold Capacitor even in hold mode. This is called
feedthrough, and is typically specified in
decibels.
The output offset is the voltage dif-
ference between the input and the
output. S/H circuit datasheets typical-
Input Signal ly show a hold mode offset and sample
mode offset in millivolts.
Software
Output Voltage An ADC system that uses a S/H may
have to accommodate the hardware
quirks. In some systems, the software
Sample/Hold Control directly controls the S/H control
(0 = Sample, 1 = Hold) input with a port or register output
bit. Typically, the S/H is placed into
sample mode, and the software must
ensure that the acquisition time
connected to the S/H input. While The ability of an S/H circuit to requirement is met. In some systems,
the control signal is low (sample), the maintain the output in hold mode is this can be accomplished simply by
output follows the input. When the dependent on the quality of the hold leaving the S/H in sample mode until
control signal goes high (hold), dis- capacitor, the characteristics of the a conversion is needed.
connecting the hold capacitor from buffer amplifier (primarily input After the S/H is placed into hold
the input, the output stays at the value impedance), and the quality of the sam- mode, another bit (or a write to an
the input had when the S/H switched ple/hold switch (real electronic switch- address or some other operation)
to hold mode. When the switch closes es have some leakage when open). The starts the ADC. After the conversion is
again, the capacitor charges quickly amount of drift exhibited by the output complete, the software reads the
and the output again follows the when in hold mode is called the droop result. However, a problem may occur
input. Typically, the S/H will be rate, and is specified in millivolts per sec- if any one interrupt (or a worst-case
switched to hold mode just before the ond, millivolts per microsecond, or stackup of interrupts) causes the out-
ADC conversion starts, and switched microvolts per microsecond. put of the S/H circuit to droop by
back to sample mode after the conver- A real S/H circuit also has finite more than one LSB. If this could hap-
sion is complete. input impedance, because the elec- pen, the software may need to disable
In a perfect world, the hold capaci- tronic switch isn’t perfect. This means interrupts before switching the S/H to
tor would have no leakage and the that in sample mode, the hold capaci- hold mode and re-enable them after
buffer amplifier would have infinite tor is charged through some resis- starting the conversion. This ensures
input impedance, so the output would tance. This limits the speed with which that the ADC will complete the con-
remain stable forever. In the real the S/H can acquire an input. The version before the S/H droop occurs.
world, though, the hold capacitor will time that the S/H must remain in sam- Software must also accommodate
leak and the buffer amplifier input ple mode in order to acquire a full- the charge time of the S/H. When the
impedance is finite, so the output level scale input is called the acquisition time, electronic switch closes and connects
will slowly drift down toward ground and is specified in nanoseconds or the input signal to the S/H capacitor,
as the capacitor discharges. microseconds. it takes a finite amount of time for the
In the real world, though, the hold capacitor will leak and the buffer
amplifier input impedance is finite, so the output level will slowly However, the result is dependent
drift down toward ground as the capacitor discharges. on the value of the 5V supply. If the
supply voltage is high by 1%, it has a
value of 5.05V. Now the value of the
A/D conversion will be:
FIGURE 4 Reference voltage variation
(3.2V x 256)/5.05V = 16210 = A216
This brings up an issue that affects all ADC designs: the accuracy of
the reference. A typical ADC reference might be nominally 2.5V, rected values were exactly right or off
but can vary between 2.47V and 2.53V. by just one. This degree of correction
is significantly better than the origi-
nal variation (10 counts) for a 2V
ADC. This reference can be very pre- division process consists of a series of input, and is all that many applica-
cise (and very expensive) because shift-and-add or shift-and-subtract tions require. If your application
only a few are needed for the produc- operations. can’t stand even this error, then you
tion line. The 2.47V example could be cor- may really need a better reference or
In the 2.47V example we’ve been rected by multiplying the ADC value you may have to resort to a manual
looking at, a precise voltage of 2V by .988. The same thing can be adjustment.
might be input to the ADC. When the achieved by subtracting 1/128 then This calibration technique can also
software reads the ADC, it knows the 1/256 then 1/512 of the initial value. be used to compensate for other sys-
correct value should be 819; the cali- Using the original 2V input example, tem inaccuracies, such as resistor tol-
bration constant is given by 829/819, and doing this with integer math, we erance stackup. If whatever you are
or 1.012. Similarly, the calibration con- get the following: measuring consists of a voltage input,
stant for the 2.53V reference is you can apply the precision voltage to
809/819, or 0.988. 829 – 829/128 – 829/156 – 829/512 that input and do one calibration to
This would seem to imply the need = 829 – 6 – 3 – 1 compensate for reference variations in
for floating-point math to correct the = 819 the ADC and resistor tolerance effects
ADC value. If you are using a proces- in the input conditioning.
sor capable of floating-point, this is an This result corrects the ADC read-
acceptable approach. On simpler ing to 819, which is the ideal value if Calculating and using the calibration
processors, though, you may not have the reference were the nominal 2.5V. value
the execution time or the code space Similarly, values read with the 2.53V The calibration value can be calcu-
available to implement floating-point reference can be corrected by adding lated by reading a known reference
calculations. 1/128 plus 1/256. and then finding which correction
One way to handle the ADC cor- Note that you do not need to factors (binary submultiples) to use.
rection is to use a lookup table. This apply the precise calibration voltage For the example given, the differ-
has the drawbacks of requiring suffi- to the input you are using. You can ence between the ideal and the
cient nonvolatile storage to maintain a use any spare ADC input, so long as worst-case ADC value will never be
lookup value for every possible ADC that ADC uses the reference you more than 1.2%, so there is no point
value—a 1,024-word table for a 10-bit want to calibrate. in starting with one-half or one-
ADC. You need to be sure that your ref- fourth of the original value. The
A voltage reference is fairly close to erence is sufficiently stable over your only values tested and used are
its nominal value—otherwise it would expected operating temperature 1/128, 1/256, and 1/512. You want
not be useful as a reference. Assuming range or the results will only be good to start with something close to the
that your reference is sufficiently sta- near the temperature during calibra- value you expect to see.
ble over your operating temperature, tion. If the temperature stability of Finding the correction factors is
the ADC error will be a constant per- the reference is not good enough, easy with a calculator, but if you have
centage of the value you read from the you will have to get a better reference to calculate it on the fixed-point
ADC. Since the ADC has a finite reso- or break your operating temperature processor you will be using in your
lution, there is no point in attempting range into multiple segments and application, you need an integer-
to correct the ADC error with any pre- use one calibration value for each based approach. Figure 5 shows in
cision greater than 1 LSB. segment. Of course, this implies that flowchart form the algorithm used in
Knowing this, you can simplify the you must have a thermistor or other this example to calculate and use the
ADC correction process. Instead of a means of measuring the tempera- calibration constant. In this method, a
lookup table, you store a value that ture, too. single byte (or word) is used to store
tells the software what (binary) per- This approach does result in the calibration constant. Bit 7 indi-
centage to add or subtract from the rounding errors caused by the trun- cates whether the reference voltage is
ADC reading to correct the error. You cation that occurs when you shift the low (calibration values need to be sub-
can add or subtract 1/8, 1/16, or result. I made a spreadsheet using tracted) or high (calibration values
1/24, all the way down to 1 LSB of the 2.47V example, and in all cases added). Bits 0, 1, and 2 indicate
accuracy. You only need to store a sin- the corrected value was within two whether the 1/128, 1/256, and 1/512
gle calibration constant, and your counts of the ideal value. Most cor- factors are used.
No
(VREF High)
ADC Value > Ideal Value? Corrected ADC = ADC Value
Yes No
(VREF Low) (VREF High)
Bit 7 of Calib Const Set?
Set Temp = 0
Set Calib Const = 80H Set Temp = 0
Yes
(MSB indicates calibration Set Calib Const = 0H
(VREF Low)
values are to be subtracted (Calibration values are
from ADC values) to be added to ADC values)