BSC EEE BEE 4102 Control Systems II Lecture 5 Digital Controllers 2024
BSC EEE BEE 4102 Control Systems II Lecture 5 Digital Controllers 2024
Fig. 4.2.1 Feed Back Control System Block Diagram with Options for Gain, Lead, Lag, PI, PD and PID
Controllers.
Eng. Prof. Mwangi Mbuthia – August - 2024
BEE 4102 Control Systems II
4 Digital Controllers – Analogue Controller Emulation
4.2.1 Discrete Time Signal
An ideal sample f *(t) of a continuous signal f(t) is a series of zero width impulses spaced at
sampling time T seconds.
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(a) Discrete Time Signal (b) Continous Time Signal
(a) Continuous Signal (b) Sampled Signal
Suppose u(t) is the input signal to the zero-order hold. The output f(t) of the zero-order hold operation can be
represented as;
Here, T is the sampling period, and k is an integer representing the discrete sampling instants. Taking the Laplace
Transform;
Continuous time controllers are analysed, simulated and designed using Laplace
transformations as described in Chapter 2.
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Eng. Prof. Mwangi Mbuthia – August - 2024
BEE 4102 Control Systems II
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Eng. Prof. Mwangi Mbuthia – August - 2024
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BEE 4102 Control Systems II
4 Digital Controllers – Analogue Controller Emulation
4.2.3 z-transform properties
(a) Linearity
𝑓 0 = lim 𝐹(𝑧)
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