Computer Architecture Lec 6

Mapping Function

Because there are fewer cache lines than main memory blocks, an algorithm is
needed for mapping main memory blocks into cache lines. Further, a means is
needed for determining which main memory block currently occupies a cache line.
The choice of the mapping function dictates how the cache is organized. Three
techniques can be used: direct, associative, and set associative

Example
For all three cases, the example includes the following elements:
• The cache can hold 64 Kbytes.
• Data are transferred between main memory and the cache in blocks of 4 bytes
each.
This means that the cache is organized as 16K 214 lines of 4 bytes each.
• The main memory consists of 16 Mbytes, with each byte directly addressable by a
24-bit address (224 16M).Thus, for mapping purposes, we can consider main memory
to consist of 4M blocks of 4 bytes each.

DIRECT MAPPING The simplest technique, known as direct mapping, maps each
block of main memory into only one possible cache line. The mapping is expressed
as:
i = j modulo m
where
i cache line number
j main memory block number
m number of lines in the cache

Figure 6.1a shows the mapping for the first m blocks of main memory. Each block of
main memory maps into one unique line of the cache. The next m blocks of main
memory map into the cache in the same fashion; that is, block Bm of main memory
maps into line L0 of cache, block Bm+1 maps into line L1, and so on.
The mapping function is easily implemented using the main memory address.
Figure 6.2 illustrates the general mechanism. For purposes of cache access, each
main memory address can be viewed as consisting of three fields. The least
significant w bits identify a unique word or byte within a block of main memory; in
most contemporary machines, the address is at the byte level. The remaining s bits
specify one of the 2s blocks of main memory. The cache logic interprets these s bits

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as a tag of s- r bits (most significant portion) and a line field of r bits. This latter field
identifies one of the m=2r lines of the cache. To summarize,
• Address length (s+w) bits
• Number of addressable units= 2 s+w words or bytes
• Block size= line size= 2w words or bytes
2𝑠+𝑤
• Number of blocks in main memory= 𝑤 = 2s
2
r
• Number of lines in cache =m= 2
• Size of cache 2r+w words or bytes
• Size of tag = (s-r) bits

Figure 6.1 Mapping form main memory to cache: Direct and associative

The effect of this mapping is that blocks of main memory are assigned to lines of the
cache as follows:

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Thus, the use of a portion of the address as a line number provides a unique
mapping of each block of main memory into the cache.
When a block is actually read into its assigned line, it is necessary to tag the data to
distinguish it from other blocks that can fit into that line. The most significants r bits
serve this purpose.

Figure 6.2 Direct-mapping cache organization

Example a: Figure 6.3 shows our example system using direct mapping In the
example, m = 16K = 214. The mapping becomes

Cache Line Starting Memory Address of Block

0 00 00 00, 01 00 00, FF 00 00
1 00 00 04, 01 00 04, FF 00 04
:
214 – 1 00 FF FC, 01 FF FC, FF FF FC

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Note that no two blocks that map into the same line number have the same tag
number. Thus, blocks with starting addresses 000000, 010000, FF0000 have tag
numbers 00, 01, FF, respectively.
A read operation works as follows. The cache system is presented with a 24-bit
address. The 14-bit line number is used as an index into the cache to access a
particular line. If the 8-bit tag number matches the tag number currently stored in
that line, then the 2-bit word number is used to select one of the 4 bytes in that line.
Otherwise, the 22-bit tag-plus-line field is used to fetch a block from main memory.
The actual address that is used for the fetch is the 22-bit tag-plus-line concatenated
with two 0 bits, so that 4 bytes are fetched starting on a block boundary.

16 M byte main memory

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 Figure 6.3 Direct Mapping Example

The direct mapping technique is simple and inexpensive to implement. Its main
disadvantage is that there is a fixed cache location for any given block. Thus, if a
program happens to reference words repeatedly from two different blocks that map
into the same line, then the blocks will be continually swapped in the cache, and the
hit ratio will be low (a phenomenon known as thrashing).
One approach to lower the miss penalty is to remember what was discarded in case
it is needed again. Since the discarded data has already been fetched, it can be used
again at a small cost. Such recycling is possible using a victim cache. Victim cache was
originally proposed as an approach to reduce the conflict misses of direct mapped
caches without affecting its fast access time. Victim cache is a fully associative cache,
whose size is typically 4 to 16 cache lines, residing between a direct mapped L1
cache and the next level of memory.

Figure 6.4 fully associative cache organization

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ASSOCIATIVE MAPPING Associative mapping overcomes the disadvantage of direct
mapping by permitting each main memory block to be loaded into any line of the
cache (Figure 6.1b). In this case, the cache control logic interprets a memory address
simply as a Tag and a Word field. The Tag field uniquely identifies a block of main
memory. To determine whether a block is in the cache, the cache control logic must
simultaneously examine every line’s tag for a match. Figure 6.4 illustrates the logic.
Note that no field in the address corresponds to the line number, so that the number
of lines in the cache is not determined by the address format. To summarize,
• Address length (s+w) bits
• Number of addressable units 2s+w words or bytes
• Block size line size 2w words or bytes
2s+w
• Number of blocks in main memory = =2s
2𝑤
• Number of lines in cache= undetermined
• Size of tag = s bits

Example b Figure 6.5 shows our example using associative mapping. A main memory
address consists of a 22-bit tag and a 2-bit byte number. The 22-bit tag must be
stored with the 32-bit block of data for each line in the cache. Note that it is the
leftmost (most significant) 22 bits of the address that form the tag. Thus, the 24-bit
hexadecimal address 16339C has the 22-bit tag 058CE7.This is easily seen in binary
notation:

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 Figure 6.5 associative mapping

With associative mapping, there is flexibility as to which block to replace when a new
block is read into the cache. Replacement algorithms are designed to maximize the
hit ratio. The principal disadvantage of associative mapping is the complex circuitry
required to examine the tags of all cache lines in parallel.

SET-ASSOCIATIVE MAPPING Set-associative mapping is a compromise that exhibits

the strengths of both the direct and associative approaches while reducing their
disadvantages.
In this case, the cache consists of a number sets, each of which consists of a number
of lines. The relationships are

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m=v*k
i = j modulo v

where
i cache set number
j main memory block number
m number of lines in the cache
v number of sets
k number of lines in each set

This is referred to as k-way set-associative mapping. With set-associative mapping,

block Bj can be mapped into any of the lines of set j. Figure 6.6a illustrates this
mapping for the first blocks of main memory. As with associative mapping, each
word maps into multiple cache lines. For set-associative mapping, each word maps
into all the cache lines in a specific set, so that main memory block B0 maps into set
0, and so on .Thus, the set-associative cache can be physically implemented as
associative caches. It is also possible to implement the set-associative cache as k
direct mapping caches, as shown in Figure 6.6b. Each direct-mapped cache is
referred to as a way, consisting of lines. The first lines of main memory are direct
mapped into the lines of each way; the next group of lines of main memory are
similarly mapped, and so on. The direct-mapped implementation is typically used for
small degrees of associativity (small values of k) while the associative-mapped
implementation is typically used for higher degrees of associativity.
For set-associative mapping, the cache control logic interprets a memory address as
three fields: Tag, Set, and Word. The d set bits specify one of v= 2d sets. The s bits of
the Tag and Set fields specify one of the 2s blocks of main memory.
Figure 6.7 illustrates the cache control logic. With fully associative mapping, the tag
in a memory address is quite large and must be compared to the tag of every line in
the cache. With k-way set-associative mapping, the tag in a memory address is much
smaller and is only compared to the k tags within a single set.
To summarize,
• Address length (s+ w) bits
• Number of addressable units 2s+w words or bytes
• Block size =line size= 2w words or bytes
• Number of blocks in main memory=2s
• Number of lines in set k
• Number of sets = n = 2d
• Number of lines in cache m =kv= k* 2d
• Size of cache k *2d-w words or bytes
• Size of tag = (s-d) bits

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Figure 6.6 Mapping from Main Memory to Cache: k-way Set Associative

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Figure 6.7 k-way set associative cache organization

Example c Figure 6.8 shows our example using set-associative mapping with two
lines in each set, referred to as two-way set-associative. The 13-bit set number
identifies a unique set of two lines within the cache. It also gives the number of the
block in main memory, This determines the mapping of blocks into lines. Thus, blocks
000000, 008000… FF8000 of main memory map into cache set 0. Any of those blocks
can be loaded into either of the two lines in the set. Note that no two blocks that
map into the same cache set have the same tag number. For a read operation, the
13-bit set number is used to determine which set of two lines is to be examined.
Both lines in the set are examined for a match with the tag number of the address to
be accessed.

In the extreme case of m, k 1, the set-associative technique reduces to direct

mapping, and for 1,k m,it reduces to associative mapping. The use of two lines per
set (n = m/2, k = 2) is the most common set-associative organization.

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Figure 6.8 two way set associative mapping example

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