INEL 4202 – 2S2021 8/12/2024
INEL 4202 – Electronics II 741 Op-Amp
This course
teaches
frequency
analysis
techniques of
BJT/CMOS
based op-amp
circuits with and
without
feedback.
1
INEL 4202 – 2S2021 8/12/2024
INEL 4201 – Electronics I
• BJTs (Chp. #6) • MOSFETs (Chp. #5)
₋ characteristic curves ₋ characteristic curves
₋ large signal behavior (DC) ₋ large signal behavior (DC)
₋ small signal behavior (AC) ₋ small signal behavior (AC)
• Small Signal Analysis (equivalent impedances)
• Single Stage Amplifier
₋ Common Emitter / Common Source
₋ Common Collector / Common Drain
₋ Common Base / Common Gate
… a strong background in AC analysis is required!
2
Electronics I
3
Electronics I
BJT Mathematical Model → Active 8/12/2024
• iC = f(vBE) Current & Parameters
𝒊𝑪 = 𝜷 ∙ 𝒊𝑪
𝜷+𝟏 𝒊𝑪
𝒊𝑬 = 𝒊𝑩 + 𝒊𝑪 = 𝒊 =
𝜷 𝑪 𝜶
𝒗𝑪𝑬
𝒊𝑪 ∝ 𝒆𝒗𝑩𝑬Τ𝑽𝑻 𝒊𝑪 ∝ IS - Saturation Current [10-12 - 10-18] A
𝑽𝑨
• iC = f(vCE) 𝑨𝑬 𝒒𝑫𝒏 𝒏𝒊
𝑰𝑺 =
𝑵𝑨 𝓦
𝜷 - Current Gain [50 - 200] A/A
𝒊𝑪
Collector Current 𝜷𝒇𝒐𝒓𝒄𝒆𝒅 = |𝒔𝒂𝒕 ≤ 𝜷
𝒊𝑩
𝒗𝑪𝑬
𝒊𝑪 = 𝑰𝑺 𝒆𝒗𝑩𝑬Τ𝑽𝑻 𝟏 + ∝ - Constant 𝜷
𝑽𝑨 𝜶=
≈ 𝑰𝑺 𝒆𝒗𝑩𝑬Τ𝑽𝑻 𝜷+𝟏
VA - Early Voltage [10 - 100] V
4
Electronics I
BJT Small Signal Circuit 8/12/2024
• Input Impedance (r𝛑)
• Trans-conductance (gm)
• Output Impedance (ro)
𝝏𝑰𝑪 𝑰𝑪
𝒈𝒎 = =
𝝏𝑽𝑩𝑬 𝑽𝑻
𝝏𝑽𝑩𝑬 𝜷
𝑹𝒊𝒏 = = = 𝒓𝝅
𝝏𝑰𝑩 𝒈𝒎
𝝏𝑽𝑪𝑬 𝑽𝑨
𝑹𝒐𝒖𝒕 = = = 𝒓𝒐
𝝏𝑰𝑪 𝑰𝑪
Small Signal Circuit
5
Electronics I
nMOS Strong Inversion → Saturation 8/12/2024
• vGS > vtn Over-drive Voltage 𝑽𝒐𝒗 = 𝑽𝑮𝑺 − 𝑽𝒕𝒏
iD ≈ f(vGS2)
• vDS > vGS - vtn
• iG = 0
𝑲𝒏 Channel Length Modulation
Parameter [1/V]
1 ′𝑊
𝐼𝐷 = 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡𝑛 2 1 + 𝜆𝑉𝐷𝑆
2 𝐿
1 ′𝑊
≈ 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡𝑛 2
2 𝐿
nMOS Transconductance Parameter [A/V2]
𝒌𝒏 ′ = 𝝁𝒏 𝑪𝒐𝒙
6
Electronics I
MOSFETs Small Signal Circuit 8/12/2024
• Input Impedance (∞)
• Trans-conductance (gm)
• Output Impedance (ro)
𝑹𝒊𝒏 = ∞
𝒅𝑰𝑫
𝒈𝒎 = = 𝟐𝑰𝑫 𝑲𝒏
𝒅𝑽𝑮𝑺
𝒅𝑽𝑫𝑺 𝟏
𝑹𝒐𝒖𝒕 = = = 𝒓𝟎
Small Signal Circuit 𝒅𝑰𝑫 𝝀𝑰𝑫
7
Electronics I
Large-Signal vs Small Signal Behavior 8/12/2024
• Bias current is stablished through VBB and supplied by Vcc
• AC signal is coupled through the capacitor and superimposed to the DC signal
bias bias
AC & DC analysis can
be performed via
superposition!
• Large-Signal (DC) – stablishes the DC operating
point of the circuit
• Small-Signal (AC) – determines de circuit
behavior around the DC operating point
8
Electronics I
Large Signal & Small Signal Analysis 8/12/2024
• npn • pnp Vout saturation active off
off active saturation
Vdd
0.3V
pnp
npn
0.3V
0.7V 0.7V Vin
Vdd
Identical small signal behavior!
9
Electronics I
Basic MOSFETs Amplifier Configuration 8/12/2024
• Common Drain
• Common Source
• Common Gate
10
Electronics I
Small Signal Analysis 8/12/2024
1) Determine the transistor bias current (DC Analysis)
2) Determine the small-signal parameters
3) Draw the small-signal equivalent circuit
• All DC sources off!
• Low freq. cap shorted!
4) Replace transistor with small-signal circuit
5) Calculate the desired specifications
11
Electronics I
Common Source Amplifier 8/12/2024
𝒗𝟎
For the given circuit find the expression for: , 𝑹𝒊𝒏 , and 𝑹𝒐
𝒗𝒔𝒊𝒈
12
Electronics I
Common Source Amplifier 8/12/2024
Small Signal Circuit
Voltages and currents of the small signal
circuit represent signal changes!
13
Electronics I
Common Source Amplifier 8/12/2024
𝑹𝒊𝒏 = 𝑹𝑮 ԡ𝑹𝒈𝒂𝒕𝒆 = 𝑹𝑮
Gate terminal presents a high
impedance node (∞)
𝑹𝟎 = 𝑹𝑫 ԡ𝑹𝒅𝒓𝒂𝒊𝒏 = 𝑹𝑫 ԡ𝒓𝟎
Drain terminal represents a high
impedance node (𝒓𝟎 – no degeneration)
Attenuation due to RG
𝑽𝟎 𝑽𝒊𝒏 𝑽𝟎 𝑹𝑮
𝑨𝒗 = = = −𝒈𝒎 𝑹𝑫 ԡ𝑹𝑳 ԡ𝒓𝟎
𝒗𝒔𝒊𝒈 𝒗𝒔𝒊𝒈 𝑽𝒊𝒏 𝑹𝒔𝒊𝒈 + 𝑹𝑮
CS Stage – high negative gain
14
Electronics I
Common Drain Amplifier 8/12/2024
Small Signal Circuit
15
Electronics I
Common Drain Amplifier 8/12/2024
𝑽𝟎 𝑽𝒊𝒏 𝑽𝟎 Assume r0=∞
𝑨𝒗 = =
𝒗𝒔𝒊𝒈 𝒗𝒔𝒊𝒈 𝑽𝒊𝒏
Attenuation due to RG
𝑹𝑮 𝒈𝒎 𝑹𝑳
𝑨𝒗 =
𝑹𝒔𝒊𝒈 + 𝑹𝑮 𝟏 + 𝒈𝒎 𝑹𝑳
CD Stage – gain ~ 1V/V
𝟏 𝟏
𝑹𝟎 = ብ 𝑹𝑳 ԡ𝒓𝟎 ≈ 𝑹𝒊𝒏 = 𝑹𝑮 ԡ𝑹𝒈𝒂𝒕𝒆 = 𝑹𝑮
𝒈𝒎 𝒈𝒎
Source terminal represents Gate terminal presents a
a low impedance node ! high impedance node (∞)
Zout = output impedance (takes in account everything connected to the output node) 16
Electronics I ZL = load impedance (takes in account the load only)
BJT – Single Stage Amplifiers 8/12/2024
Common-Emmitter Common-Collector Common-Base
Voltage Gain
𝑔𝑚 𝑔𝑚
𝑣𝑜 ≅− ∙Z ≅+ ∙𝑍 = +𝑔𝑚 ∙ Z𝑜ut
𝐴𝑣 = 1 + 𝑔𝑚 𝑍𝑒 𝑜ut 1 + 𝑔𝑚 𝑍L L
𝑣𝑖
Input Resistance 1
= 𝑟𝜋 (1 + 𝑔𝑚 𝑍𝑒 ) = 𝑟𝜋 (1 + 𝑔𝑚 𝑍𝑒 ) ≅
𝑅𝑖 𝑔𝑚
Output Resistance 1 𝑍𝑏
= 𝑟𝑜 (1 + 𝑔𝑚 𝑍𝑒 ) ≅ + = 𝑟𝑜 1 + 𝑔𝑚 (𝑍𝑖 //𝑍𝑒 )
𝑅𝑜 𝑔𝑚 𝛽𝑜 + 1
Zout = output impedance (takes in account everything connected to the output node) 17
Electronics I ZL = load impedance (takes in account the load only)
MOS – Single Stage Amplifiers 8/12/2024
Common-Source Common-Drain Common-Gate
Voltage Gain
𝒈𝒎 𝒈𝒎
𝒗𝒐 =− ∙𝒁 =+ ∙𝒁 = +𝒈𝒎 𝒁𝒐𝒖𝒕
𝑨𝒗 = 𝟏 + 𝒈𝒎 𝒁𝒔 𝒐𝒖𝒕 𝟏 + 𝒈𝒎 𝒁𝑳 𝑳
𝒗𝒊
Input Resistance 𝟏
=∞ =∞ =
𝑹𝒊 𝒈𝒎
Output Resistance 𝟏
= 𝒓𝟎 (𝟏 + 𝒈𝒎 𝒁𝒔 ) = = 𝒓𝟎 𝟏 + 𝒈𝒎 (𝒁𝒊 //𝒁𝒔 )
𝑹𝒐 𝒈𝒎
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Electronics I
Terminal Impedances 8/12/2024
BJT Equivalent Impedance MOSFET Equivalent Impedance
Base 𝑟𝜋 1 + 𝑔𝑚 ∙ 𝑍𝑒𝑚𝑖𝑡𝑡𝑒𝑟 Gate ∞
Collector 𝑟0 1 + 𝑔𝑚 ∙ 𝑍𝑒𝑚𝑖𝑡𝑡𝑒𝑟 Drain 𝑟0 1 + 𝑔𝑚 ∙ 𝑍𝑠𝑜𝑢𝑟𝑐𝑒
Emitter 1Τ𝑔𝑚 + 𝑍𝑏 Τ(𝛽 + 1) Source 1Τ𝑔𝑚
The equivalent impedance at a node will be the parallel
combination of all the impedances attached to it!
