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SC1006 Course Content

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32 views2 pages

SC1006 Course Content

Uploaded by

Alex Khoo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SC1006, CE1106 and CZ1106 – Computer Organisation and Architecture

Course Content
Topics
Computer Hardware Decomposition
Interconnection of processor, memory, data storage, power supplies and peripherals. Clock and
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reset circuitry.
Input devices such as touch screens, mice, and keyboards and output devices.
Data Representation, Memory Allocation and Access
2 Signed and unsigned number representation. Little Endian vs Big Endian. Character encoding (DEC
6-bit vs ASCII vs Unicode). Arrays, string (C and Pascal), structure and pointer representation. Data
alignment and data padding.
Central Processing Unit
Concept of a stored program. Allocation of memory to code and data segments in Von Neumann
3 architecture and dual memory spaces in Harvard architecture with concurrent access.
Programmer’s functional models of processors. Status register and flags. Control unit. Fetch-
decode-execute cycle.
Assembly Programming and Instruction Set Architecture
Assembly-level programming. Addressing modes. Use of Program Counter for instruction and data
access. Basic arithmetic and logical operations. Program control instructions. Implementing
position-independent code. Supervisor vs User modes. Privileged instructions.
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Instruction set architectures (ISA) and paradigms. Classifications based on accumulators, registers,
load-store and memory-to-memory transfers and operations. Differentiating characteristics of 8-bit
to 64-bit ISAs. Fixed-length vs variable-length instructions. Mnemonics, instruction encoding and
orthogonality.
High-level Software to Low-level Instructions
Mapping of high-level language constructs for control flow and data structures to machine-level
operations. Including ‘if’, ‘switch’, ‘for’ and ‘while’ with pre- and post- test conditions. Using examples
of code produced by a ‘C’ compiler. Compiler optimisation techniques (e.g. jump tables, loop
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unrolling) for execution speed or code size.
Modular programming, mechanisms for subroutine/function linkage, including return address,
parameter/result passing and local data. Parameter passing using register, memory and stacks.
Transparent subroutines. Implementing local variables with stack frame and frame pointer.
Signal Chain Sub-System
Interfacing to the Real World
- Analog to digital conversion
- Digital sampling process
- Interpreting digital logic levels
- Digital to Analog conversion
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Serial versus parallel data transfer.
Asynchronous versus synchronous digital data transfer.
Digital Serial Interface Standards e.g. UART, SPI.
Sources of interference to data transmission e.g. Signal Skews, Cross Talk. Programmed I/O.
Interrupts – flow mechanism and interrupt service routines.
Direct Memory Access – configuration, flow and notification mechanism
Memory Sub-System
Operating principles, design and interface consideration
- Volatile and non-volatile Memory
- Static RAM and Dynamic RAM
- Flash and EEPROM
- Magnetic HDD and Solid State Drive
7 Cache Memory Management
- Operating principles
- Cache Mapping Scheme (Direct Mapped)
Virtual Memory Management
- Physical and Virtual Memory Addressing Space
- Virtual Memory Management: Paging Scheme
Integration of Cache and Virtual Memory
Communication and User Interface Sub-System
Wired, e.g. USB, SATA, HDMI
8 Wireless, e.g. WIFI, Bluetooth
Input interface, e.g. Key Board, Mouse, Capacitive Touch, Camera, Microphone.
Output interface, e.g. Display and Speakers
Computer Arithmetic
Positional numbering systems.
Fixed Point Number System
- 2’s complement system.
- Fixed-point arithmetic.
- Carry vs. Overflow.
Floating point number system
9 - IEEE 754 standard.
- Floating-point arithmetic.
Fixed Point vs Floating Point Number system
Implementation consideration
- Effects of the fours operators (+, - , *, /)
- Effects of rounding.
- Handling of numbers with different magnitude
- Maximising precision during computation
Performance Optimization
Processor Pipeline Architecture
10 - Basic operating concept
- Pipeline conflicts and management
- Performance computation

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