2253483

SID: 2253483

Digital Systems Design with VHDL and

FPGAs (2023 MOD002717 TRI2 F01CHE)

ASSIGNMENT

Design and Simulation controlling DC

motor using PWM signal through FPGA
board.

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Table of contents

1 Abstract……………………………………………………. 3
2 Introduction………………………………………………... 3
3 Design Steps (Methodology)……………………………… 4
4 Problems must be solved………………………………….. 4
5 Possible solutions………………………………………….. 5
6 PWM duty cycle…………………………………………... 5
7 Why PWM to control (benefits) and how…………………. 6
8 VHDL Modelling types (Dataflow, structural, and
Behavioural)……………………………………………….. 7
9 Design the control of DC motor by PWM………………… 8
10 Configuration FPGA board with VHDL code synthesis in
Vivado and explanation of the codes……………………… 11
11 The H-bridge’s role………………………………………... 13
12 Appendix for pictures of the results……………………….. 14
13 Conclusion…………………………………………………. 18
14 References………………………………………………….. 19
15 Appendix for VHDL codes………………………………… 20

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Abstract

This report outlines the design and successful working implementation of a PWM controlled
DC motor, using VHDL for modelling, and verification through simulation. Dataflow,
Structural and Behavioural VHDL models have been used to leverage the strengths of each
approach to develop a robust, efficient, and flexible control environment to precisely regulate
the speed of the motor, using adjustable PWM duty cycles to maximise a motorís
responsiveness to varying operational demands. The performance is characterized with analysis
of the relationship between motor stall speed and PWM duty cycles with tables compiled from
captured data from the hardware to ensure that engineered control strategy would deliver an
adequate response after development testing and implementation. This study demonstrates that
VHDL is an effective method to develop control systems and through this comparison between
reference data and actual performance, an alternative to existing control applications is
proposed, which could lead to enhanced power efficiency and allow greater operational
stability. The fact is that precise control over DC motor speed can be changed very efficiently
through a control system that can be designed in VHDL.

Introduction

DC motor’s function based on Faraday's concept of electromagnetism, which asserts that a

conductor carrying an electric current will encounter a force when positioned within a magnetic
field. As per Fleming's "Left-hand rule for electric motors," the movement of this conductor is
consistently perpendicular to both the current and the magnetic field. The force can be
mathematically represented as F = BIL, where F represents force, B represents the magnetic
field, I represents current, and L represents the length of the conductor (Ikimi, 2020).
DC motors are classified into various types based on their design and structure. The
predominant variations comprise brushed or brushless, permanent magnet, series, and parallel.
A brushed DC motor employs a set of graphite or carbon brushes to conduct and deliver current
from the armature. Typically, these brushes are stored in close proximity to the commutator.
Additional beneficial duties of brushes in dc motors encompass guaranteeing sparkless
operating, regulating the current direction throughout rotation, and maintaining the cleanliness
of the commutator. Brushless DC motors are devoid of carbon or graphite brushes. Typically,
they consist of one or many permanent magnets that rotate around a stationary armature.
Brushless DC motors employ electronic circuits instead of brushes to regulate both the
rotational direction and speed (Ikimi, 2020).

Motors, especially, DC motors are used in varied fields from industrial machinery and
consumer electronics to automotive systems, advanced robotics, and aerospace technology.
Accurate control of speed, position, and torque is crucial for achieving efficient performance
and output in various general and specific applications. Motor control is essential in various
disciplines. In this chapter the main applications and significances will be introduced below.

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DC motors are responsible for operating many components in automobiles such as power
window regulators, windscreen wipers, electric power steering systems and cooling fans. Due
to their durability and capacity to offer accurate control, they are essential in contemporary
automotive design. Also, various domestic gadgets, such as blenders, mixers, hoover cleaners
and electric shavers, depend on direct current (DC) motors for effective and regulated
functioning. Additionally, DC motors are essential components of robotic systems, providing
precise control over movement and positioning in a wide range of applications, including
industry and healthcare. In aerospace engineering DC motors drive critical systems in aircraft,
spacecraft, and defence equipment. They are used in various control mechanisms, from landing
gear operation to missile guidance systems. Lastly, conveyor belts, machine tools, and
production lines often depend on DC motors for consistent and precise motion control, ensuring
efficient manufacturing processes (Medium, 2023).

DC motors possess superior initial torque compared to AC motors, facilitating the initiation of
motion. An inherent limitation of these motors is that they cannot be initiated unless they are
already operating with a load. DC motors can easily burn up if they operate without a load to
impede their speed. DC motors are well-suited for applications that require a consistent low-
speed or adjustable-speed torque. Also, AC motors are vulnerable to harmonic effects that have
the potential to destroy the equipment or result in severe heating of the iron or copper
components. Harmonic issues not only result in excessive noise but can lead to premature
motor failure or misfiring, which can cause damage to other equipment or disrupt the
manufacturing process. DC motors do not experience this problem, so completely resolving
the issue. DC motors provide superior speed regulation compared to AC motors. When dealing
with high-capacity systems, having exact control over the speed can determine the outcome of
a task, either resulting in success or damaging the motor. That is the reason why they are
frequently utilised in paper mills and rolling mills, where it is crucial to maintain a regular pace
in order to guarantee a continuous level of product quality. DC motors are well-suited for tasks
that require a consistent supply of low-speed torque or the ability to change torque levels.
(Nichols, 2019).

Design Steps (Methodology)

The technique to designing and implementing a DC motor control system utilising FPGA
involves a systematic process that emphasises careful planning and execution phases. This
method guarantees accurate manipulation of the motor's velocity and direction by employing a
pulse width modulation (PWM) technology. In this project, we're using FPGA technology to
make DC motor control even better. By using FPGA, we can make the motor do what we want
it to do faster and more accurately than ever before. This is going to be super useful in all those
places where DC motors are already being used, like robotics and automation systems, where
being able to control motors well is super important. Below are the detailed steps and
procedures that are followed:

Problems must be solved.

The primary issue this project tackles is how to precisely control the speed and direction of DC
motors using FPGA tech. DC motors are super important in all sorts of industries, like cars and

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factories, where they are used to power stuff and give fine-tuned control over speed. Also, DC
motors have to handle a variety of speeds to meet different needs, but standart analog or
mechanical controls often are not very precise or adaptable PWM can help by tweaking the
average power fed to the motor using digital signals, giving you more control over the speed
(Abbas, Chisab, and Mnati, 2021).

Many applications need the motor to spin in both directions. When you use an H-Bridge
together with an FPGA, you can easily reverse the motor's direction by simply changing the
polarity of the voltage supplied to it. The design must ensure a seamless change in direction
for both the electrical and mechanical systems. Furthermore, optimising the motor control
system to utilise the least amount of power while getting the most out of it is critical, especially
when working with highly sensitive energy sources. When adopting an FPGA-based control
system, ensure that it is built to be as efficient as possible to avoid wasted energy or heat
buildup (Abbas, Chisab, and Mnati, 2021).

Possible solutions.

It can be solved using Pulse-Width Modulation (PWM) technique. We can select between
fixed-frequency PWM, which changes the duty cycle but keeps the frequency constant, and
variable frequency PWM, which changes both the duty cycle and frequency. Fixed frequency
PWM is typically easy to set up and control using an FPGA, and it works well for most motor
control applications. Variable frequency PWM, on the other hand, can assist reduce
electromagnetic interference and improve motor efficiency when the load varies. Also, High-
resolution PWM can enable tighter control over motor speed and torque, particularly in
applications that need precise motions. FPGAs can provide high-resolution PWM signals due
to their fast clock speeds, enabling for more precise motor control (Taylor, 2023).

H-Bridge Configurations allow us to control the direction of a DC motor. We can accomplish

this with various H-Bridge configurations. An H-Bridge reverses the voltage on the motor,
allowing us to control its direction. To make things safe, our design should include measures
that prevent anything from happening simultaneously that could short-circuit the system. Soft
switching technique can make shifting directions simpler on the motor and H-Bridge, allowing
robot to run more smoothly and survive longer.

Designing simulations with VHDL code and advanced tools like the Xilinx ISE Design Suite
can help us evaluate our FPGA configuration before putting it into a physical device. This can
assist identify errors in your VHDL code or system architecture, saving you headaches later
when you apply it in the real world.

PWM duty cycles

In PWM, the speed of your motor is measured in revolutions per minute, and you can precisely
control it by tweaking the duty cycle. The duty cycle is basically the percentage of time a
voltage is on during each cycle. So, if you got a 40% duty cycle, the voltage would be high for
40% of the time and off for the other 60%. By changing this duty cycle, you can make the
average voltage delivered to your motor go up or down, allowing for precise control over your
motor's speed (Figure 1 and 2). This capacity not only ensures accuracy, but also allows your

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motor to adjust to changing conditions without wasting a lot of energy. It's like having a built-
in safety valve that allows you to dial in just the perfect amount of power when you need it,
without adding extraneous features. That's an interesting feature (Dietrich, 2022).

Figure 1. PWM signal with different Duty Cycle. (Dietrich, 2022).

Pulse width modulation (PWM) can be utilised to effectively address the challenges of
precision and efficiency while controlling the speed of DC motors. By what means does it
accomplish that? Initially, PWM deceives the motor by creating the illusion that it is still
operating on a fluctuating voltage alternating current power source. This capacity not only
ensures accuracy, but also allows your motor to adjust to changing conditions without wasting
a lot of energy. It's having a built-in safety valve that allows you to dial in just the perfect
amount of power when you need it, without adding extraneous features. That's an interesting
feature (Colley, 2020).

Why PWM to control (benefits) and how

PWM lets you adjust almost instantly to load shifts in the motor's load by changing the duty
cycle. PWM can improve latency and power waste in applications with variable loads, such
as welding robots. PWM adjusts input voltage quantity rather than absolute voltage level,
making it less sensitive to supply voltage swings. PWM controllers can vary duty cycles to
keep motor speed steady even if supplied voltage drops or spikes. PWM adjusts input voltage
rather than absolute voltage, making it less sensitive to supply voltage swings. The PWM
controller may vary the duty cycle to maintain motor speed even if the supplied voltage drops
or spikes (Figure 2)(Özer, Kıvrak, and Oğuz, 2017). Lastly, efficiency: The PWM quickly
turns the motor voltage on and off thousands of times in speed control, reducing heat loss. In
contrast, resistive systems dissipate power as heat.

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Figure 2. Voltage changing through PWM. (Özer, Kıvrak, and Oğuz, 2017).

Implementation using Microcontrollers or FPGA. PWM controllers can be realised by utilising

microcontrollers or programmable logic devices like FPGAs. These devices would generate
precise PWM signals based on input from real-time sensors and feedback systems. Applying
more advanced control algorithms, such as PID (Proportional-Integral-Derivative), allows for
finer tuning of motor performance (Garcia-Reyes et. al, 2022).

VHDL Modelling types (Dataflow, structural, and Behavioural)

There are three fundamental coding techniques that can be used to write an architecture,
namely, Dataflow, Behavioural and Structural. The distinction between these styles is
predicated on the variety of concurrent statements employed: A dataflow design exclusively
use concurrent signal assignment statements. A behavioural architecture exclusively uses
process statements. A structural architecture exclusively uses component instantiation
statements. Instead of exclusively adhering to one architectural style, we have the option to
combine two or more types, resulting in a hybrid or mixed design. Below other differences are
specified.

Dataflow style refers to a system that is defined based on the manner in which data moves
through it. The data dependencies in the description correspond to those found in a standard
hardware implementation. A dataflow description inherently entails a corresponding gate-level
implementation. Dataflow descriptions are comprised of multiple concurrent signal assignment
statements.

A behavioural description provides an algorithmic representation of a system's behaviour or

function. The behavioural style is the most abstract style. The description is abstract in that it
does not explicitly specify a specific gate-level implementation. The behavioural style
comprises one or more process statements. Each process statement is a singular concurrent
statement that comprises one or more sequential statements. The simulator executes sequential

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statements in the same order as they are written, similar to how sequential statements are
performed in a traditional programming language.

In the structural style of modelling, an entity is defined as a collection of interconnected

components. The architecture of the top-level design entity specifies the interaction of design
entities at lower levels. Each subordinate design element can be defined as a network of design
elements at the subsequent lower level, and so forth. Structural style is particularly
advantageous and effective when an intricate system is delineated as a network of relatively
intricate design components. This methodology enables the individual design entities to be
autonomously designed and validated prior to their use in the higher-level description (Pedroni,
2010).

Design the control of DC motor by PWM.

Our design will be based on following block diagram. The block diagram is shown in the
Figure-2.

Figure 3. Block diagram of DC motor control by FPGA board. (Abbas, Chisab, and Mnati,
2021).

To simulate the design and get result from it Vivado® Design Suite software, which is created
by AMD, is used. Using Vivado® Design Suite we can synthesize VHDL code in real hardware
board like Nexys4 DDR™ FPGA Board (Figure 3).

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Figure 4. Nexys4 DDR™ FPGA Board

The Nexys4 DDR board is a fully equipped digital circuit development platform that utilises
the latest Artix-7™ Field Programmable Gate Array (FPGA) technology from Xilinx®. The
Nexys4 DDR is equipped with a spacious FPGA (Xilinx component number XC7A100T-
1CSG324C), ample external memories, and a variety of USB, Ethernet, and other connections.
This makes it capable of accommodating a wide range of designs, from basic combinational
circuits to advanced embedded processors. The Nexys4 DDR is equipped with many integrated
peripherals including as an accelerometer, temperature sensor, MEMs digital microphone,
speaker amplifier, and other I/O devices. These built-in components enable the Nexys4 DDR
to be utilised for a diverse range of designs without the need for additional external
components.

The Nexys4 DDR also offers an improved collection of ports and peripherals, including:

* 16 user switches * 16 user LEDs * Two 4-digit 7-segment

displays
* USB-UART Bridge * Two tri-color LEDs * Micro SD card connector
* 12-bit VGA output * PWM audio output * PDM microphone

* 3-axis accelerometer * Temperature sensor * 10/100 Ethernet PHY

* 128MiB DDR2 * Serial Flash * Four Pmod ports
* Pmod for XADC signals * Digilent USB-JTAG port * USB HID Host for mice,
for FPGA programming and keyboards and memory
communication sticks

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Based on the block diagram following circuit is built (Figure 4) and following components are
used:

-through USB-UART Bridge bitstream generated in Vivado © Design Suite software is

transferred to the board from the computer,

-seven segment display shows us level of voltage

-buttons are used to change duty cycle of PWM signal

-through the output ports output voltage is sent to DC motor (in our project electric fan is used
as a DC motor).

Between output voltage and DC motor a transistor and a diode are applied to regulate the
current.

Figure 5. Circuit design based on the block diagram.

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Configuration FPGA board with VHDL code synthesis in Vivado and explanation of the
codes.

Let us split simulation process into steps:

1. Running Vivado® Design Suite and writing the code given in Appendix for VHDL
codes page (Figure 4).

2.
Figure 6. Main window of the Vivado® Design Suite and its code editor section.

3. Running the written code.

Figure 7. Running the written code

4. Testing the simulation by loading the bit stream to the FPGA board by clicking Run
Synthesis button, transferring the output voltage to the electric fan.
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5. If the fan is working, we check the implementation of PWM signal by increasing duty
cycle using push buttons on FPGA board. Changes are shown on the 4-bit 7 segment
display (Appendix for pictures of the results: Figures 1-10).

It can be seen from the graphs propellers of the fan are changing their rotating speeds as duty
cycle has been changed (See Appendix for pictures of the results: Figures 11-15).

We write the code in 4 .vhd files of the Vivado’s code editor section. Let’s analyse the
VHDL code file by file and section by section.

The first file creates PWM signal using following bunch of VHDL code (Appendix for
VHDL codes):

1-3rd lines are declaration of the libraries and packages used. From 5th to 15th lines include an
entity declaration. Inside the entity input and output ports are assigned to signals. These port
names are assigned to the FPGA boards ports in Vivado before simulating. In here 9 th and 10th
lines are buttons to increase or decrease the duty cycle. The second part (17th 119th lines) is
architecture of the program where main functionality goes on.
The second which is called DFF_bounce just simple flip flop code. It assigns the input D flip-
flop to the output Q only when it is enabled (en = '1') at a rising edge of the clock signal.
Similarly, it has library and package declaration, entity and architecture declaration parts.

Codes in Seven_segment file represents change in the value of the duty cycle of PWM signals.
It can be seen in the pictures that 7 segment display working accurately after implementing the
code (Appendix for the pictures: Figures 1-10).

The last file is constraint file. We can say it acts like a driver of the computers. It declares
which pins assigned to the signal names in the code.

DFF_bounce.vhd is fully behavioural code, where both seven_segment.vhd and

PWM_modulation are a combination of structural and dataflow modelling taht how things
function and organising information about the display.

In the next step, we add a H-bridge to control direction of the DC motor and test the simulation
again.

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H-Bridge

Figure 8. Applying H-Bridge in the circuit.

The H-bridge’s role

The H-bridge is the most fundamental and commonly employed circuit for driving and
controlling a DC motor. The H-bridge, depicted in Figure 7, has four switches that are typically
constructed using metal–oxide–semiconductor field-effect transistors (MOSFETs) arranged in
a "H" configuration surrounding a DC motor. An H-bridge is a circuit commonly used for
controlling DC motors. It enables precise control over the motor's direction and speed by
selectively activating and deactivating a series of switches (Hertz 2022).
In order to alter the rotational direction of the DC motor, it is imperative to modify the polarity
of the voltage that is supplied to the winding coil. The most prevalent method is utilising a "H
bridge" configuration to conveniently alter the direction of a DC motor. The circuit's
configuration bears a resemblance to the letter "H", so it was designated as a H bridge. Figure
(3) depicts a H bridge configuration. To achieve forward rotation, Q1 and Q4 are activated
while Q2 and Q3 are deactivated. During reverse rotation, Q2 and Q3 are activated while Q1
and Q4 are deactivated (Özer, Kıvrak, and Oğuz, 2017).

Figure 9. Direction of the current when H-bridge is applied. (Özer, Kıvrak, and Oğuz, 2017).

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Appendix for pictures of the results

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Figures 1-10. Seven segment display working.

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Figures 11-15. The fan is working in different speeds.

Conclusion

In conclusion, the report reveals that VHDL was effectively employed in designing and
developing of a DC motor control system using PWM (Pulse width Modulated) control. With
the combined use of Dataflow, Structural, and Behavioural VHDL models, it has been created
a flexible and robust control environment with effective stages allowing the user to control the
motor speed with adjustable PWM duty cycles. The relationship between motor speed and
PWM duty cycles demonstrated shows that the required motor speed increased when the duty
cycles were adjusted. Implementation on FPGA (Nexys4 DDR board) helped to create precise,
high speed, bitstream signals. Also, the use of FPGA in providing a superior efficiency with
improved power supplies. Use of H-bridge facilitates current flow control and control in
direction of the motor. In shortly, we have got desired results using FPGA board.

It can conclusively be stated that application of VHDL and FPGA-based control systems or
controllers in developing control systems can successfully perform well in comparison with
some conventional control methods. Low power consumption and high efficiency of
operation of the system provide an alternative means of developing power-saving and stable
systems.

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References:

Abbas M.A.H., Chisab F.R., and Mnati J.M. (2021) ‘Monitoring and controlling the speed
and direction of a DC motor through FPGA and comparison of FPGA for speed and
performance optimization’, International Journal of Electrical and Computer Engineering
(IJECE), 11(3903). Available at: http://doi.org/10.11591/ijece.v11i5.pp3903-3912 (Aceessed: 17
Apr 2024).

Colley S. (2020) Pulse-width Modulation (PWM) Timers in Microcontrollers. Available at:

https://www.allaboutcircuits.com/technical-articles/introduction-to-microcontroller-timers-
pwm-timers/ (Accessed 18 Apr. 24).

Dietrich Sh. (2022) Understanding the Basics of Pulse Width Modulation (PWM). Available
at: https://control.com/technical-articles/understanding-the-basicsof-pulse-width-modulation-
pwm/#:~:text=The%20duty%20cycle%20of%20a,off%20for%20the%20other%20half
(Accessed: 18 Apr 2024).

Garcia-Reyes et. al. (2022) ‘Level-Shift PWM Control of a Single-Phase Full H-Bridge
Inverter for Grid Interconnection, Applied to Ocean Current Power Generation’, Applied to
Ocean Current Power Generation, 15(5). Available at: https://doi.org/10.3390/en15051644
(Accessed: 18 Apr. 24).
Hertz J. (2022) H-bridge DC Motor Control Using Complementary PWM, Shoot-through,
and Dead-time. Available at: https://www.allaboutcircuits.com/technical-articles/h-bridge-dc-
motor-control-complementary-pulse-width-modulation-pwm-shoot-through-dead-time-pwm/

Ikimi O. (2020) Understanding DC Motor Operation Modes and Speed Regulation

Techniques. Available at: https://www.allaboutcircuits.com/news/a-basic-guide-to-dc-motors-
types-of-motors-operation-modes-and-their-applications/ (Accessed: 16 Apr 2024).

Medium (2023) Why is a DC motor important? Available at:

https://medium.com/@iastarun/why-is-a-dc-motor-important-bd47e0949fe9 (Accessed: 16
Apr 2024).

Nicolas R. R. (2019) Advantages of DC motors in industrial applications. Available at:

https://www.controlglobal.com/home/blog/11300357/advantages-of-dc-motors-in-industrial-
applications (Accessed: 16 Apr 2024).

Özer T., Kivrak S., and Oğuz Y. (2017) ‘H Bridge DC Motor Driver Design and
Implementation with Using dsPIC30f4011’, International Journal of Innovative Research in
Science, Engineering and Technology, 6. pp. 75-83. Available at:
https://www.researchgate.net/publication/317225711_H_Bridge_DC_Motor_Driver_Design_
and_Implementation_with_Using_dsPIC30f4011 (Accessed: 18 Apr. 24).

Pedroni A. V. (2010) Circuit design and Simulation with VHDL. 2nd Edtn. London:The MIT
Press.

Taylor A. (2023) FPGA Based Motor Control. Available at: https://www.hackster.io/adam-

taylor/fpga-based-motor-control-cd47e7 (Accessed: 17 Apr 24).

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Appendix for VHDL codes

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4 ----------------------------------------------------------------------------------------------------
5 entity pulsewidthmodulation is
6 port(
7 clk : in std_logic;
8 rst : in std_logic;
9 inc : in std_logic;
10 dec : in std_logic;
11 pwm_out : out std_logic;
12 a_to_g : out std_logic_vector(6 downto 0);
13 an : out std_logic_vector(7 downto 0)
14 );
15 end pulsewidthmodulation;
16 ---------------------------------------------------------------------------------------------------
17 architecture behaviural of pulsewidthmodulation is
18 component dff_button
19 port(
20 clk : in std_logic;
21 en : in std_logic;
22 d : in std_logic;
23 q : out std_logic
24 );
25 end component;
26 ---------------------------------------------------------------------------------------------------
27 component seven_seg
28 port(
29 clk_in : in std_logic;
30 data_in : in std_logic_vector(15 downto 0);
31 segs_out : out std_logic_vector(6 downto 0);
32 anodes_out : out std_logic_vector(7 downto 0)
33 );
34 end component;
35 ------------------------------------------------------------------------------------------------
36 signal duty : std_logic_vector(15 downto 0):= x"1388";
37 signal cnt : std_logic_vector(15 downto 0):= (others => '0');
38 signal pwm : std_logic;
39 signal slow_clk_en : std_logic := '0';
40 signal count_slow : std_logic_vector(23 downto 0):= (others => '0');
41 signal tmp1,tmp2,duty_inc: std_logic;
42 signal tmp3,tmp4,duty_dec: std_logic;
43 signal data_in : std_logic_vector(15 downto 0);
44
45 begin

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46 process(clk)
47 begin
48 if(rising_edge(clk)) then
49 count_slow <= count_slow + x"000001";
50 if(count_slow>=x"2faf08") then
51 count_slow <= x"000000";
52 end if;
53 end if;
54 end process;
55 slow_clk_en <= '1' when count_slow = x"2faf08" else '0';
56
57 stage0: dff_button port map(clk => clk, en => slow_clk_en, d => inc, q => tmp1);
58 stage1: dff_button port map(clk => clk, en => slow_clk_en, d => tmp1, q => tmp2);
59 duty_inc <= tmp1 and (not tmp2) and slow_clk_en;
60 stage2: dff_button port map(clk => clk, en => slow_clk_en, d => dec, q => tmp3);
61 stage3: dff_button port map(clk => clk, en => slow_clk_en, d => tmp3, q => tmp4);
62 duty_dec <= tmp3 and (not tmp4) and slow_clk_en;
63
64 -- seven segment output
65 a1: seven_seg port map(clk_in => clk, data_in => data_in, segs_out => a_to_g,
66 anodes_out => an);
67
68 process(clk) -- process controlling the counter
69 begin
70
71 if(rising_edge(clk))then
72 cnt <= cnt + x"1";
73 if(cnt >= x"270f")then
74 cnt <= x"0000";
75 end if;
76 if(rst = '1')then
77 duty <= x"1388";
78 data_in <= x"0032";
79 else
80 if(duty_inc='1' and duty <= x"2328") then
81 duty <= duty + x"3e8";
82 elsif(duty_dec='1' and duty>=x"3e8") then
83 duty <= duty - x"3e8";
84 end if;
85 end if;
86
87 if(duty >= x"2710")then
88 data_in <= x"0100";
89 elsif(duty >= x"2328")then
90 data_in <= x"0090";
91 elsif(duty >= x"1f40")then
92 data_in <= x"0080";

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93 elsif(duty >= x"1b58")then

94 data_in <= x"0070";
95 elsif(duty >= x"1770")then
96 data_in <= x"0060";
97 elsif(duty >= x"1388")then
98 data_in <= x"0050";
99 elsif(duty >= x"fa0")then
100 data_in <= x"0040";
101 elsif(duty >= x"bb8")then
102 data_in <= x"0030";
103 elsif(duty >= x"7d0")then
104 data_in <= x"0020";
105 elsif(duty >= x"3e8")then
106 data_in <= x"0010";
107 elsif(duty >= x"0")then
108 data_in <= x"0000";
109 else
110 data_in <= x"0032";
111 end if;
112
113
114 end if;
115 end process;
116
117 pwm <= '1' when cnt < duty else '0';
118 pwm_out <= pwm;
119 end architecture;
120 ----------------------------------------------------------------------------------------------------------
121 ----------------------------------------------------------------------------------------------------------
DFF_bounce.vhd
----------------------------------------------------------------------------------------------------
1 library ieee;
2 use ieee.std_logic_1164.all;
3 ----------------------------------------------------------------------------------------------------
4 entity dff_button is
5 port (
6 clk : in std_logic;
7 en : in std_logic;
8 d : in std_logic;
9 q : out std_logic
10 );
11 end dff_button;
12 ----------------------------------------------------------------------------------------------------
13 architecture arch of dff_button is
14 begin
15 process(clk)

22
 2253483

16 begin
17 if (rising_edge(clk)) then
18 if (en = '1') then
19 q <= d;
20 end if;
21 end if;
22 end process;
23 end arch;
24 ----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
seven_segment.vhd
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
1 use ieee.numeric_std.all;
2 ----------------------------------------------------------------------------------------------------
3 entity seven_seg is
4 port(
5 clk_in : in std_logic;
6 data_in : in std_logic_vector(15 downto 0);
7 segs_out : out std_logic_vector(6 downto 0);
8 anodes_out : out std_logic_vector(7 downto 0)
9 );
10 end entity;
11 ---------------------------------------------------------------------------------------------------
12 architecture rtl of seven_seg is
13 signal count : unsigned(18 downto 0) := (others => '0');
14 signal count_next : unsigned(18 downto 0);
15 signal anodeSelect : std_logic_vector(1 downto 0);
16 signal nibble : std_logic_vector(3 downto 0);
17 signal segs : std_logic_vector(6 downto 0);
18
19 begin
20 -- Infer counter register
21 process(clk_in)
22 begin
23 if ( rising_edge(clk_in) ) then
24 count <= count_next;
25 end if;
26 end process;
27
28 -- Increment counter and derive anode select from top two bits
29 count_next <= count + 1;
30 anodeSelect <= std_logic_vector(count(18 downto 17));
31
32 -- Drive anodes
33 with anodeSelect select anodes_out <=

23
 2253483

34 "11111111" when "0000",

35 "11111011" when "0001",
36 "11111101" when "0010",
37 "11111110" when "0011",
38 "01111111" when "0100",
39 "10111111" when "0101",
40 "11011111" when "0110",
41 "11101111" when others;
42
43 -- Choose a nibble to display
44 with anodeSelect select nibble <=
45 data_in(15 downto 12) when "00",
46 data_in(11 downto 8) when "01",
47 data_in(7 downto 4) when "10",
48 data_in(3 downto 0) when others;
49
50 -- Decode chosen nibble
51 with nibble select segs <=
52 "1000000" when "0000",
53 "1111001" when "0001",
54 "0100100" when "0010",
55 "0110000" when "0011",
56 "0011001" when "0100",
57 "0010010" when "0101",
58 "0000010" when "0110",
59 "1111000" when "0111",
60 "0000000" when "1000",
61 "0010000" when "1001",
62 "0001000" when "1010",
63 "0000011" when "1011",
64 "1000110" when "1100",
65 "0100001" when "1101",
66 "0000110" when "1110",
67 "0001110" when others;
68
69 -- Drive segs_out
70 segs_out <= segs;
71 end architecture;
72
73
==========================================================
Constraint file
--------------------------------------------------------------------------------------------------
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {CLK}];
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {Inc}];
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {Dec}];

24
 2253483

set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports

{a_to_g[0] }];
set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[1] }];
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[2] }];
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[3] }];
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[4] }];
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[5] }];
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports
{a_to_g[6] }];

set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports { an[0] }];

set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports { an[1] }];
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports { an[2] }];
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports { an[3] }];
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports { an[4] }];
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports { an[5] }];
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports { an[6] }];
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports { an[7]
}];

set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {RST}];

set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports
{PWM_OUT}];

25