HCSDS5012T (MCP)
HCSDS5012T (MCP)
Marks: 60
HCSDS5012T (Theory)
Interfacing: Memory address decoding, cache memory and cache controllers, I/O
5 12
interface, keyboard, display, timer,
Total 52
Books and References:
1. Barry B. Brey : The Intel Microprocessors : Architecture, Programming and
Interfacing. Pearson Education, Sixth Edition,2009.
2. Walter A Triebel, Avtar Singh; The 8088 and 8086 Microprocessors Programming,
Interfacing, Software, Hardware, and Applications. PHI, Fourth Edition 2005.
3. Microprocessor Architecture, programming and application with the 8085 – Ramesh S. Gaonkar, 4th Edition,
Penram International Publishing.