Part 1: Differential Amplifier Design

1) We want to design a resistive loaded differential amplifier with the specifications below.
NOTE: that the bias current is split between two transistors; each transistor gets 𝐼𝐷 = 20𝜇𝐴.

Parameter

Supply (𝑽𝑫𝑫) 1.8𝑉

Bias current (𝑰𝑺𝑺) 40𝜇𝐴

Differential gain 8

CM output level1 𝑉𝐷𝐷/3

Load capacitance 1𝑝𝐹

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Note that 𝐼𝑆𝑆𝑅𝐷 = 2𝑉𝑜𝑢𝑡−𝐶𝑀 must be smaller than (𝑉𝐷𝐷 – 𝑉𝑑𝑠𝑎𝑡3) for proper large signal characteristics,
why?
2) Since the output level is closer to the ground rail, we will use a PMOS input stage. Assume
the PMOS will not be placed in a dedicated well to save the area. Assume we will use a simple
current mirror for biasing.

Figure 1 schematic

𝑉𝑅𝐷 0.6
•Choose 𝑹𝑫 to meet the CM output level spec. 𝑅𝐷 = 𝐼
= 20𝜇
= 30𝐾Ω.

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•The differential amplifier gain is given by
|𝐴𝑣| ≈ 𝑔𝑚(𝑅𝐷||𝑟𝑜)
•We will choose 𝐿 to set 𝑟𝑜 ≫ 𝑅𝐷 → 𝑟𝑜 = 10 × 𝑅𝐷.

𝐼 𝑉
|𝐴𝑣| ≈ 0.91 × 𝑔𝑚𝑅𝐷 = 0.91 × 2𝑉𝐷∗ × 𝑅𝐷=1.82 𝑉𝑅𝐷
∗

•Choose 𝑽∗ to meet the differential gain spec.

𝟏.𝟖𝟐𝑽𝑹𝑫
𝑽∗ = 𝑨𝑽

•Assume we will set 𝑉𝐷𝑆 of the tail current source to 300𝑚𝑉 to allow more output swing. Report the
input pair sizing using SA.

Figure 2 sizing assistant parameters.

From sizing assistant parameters is 𝑊 = 15.88𝜇𝑚 𝐿 = 420𝑛𝑚. 𝑉𝑇𝐻 = 533.7𝑚𝑉

•Give the above assumption, calculate the CM input level. Calculate the min and max CM input
levels. Is the selected CM input level in the valid range?
𝑉𝐼𝑁𝐶𝑀𝐿𝐸𝑉𝐸𝐿 = 1.8 − 300𝑚 − 𝑉𝐺𝑆𝐷𝐼𝐹𝐹 = 1.8 − 300𝑚 − 643.3𝑚 = 856.7𝑚𝑉
𝑉𝐼𝑁𝐶𝑀𝑀𝐼𝑁 = 𝑉𝑅𝐷 − 𝑉𝑇𝐻 = 0.6 − 527.4𝑚 = 72.6𝑚𝑉
𝑉𝐼𝑁𝐶𝑀𝑀𝐴𝑋 = 𝑉𝐷𝐷 − 𝑉 ∗ − 𝑉𝐺𝑆𝐷𝐼𝐹𝐹 = 1.8 − 138.7𝑚 − 643.3𝑚 = 1.0202𝑉
Yes, CM input level in the range.
•The tail current source has the following specifications:
Parameter

Input current 20𝜇𝐴

Percent mismatch: 𝝈(𝑰𝒐𝒖𝒕)/𝐼𝑜𝑢𝑡 ≤ 2%

Compliance voltage ≤ 200𝑚𝑉

Area Minimize

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10)

Figure 3 sizing assistant.

Figure 4 plot parameters vs v*

•As seen in the plot, for a given mismatch requirement, the minimum area is achieved at the max 𝑉∗.
Similarly, for a given area requirement, the minimum mismatch is achieved at the max 𝑉∗. That’s why
current mirrors are commonly biased in strong inversion.
•Given the compliance voltage spec, report the above figure with a cursor added to the selected
design point.

From the graph 𝑊 = 8.79𝜇𝑚 𝐿 = 525.171𝑛𝑚

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 Part 2: Differential Amplifier Simulation
OP simulation

Figure 5 DC Operating point

All transistors operate in saturation.

Diff small signal ccs

Figure 6 plot VODIFF vs frequency

Figure 7 results from simulator

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 Figure 8 plot VODIFF vs frequency in dB

Hand analysis:
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𝐴𝑉𝑑 = 𝑔𝑚(𝑅𝐷 ||𝑟𝑜 ) = 285.8𝜇 ∗ (30𝐾 || 3.191𝜇 ) = 7.825
1
𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = = 5.67MHZ
2𝜋(𝑅𝐷 ||𝑟𝑜 )∗(𝐶𝑔𝑑 +𝐶𝑑𝑏 +𝐶𝐿)
Simulator Analytical
Gain 7.827 7.825
bandwidth 5.697MHZ 5.67MHZ

CM small signal ccs

Figure 9 plot VOCM vs frequency

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 Figure 10 plot VOCM vs frequency

Figure 11 results from simulator

Hand analysis:
𝑔𝑚 𝑅𝐷
𝐴𝑉𝐶𝑀 = 1+2(𝑔 = 96𝑚
𝑚 +𝑔𝑚𝑏 )𝑟𝑜1

Simulator Analytical
Gain 95.16m 96m

•Yes, the gain is smaller than one as expected to reject the CM signal.

• The system first faces the dominant pole which gives the -20db/dec that the graphs shows Then it
faces a zero which tries to increase the slope which shows the slight increase in slope at about 10^7 Hz
then comes the non-dominant pole which decreases the slope again, because tail current source is
shunted by capacitance so at high frequency another pole due to this capacitance come to action which
effects on bode plot and also impedance increases.

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 Figure 12 plot Avd/Avcm

From simulator CMMR = 38.2852dB

𝐴 (𝑔𝑚 (𝑅𝐷 ||𝑟𝑜 ))
𝐶𝑀𝑀𝑅 = 𝑣𝑑 = 𝑔 𝑅 = 81.5 =38.223dB.
𝐴𝑣𝑐𝑚 ( 𝑚 𝐷 )
1+2(𝑔𝑚+𝑔𝑚𝑏)𝑅𝑠𝑠

Simulator Analytical
CMMR 38.2852dB 38.223dB

the same reason for the variations of AVCM because the system faces dominant pole then it faces a zero
which slightly increase the slope then face another pole which continue to the end, due to capacitance
which shunt Rss and decrease impedance and come into action with pole.

Diff large signal ccs

Figure 13 plot VODIFF vs Vid

The analytical range:

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−𝐼𝑆𝑆 𝑅𝐷 → 𝐼𝑆𝑆 𝑅𝐷 − 1.2 → 1.2
The simulator range:
-1.194 → 1.194

CM large signal ccs (region vs VICM)

Figure 14 plot regions

I have the negative input range to get minimum input why?

Because we haven’t current equal 20𝜇𝐴 exactly so drop in resistance not equal exactly 0.6V and when
we do simulator range of 𝑉𝑖𝑛𝑐𝑚 by 𝑉 ∗ and simulator calculate it using 𝑉𝐷𝑆𝐴𝑇

From simulator range from

-74.6843𝑚𝑉 𝑏𝑢𝑡 𝑤𝑒 𝑠𝑡𝑎𝑟𝑡 𝑠𝑤𝑒𝑒𝑝 𝑓𝑟𝑜𝑚 𝑧𝑒𝑟𝑜 𝑖 𝑤𝑖𝑙𝑙 𝑡𝑎𝑘𝑒 𝑧𝑒𝑟𝑜 𝑎𝑠 min 𝑣𝑎𝑙𝑢𝑒 𝑡𝑜 1.03584 𝑚𝑉

From part one 𝑉𝐼𝑁𝐶𝑀𝑀𝐼𝑁 = 𝑉𝑅𝐷 − 𝑉𝑇𝐻 = 0.6 − 527.4𝑚 = 72.6𝑚𝑉.

𝑉𝐼𝑁𝐶𝑀𝑀𝐴𝑋 = 𝑉𝐷𝐷 − 𝑉 ∗ − 𝑉𝐺𝑆𝐷𝐼𝐹𝐹 = 1.8 − 138.7𝑚 − 643.3𝑚 = 1.0202𝑉

The range from simulator = 1.03584-0=1.03584V

The range if used the minimum -74.6843 =1.03584+74.6843=1.11 V.

The range hand analysis =1.0202-72.6m=0.9476 V

Simulation Hand analysis
Max 1.03584 1.0202
Min 0 &&-74.6843 I will take 72.6m
zero as minimum because
starts from zero
rang 1.03584 if I take negative 0.9476 V
min value the range will be
1.11

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CM large signal ccs (GBW vs Vicm)

Figure 15 plot VODIFF vs Vicm

Figure 16 max output Vodiff

𝑉𝑂𝐷𝐼𝐹𝐹90% = 0.9 ∗ 7.864 = 7.0776𝑉

Figure 17 plot VODIFF and regions vs VCM

From the graph the 𝐶𝑀𝑟𝑎𝑛𝑔𝑒 1.1078 − 27.7907𝑚 = 1.08𝑉

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From plot of regions 𝐶𝑀𝑟𝑎𝑛𝑔𝑒 1.03584 + 74.6843𝑚 = 1.11𝑉 when I plot regions, I found min is this
negative -74.6843 but the sweep required starts from zero.
From plot of regions 𝐶𝑀𝑟𝑎𝑛𝑔𝑒 1.03584 − 0 = 1.03584𝑉 Because sweep starts from zero, I will take it
as min value.
GBW Regions
Range 1.08V 1.03584 V
1.1 V if we take vmin equal -
74m

The GBW is way better than the regions as the regions first is a simulation parameter only and second
has a very sharp edged between transitions while the GBW is a logical and experimental way to tell the
valid range and leaves the designer to his own estimation whether he accepts 90% of the output or
maybe less.

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