Session 3

‫ﻃﺮﺍﺣﯽ ﻳﮏ ﭘﺮﺩﺍﺯﺷﮕﺮ ﺗﮏ ﭼﺮﺧﻪ ﺍی‬

Data and Control Path

Advanced Computer Architecture & Design

1
Science & Research Branch
 ‫ﺷﻤﺎی ﺍﺻﻠﯽ‬
: ‫• ﮐﺎﺭﺍﻳﯽ ﻳﮏ ﻣﺎﺷﻴﻦ ﺑﺮ ﺍﺳﺎﺱ ﺳﻪ ﻋﺎﻣﻞ ﺗﻌﻴﻴﻦ ﻣﯽ ﺷﻮﺩ‬

( Inst. Count)‫– ﺗﻌﺪﺍﺩ ﺩﺳﺘﻮﺭ ﺍﻟﻌﻤﻞ ﻫﺎ‬

( Cycle Time ) ‫– ﺯﻣﺎﻥ ﻫﺮ ﭼﺮﺧﻪ‬

(CPI(Clock Cycle Per Instruction))‫– ﭼﺮﺧﻪ ﻫﺎی ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

CPI

Inst. Count Cycle Time

2 Advanced Computer Architecture & Design
Science & Research Branch
 ‫• ﮐﺎﻣﭙﺎﻳﻠﺮ ﻭ ﻣﻌﻤﺎﺭی ﻣﺠﻤﻮﻋﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

‫ﺗﻌﻴﻴﻦ ﺗﻌﺪﺍﺩ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻻﺯﻡ ﺑﺮﺍی ﻳﮏ ﺑﺮﻧﺎﻣﻪ ﻣﻔﺮﻭﺽ‬

‫• ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﭘﺮﺩﺍﺯﻧﺪﻩ‬

‫ﺯﻣﺎﻥ ﭼﺮﺧﻪ ﺳﺎﻋﺖ ﻭ ﺗﻌﺪﺍﺩ ﭼﺮﺧﻪ ﺳﺎﻋﺖ ﺑﻪ ﺍﺯﺍی ﻳﮏ‬

‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 ‫ﺩﺭ ﺍﻳﻦ ﻓﺼﻞ ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﮐﻪ ﺷﺎﻣﻞ ﺯﻳﺮ ﻣﺠﻤﻮﻋﻪ ﺍی ﺍﺯ‬
‫ﻣﺠﻤﻮﻋﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ‪ MIPS‬ﺍﺳﺖ ﺑﺮﺭﺳﯽ ﺧﻮﺍﻫﺪ ﺷﺪ‪:‬‬

‫‪ -‬ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻠﻬﺎی ﺩﺳﺘﻴﺎﺑﯽ ﻭﺍﺭﺟﺎﻉ ﺑﻪ ﺣﺎﻓﻈﻪ‪sw ، lw:‬‬

‫‪ -‬ﺍﻋﻤﺎﻝ ‪ ALU‬ﺣﺴﺎﺑﯽ ﻭ ﻣﻨﻄﻘﯽ‪add, sub, and, or :‬‬

‫‪ -‬ﺩﺳﺘﻮﺭﺍﺕ ﺍﻧﺸﻌﺎﺏ ﺩﺭ ﺻﻮﺭﺕ ﺗﺴﺎﻭی)‪ (beq‬ﻭ ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺵ )‪(j‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 MIPS ‫ﻗﺎﻟﺐ ﻫﺎی ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی‬:‫ﻳﺎﺩﺁﻭﺭی‬
.‫ﺗﺎ ﻗﺎﻟﺐ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺴﺘﻨﺪ‬3 .‫ ﺑﻴﺖ ﺍﺳﺖ‬32 ‫ﻃﻮﻟﺸﺎﻥ‬MIPS ‫• ﻫﻤﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی‬
6
31 26 21 16 11 0 R-type –
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
I-type –
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits J-type –
31 26 0
op target address
6 bits 26 bits
:‫ﺩﺍﺭﺍی ﻓﻴﻠﺪﻫﺎی ﻣﺘﻔﺎﻭﺗﯽ ﻫﺴﺘﻨﺪ‬
‫ﻋﻤﻠﮑﺮﺩ ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬:OP –
‫ﻣﻨﺒﻊ ﻭﻣﻘﺼﺪ ﻣﺨﺼﻮﺹ ﺛﺒﺎﺕ ﻫﺎ‬:rs,rt,rd –
‫ ﺍﻧﺪﺍﺯﻩ ﺷﻴﻔﺖ‬:shamt –
”op”‫ﺍﻧﺘﺨﺎﺏ ﮐﺮﺩﻥ ﻋﻤﻠﻴﺎﺕ ﻣﺘﻔﺎﻭﺕ ﺩﺭ ﻓﻴﻠﺪ‬:Funct –
‫ﺍﻓﺴﺖ ﺁﺩﺭﺱ ﻳﺎ ﻣﻘﺪﺍﺭ ﻓﻮﺭی‬:address / immediate –
‫ﺁﺩﺭﺱ ﻫﺪﻑ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﭘﺮﺵ‬:target address –
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Science & Research Branch
 ‫ﺑﺮﺍﻱ ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻠﻲ ‪ 2‬ﮔﺎﻡ ﻧﺨﺴﺖ ﻣﺸﺎﺑﻪ ﺍﺳﺖ‪:‬‬

‫‪ -1‬ﻭﺍﻛﺸﻲ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺍﺯ ﻣﺤﻠﻲ ﺍﺯ ﺣﺎﻓﻈﻪ ﺣﺎﻭﻱ ﻛﺪ ﻛﻪ ﺷﻤﺎﺭﻧﺪﻩ ﺑﺮﻧﺎﻣﻪ ﺑﻪ‬

‫ﺁﻥ ﺍﺷﺎﺭﻩ ﻣﻲ ﻛﻨﺪ‪.‬‬

‫‪ -2‬ﺧﻮﺍﻧﺪﻥ ﻳﻚ ﻳﺎ ﺩﻭ ﺭﺟﻴﺴﺘﺮ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻣﻴﺪﺍﻥ ﻫﺎﻱ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺮﺍﻱ‬

‫ﺍﻧﺘﺨﺎﺏ ﺍﻳﻦ ﺭﺟﻴﺴﺘﺮﻫﺎ‬

‫ﭘﺲ ﺍﺯ ﺍﻳﻦ ‪ 2‬ﻣﺮﺣﻠﻪ ﺳﺎﻳﺮ ﺍﻋﻤﺎﻝ ﻻﺯﻡ ﺑﺮﺍﻱ ﺗﻜﻤﻴﻞ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﻪ ﺭﺩﻩ ﻳﺎ‬
‫ﻛﻼﺱ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺴﺘﮕﻲ ﺩﺍﺭﺩ‪ .‬ﻛﻪ ﺧﻮﺷﺒﺨﺘﺎﻧﻪ ﺑﺮﺍﻱ ﻫﺮ ‪ 3‬ﺭﺩﻩ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺍﻋﻤﺎﻝ ﻻﺯﻡ ﻳﻜﺴﺎﻥ ﺍﺳﺖ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 ‫ﻣﺮﺍﺣﻞ ﻻﺯﻡ ﺑﺮﺍی ﺍﺟﺮﺍی ﺩﺳﺘﻮﺭ‪:‬‬

‫• ﻭﺍﮐﺸﯽ ﺩﺳﺘﻮﺭ ﺍﺯ ﻣﺤﻠﯽ ﮐﻪ ‪ PC‬ﺍﺷﺎﺭﻩ ﻣﻴﮑﻨﺪ‬

‫• ﺧﻮﺍﻧﺪﻥ ﻣﺤﺘﻮی ‪ 1‬ﻳﺎ ‪ 2‬ﺭﺟﻴﺴﺘﺮ ﺑﻨﺎ ﺑﻪ ﻓﻴﻠﺪﻫﺎی ﻣﺸﺨﺺ‬
‫ﺷﺪﻩ ﺩﺭ ﺩﺳﺘﻮﺭ‬
‫• ﺍﻧﺠﺎﻡ ﻣﺤﺎﺳﺒﺎﺕ ‪ALU‬‬

‫ﻫﻤﻪ ﺩﺳﺘﻮﺭﺍﺕ ﺑﻪ ﻧﻮﻋﯽ ﺑﻪ ‪ ALU‬ﻧﻴﺎﺯ ﺩﺍﺭﻧﺪ‪:‬‬

‫– ﺩﺳﺘﻮﺭﺍﺕ ﺍﻧﺘﻘﺎﻝ ﺩﺍﺩﻩ ﻭ ﺍﺭﺟﺎﻉ ﺑﻪ ﺣﺎﻓﻈﻪ‪ :‬ﺑﺮﺍی ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ‬
‫– ﺩﺳﺘﻮﺭﺍﺕ ﻣﺤﺎﺳﺒﺎﺗﯽ ﻭ ﻣﻨﻄﻘﯽ‪ :‬ﺑﺮﺍی ﺍﻧﺠﺎﻡ ﻣﺤﺎﺳﺒﻪ‬
‫– ﺩﺳﺘﻮﺭﺍﺕ ﺍﻧﺸﻌﺎﺏ‪ :‬ﺑﺮﺍی ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﻣﻮﺛﺮ ﻭ ﻣﻘﺎﻳﺴﻪ‬
‫‪Advanced Computer Architecture & Design‬‬
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‫‪Science & Research Branch‬‬
 ‫ﺗﻔﺎﻭﺕ ﺩﺭ ﺍﺟﺮﺍی ﺩﺳﺘﻮﺭﺍﺕ‬
‫• ﺩﺳﺘﻮﺭﺍﺕ ﺍﻧﺘﻘﺎﻝ ﺩﺍﺩﻩ‬
– load: access memory for read data {ld R1, 0(R2)}
– store: access memory for write data {ld 0(R2), R1}
ALU‫• ﺩﺳﺘﻮﺭﺍﺕ‬
– no memory access for operands
– access a register for write of result {add R1,R2, R3}
‫• ﺩﺳﺘﻮﺭﺍﺕ ﺍﻧﺸﻌﺎﺏ‬
– change PC content based on comparison {bne
R1, Loop}
Advanced Computer Architecture & Design
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Science & Research Branch
 ‫ﻣﺮﺍﺣﻞ ﻣﻮﺭﺩ ﻧﻴﺎﺯ ﺩﺳﺘﻮﺭﺍﺕ ﻣﺨﺘﻠﻒ‬
Fetch Decode Read Compute Access Write
Registers Memory Registers
add/sub X X X X X
load X X X X X X
store X X X X X
conditional X X X X
branch
unconditional X X X
branch

Advanced Computer Architecture & Design

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Science & Research Branch
 Data Path ‫ﺍﺟﺰﺍی‬
‫ ﺑﺎﻳﺪ ﺷﺎﻣﻞ ﺍﻟﻤﺎﻧﻬﺎی ﺗﺮﮐﻴﺒﯽ ﻭ‬Data Path ‫• ﺣﺪﺍﻗﻞ ﺍﺟﺰﺍی‬
.‫ﺗﺮﺗﻴﺒﯽ ﺑﺎﺷﺪ ﮐﻪ ﺑﺘﻮﺍﻧﺪ ﻋﻤﻠﻴﺎﺕ ﺯﻳﺮ ﺭﺍ ﺍﺟﺮﺍ ﻧﻤﺎﻳﺪ‬

– Fetch instructions and data from memory

– Decode instructions and dispatch them to the
execution unit
– Execute arithmetic & logic operations

Advanced Computer Architecture & Design

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Science & Research Branch
 MIPS ‫ﻧﻤﺎی ﺳﻄﺢ ﺑﺎﻻی ﻳﮏ ﭘﻴﺎﺩﻩ ﺳﺎﺯی‬

Advanced Computer Architecture & Design

11
Science & Research Branch
 ‫‪ -1‬ﻫﻤﺎﻧﻄﻮﺭ ﻛﻪ ﺩﺭ ﺷﻜﻞ ﻣﺸﺨﺺ ﺍﺳﺖ ﺩﺭ ﭼﻨﺪ ﻣﻜﺎﻥ ﺩﺍﺩﻩ ﺍﻱ ﻛﻪ ﺑﻪ ﻳﻚ ﻭﺍﺣﺪ ﻣﺸﺨﺺ ﻣﻲ ﺭﻭﺩ‬
‫ﺍﺯ ‪ 2‬ﻣﻨﺒﻊ ﻣﺨﺘﻠﻒ ﻣﻲ ﺁﻳﺪ‪.‬ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻣﻘﺪﺍﺭﻱ ﻛﻪ ﺩﺭ ‪ PC‬ﻧﻮﺷﺘﻪ ﻣﻲ ﺷﻮﺩ ﻣﻲ ﺗﻮﺍﻧﺪ ﺍﺯ ﻳﻜﻲ ﺍﺯ‬
‫‪ 2‬ﺟﻤﻊ ﻛﻨﻨﺪﻩ ﺑﻴﺎﻳﺪ‪ .‬ﻭ ﻳﺎ ﺩﺍﺩﻩ ﺍﻱ ﻛﻪ ﺩﺭ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﻧﻮﺷﺘﻪ ﻣﻲ ﺷﻮﺩ ﻣﻲ ﺗﻮﺍﻧﺪ ﻳﺎ ﺍﺯ ‪ ALU‬ﻭ‬
‫ﻳﺎ ﺍﺯ ﺣﺎﻓﻈﻪ ﺩﺍﺩﻩ ﺑﻴﺎﻳﺪ‪.‬ﺩﺭ ﻋﻤﻞ ﺍﻳﻦ ﺧﻄﻮﻁ ﺩﺍﺩﻩ ﺭﺍ ﻧﻤﻲ ﺗﻮﺍﻥ ﺑﻪ ﺳﺎﺩﮔﻲ ﺑﻪ ﻫﻢ ﻭﺻﻞ ﻛﺮﺩ‪.‬‬

‫ﻣﺎﻟﺘﻲ ﭘﻠﻜﺴﺮ ﻳﺎ ﮔﺰﻳﻨﺸﮕﺮ ﺩﺍﺩﻩ‬

‫ﺑﺴﺘﮕﻲ ﺑﻪ ﭼﮕﻮﻧﮕﻲ ﺗﻨﻈﻴﻢ ﺧﻄﻮﻁ ﻛﻨﺘﺮﻟﻲ‬

‫ﺗﻨﻈﻴﻢ ﺑﺮ ﺍﺳﺎﺱ ﺍﻃﻼﻋﺎﺕ ﮔﺮﻓﺘﻪ ﺷﺪﻩ ﺍﺯ ﺩﺳﺘﻮﺭ ﺩﺭ ﺣﺎﻝ ﺍﺟﺮﺍ‬

‫‪Advanced Computer Architecture & Design‬‬
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 ‫‪ -2‬ﺑﺴﺘﻪ ﺑﻪ ﻧﻮﻉ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺎﻳﺪ ﭼﻨﺪ ﻭﺍﺣﺪ ﺭﺍ ﮐﻨﺘﺮﻝ ﻧﻤﻮﺩ‪.‬‬
‫ﻣﺜﻼ ﺍﺯ ﺣﺎﻓﻈﻪ ﺩﺍﺩﻩ ﺑﺎﻳﺪ ﺑﻪ ﻫﻨﮕﺎﻡ ﺑﺎﺭ ﮐﺮﺩﻥ‪،‬ﺧﻮﺍﻧﺪ ﻭ ﺑﻪ ﻫﻨﮕﺎﻡ‬
‫ﺫﺧﻴﺮﻩ ﮐﺮﺩﻥ‪ ،‬ﻧﻮﺷﺖ‪.‬‬
‫ﺩﺭ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﺑﺎﻳﺪ ﺑﻪ ﻫﻨﮕﺎﻡ ﺑﺎﺭ ﮐﺮﺩﻥ ﻭ ﻧﻴﺰ ﺩﺭ ﺣﻴﻦ ﻳﮏ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺣﺴﺎﺑﯽ‪-‬ﻣﻨﻄﻘﯽ ﻧﻮﺷﺖ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﺍﺻﻠﯽ ﺯﻳﺮ ﻣﺠﻤﻮﻋﻪ ‪ MIPS‬ﺷﺎﻣﻞ ﻣﺎﻟﺘﯽ ﭘﻠﮑﺴﺮﻫﺎ‬
‫ﻭ ﺧﻄﻮﻁ ﮐﻨﺘﺮﻟﯽ‬

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 ‫ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﺟﺰﺋﻴﺎﺕ‬
‫ﺑﺮﺍﻱ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺟﺰﺋﻴﺎﺕ ﻧﻴﺎﺯ ﺑﻪ ﺍﻓﺰﻭﺩﻥ ﻭﺍﺣﺪﻫﺎﻱ ﻋﻤﻠﻴﺎﺗﻲ ﺑﻴﺸﺘﺮ‪،‬ﺍﻓﺰﺍﻳﺶ ﺍﺗﺼﺎﻻﺕ ﺑﻴﻦ‬
‫ﻭﺍﺣﺪﻫﺎ ﻭ ﺍﻓﺰﻭﺩﻥ ﻭﺍﺣﺪ ﻛﻨﺘﺮﻟﻲ ﺩﺍﺭﻳﻢ‪.‬‬

‫ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺗﻚ ﭼﺮﺧﻪ ﺍﻱ ﻛﻪ ﻣﻔﺎﻫﻴﻢ ﺁﻥ ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﻣﻮﺭﺩ ﺑﺤﺚ ﻗﺮﺍﺭ ﻣﻲ ﮔﻴﺮﺩ ﺑﺎﻳﺪ‬
‫ﺣﺎﻓﻈﻪ ﺩﺍﺩﻩ ﻭ ﺣﺎﻓﻈﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺟﺪﺍﮔﺎﻧﻪ ﺍﻱ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ ﺯﻳﺮﺍ‪:‬‬

‫‪ -1‬ﻗﺎﻟﺐ ﺩﺍﺩﻩ ﻭ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﺩﺭ‪ MIPS‬ﻣﺘﻔﺎﻭﺕ ﺍﺳﺖ ﻭ ﺍﺯ ﺍﻳﻦ ﺭﻭ ﺣﺎﻓﻈﻪ ﻫﺎﻱ ﻣﺨﺘﻠﻔﻲ‬
‫ﻣﻮﺭﺩ ﻧﻴﺎﺯ ﺍﺳﺖ‪.‬‬

‫‪ -2‬ﺩﺍﺷﺘﻦ ﺣﺎﻓﻈﻪ ﻫﺎﻱ ﻣﺨﺘﻠﻒ ﺍﺭﺯﺍﻥ ﺗﺮ ﺍﺳﺖ‪.‬‬

‫‪-3‬ﭘﺮﺩﺍﺯﻧﺪﻩ ﺩﺭ ﻳﻚ ﭼﺮﺧﻪ ﻋﻤﻞ ﻣﻲ ﻛﻨﺪ ﻭ ﻧﻤﻲ ﺗﻮﺍﻧﺪ ﺍﺯ ﻳﻚ ﺣﺎﻓﻈﻪ ‪single-ported‬‬

‫ﺑﺮﺍﻱ ‪ 2‬ﺩﺳﺘﻴﺎﺑﻲ ﻣﺨﺘﻠﻒ ﺩﺭ ﻳﻚ ﭼﺮﺧﻪ ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﺪ‪.‬‬
‫‪15‬‬ ‫‪Advanced Computer Architecture & Design‬‬
‫‪Science & Research Branch‬‬
 ‫ﻗﻮﺍﻋﺪ ﻃﺮﺍﺣﯽ ﻣﻨﻄﻘﯽ‬
‫• ﺑﺮﺍی ﺑﺤﺚ ﺭﻭی ﻃﺮﺍﺣﯽ ﻣﺎﺷﻴﻦ ﺍﺑﺘﺪﺍ ﺑﺎﻳﺪ ﺗﺼﻤﻴﻢ ﺑﮕﻴﺮﻳﻢ ﮐﻪ‬
‫ﻣﺪﺍﺭ ﻣﻨﻄﻘﯽ ﻣﺮﺑﻮﻃﻪ ﭼﮕﻮﻧﻪ ﻋﻤﻞ ﻣﯽ ﮐﻨﺪ ﻭ ﺑﻪ ﻣﺎﺷﻴﻦ‬
‫ﭼﮕﻮﻧﻪ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺍﻋﻤﺎﻝ ﻣﯽ ﺷﻮﺩ؟‬

‫• ﻭﺍﺣﺪ ﻫﺎی ﻋﻤﻠﮑﺮﺩی ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯی‪ MIPS‬ﺍﺯ ‪ 2‬ﻧﻮﻉ‬

‫ﻋﻨﺼﺮ ﻣﻨﻄﻘﯽ ﻣﺘﻔﺎﻭﺕ ﺗﺸﮑﻴﻞ ﻣﯽ ﺷﻮﻧﺪ‪:‬‬
‫‪ ‬ﻋﻨﺎﺻﺮی ﮐﻪ ﺭﻭی ﻣﻘﺎﺩﻳﺮ ﺩﺍﺩﻩ ﻫﺎ ﻋﻤﻞ ﻣﯽ ﮐﻨﻨﺪ‬
‫‪ ‬ﻋﻨﺎﺻﺮی ﮐﻪ ﺣﺎﻭی ﺣﺎﻟﺖ ﻫﺴﺘﻨﺪ‪.‬‬
‫‪Advanced Computer Architecture & Design‬‬
‫‪16‬‬
‫‪Science & Research Branch‬‬
 ‫ﻋﻨﺎﺻﺮی ﮐﻪ ﺭﻭی ﻣﻘﺎﺩﻳﺮ ﺩﺍﺩﻩ ﻫﺎ ﻋﻤﻞ ﻣﯽ ﮐﻨﻨﺪ‪:‬‬
‫ﻫﻤﮕﯽ ﺗﺮﮐﻴﺒﯽ ﻫﺴﺘﻨﺪ ﻳﻌﻨﯽ ﺧﺮﻭﺟﯽ ﻫﺎ ﺗﻨﻬﺎ ﺑﻪ ﻭﺭﻭﺩی ﻫﺎی‬
‫ﻓﻌﻠﯽ ﺑﺴﺘﮕﯽ ﺩﺍﺭﻧﺪ‪.‬‬
‫ﭼﻨﺎﻧﭽﻪ ﻣﺠﻤﻮﻋﻪ ﻣﻔﺮﻭﺽ ﻭ ﻳﮑﺴﺎﻧﯽ ﺍﺯ ﻭﺭﻭﺩی ﻫﺎ ﺭﺍ ﺑﻪ ﺁﻥ‬
‫ﺍﻋﻤﺎﻝ ﮐﻨﻴﻢ ﺧﺮﻭﺟﯽ ﻫﻤﻮﺍﺭﻩ ﻳﮑﺴﺎﻥ ﺧﻮﺍﻫﺪ ﺑﻮﺩ ﺯﻳﺮﺍ ﺩﺍﺭﺍی‬
‫ﻫﻴﭻ ﺫﺧﻴﺮﻩ ﺳﺎﺯی ﺩﺭﻭﻧﯽ ﻧﻴﺴﺖ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

‫‪17‬‬
‫‪Science & Research Branch‬‬
 ‫ﻋﻨﺎﺻﺮی ﮐﻪ ﺣﺎﻭی ﺣﺎﻟﺖ ﻫﺴﺘﻨﺪ‪:‬‬
‫ﻋﻨﺼﺮی ﺩﺍﺭﺍی ﺣﺎﻟﺖ ﺍﺳﺖ ﮐﻪ ﺩﺍﺭﺍی ﻧﻮﻋﯽ ﺫﺧﻴﺮﻩ ﺳﺎﺯی‬
‫ﺩﺭﻭﻧﯽ ﺑﺎﺷﺪ‪.‬ﺍﮔﺮ ﺗﻐﺬﻳﻪ ﻣﺎﺷﻴﻦ ﺭﺍ ﻗﻄﻊ ﮐﻨﻴﻢ ﻣﯽ ﺗﻮﺍﻥ ﺩﻭﺑﺎﺭﻩ‬
‫ﻣﻘﺎﺩﻳﺮ ﺍﻳﻦ ﻋﻨﺎﺻﺮ ﭘﻴﺶ ﺍﺯ ﻗﻄﻊ ﺗﻐﺬﻳﻪ ﺭﺍ ﺩﺭ ﺁﻧﻬﺎ ﺑﺎﺭ ﮐﺮﺩ ﻭ‬
‫ﻣﺎﺷﻴﻦ ﺭﺍ ﺩﻭﺑﺎﺭﻩ ﺭﺍﻩ ﺍﻧﺪﺍﺯی ﮐﺮﺩ‪.‬ﻫﻤﭽﻨﻴﻦ ﺍﮔﺮ ﻋﻨﺎﺻﺮ‬
‫ﺣﺎﻟﺖ ﺭﺍ ﺫﺧﻴﺮﻩ ﻣﯽ ﮐﺮﺩﻳﻢ ﻭ ﺁﻥ ﻫﺎ ﺭﺍ ﺑﺎﺯﻳﺎﺑﯽ ﻣﯽ ﮐﺮﺩﻳﻢ‬
‫ﺍﻧﮕﺎﺭ ﺗﻐﺬﻳﻪ ﻣﺎﺷﻴﻦ ﺍﺻﻼ ﻗﻄﻊ ﻧﺸﺪﻩ ﺍﺳﺖ‪.‬ﺑﺪﻳﻦ ﺗﺮﺗﻴﺐ ﺍﻳﻦ‬
‫ﻋﻨﺎﺻﺮ ﻣﺸﺨﺼﻪ ﻣﺎﺷﻴﻦ ﺭﺍ ﺗﻌﻴﻴﻦ ﻣﯽ ﮐﻨﻨﺪ‪.‬‬
‫ﻳﮏ ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﺣﺪﺍﻗﻞ ‪ 2‬ﻭﺭﻭﺩی ﻭ ﻳﮏ ﺧﺮﻭﺟﯽ ﺩﺍﺭﺩ‪.‬‬
‫ﻣﻘﺪﺍﺭی ﮐﻪ ﺩﺭ ﭼﺮﺧﻪ ﺳﺎﻋﺖ‬
‫ﻭﺭﻭﺩی ﺳﺎﻋﺖ ﮐﻪ ﺗﻌﻴﻴﻦ ﻣﯽ‬ ‫ﻣﻘﺪﺍﺭ ﺩﺍﺩﻩ ﺍی ﮐﻪ ﻗﺮﺍﺭ ﺍﺳﺖ‬
‫ﻗﺒﻠﯽ ﺩﺭﻭﻥ ﻋﻨﺼﺮ ﻧﻮﺷﺘﻪ‬
‫ﮐﻨﺪ ﻣﻘﺪﺍﺭ ﺩﺍﺩﻩ ﭼﻪ ﻫﻨﮕﺎﻡ ﺩﺭ‬ ‫ﺩﺭ ﻋﻨﺼﺮ ﻧﻮﺷﺘﻪ ﺷﻮﺩ‬
‫ﺷﺪﻩ ﺍﺳﺖ‬
‫ﻋﻨﺼﺮ ﻧﻮﺷﺘﻪ ﺷﻮﺩ‬
‫‪18‬‬ ‫‪Advanced Computer Architecture & Design‬‬
‫‪Science & Research Branch‬‬
 ‫• ﺑﻪ ﻃﻮﺭ ﻣﺜﺎﻝ ﻓﻠﻴﭗ ﻓﻼپ ‪ D‬ﻳﻚ ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﺍﺳﺖ ﻛﻪ ﺍﺯ ﻟﺤﺎﻅ ﻣﻨﻄﻘﻲ ﺑﺴﻴﺎﺭ ﺳﺎﺩﻩ‬
‫ﺍﺳﺖ‪.‬ﺩﻗﻴﻘﺎ ﺩﺍﺭﺍﻱ ‪ 2‬ﻭﺭﻭﺩﻱ ﻣﻘﺪﺍﺭ ﻭ ﺳﺎﻋﺖ ﻭ ﻳﻚ ﺧﺮﻭﺟﻲ ﺍﺳﺖ‪.‬‬
‫• ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ‪ MIPS‬ﻋﻼﻭﻩ ﺑﺮ ﻓﻠﻴﭗ ﻓﻼپ ﻫﺎ ﺍﺯ ‪ 2‬ﻧﻮﻉ ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﺩﻳﮕﺮ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲ‬
‫ﺷﻮﺩ‪:‬‬
‫‪ ‬ﺣﺎﻓﻈﻪ ﻫﺎ‬
‫‪ ‬ﺭﺟﻴﺴﺘﺮﻫﺎ‬
‫• ﻗﻄﻌﺎﺕ ﻣﻨﻄﻘﻲ ﻛﻪ ﺣﺎﻭﻱ ﺣﺎﻟﺖ ﻫﺴﺘﻨﺪ ﺗﺮﺗﻴﺒﻲ ﻧﻴﺰ ﻧﺎﻣﻴﺪﻩ ﻣﻲ ﺷﻮﻧﺪ‪.‬ﭼﺮﺍ ﻛﻪ ﺧﺮﻭﺟﻲ‬
‫ﻫﺎﻱ ﺍﻳﻦ ﻗﻄﻌﺎﺕ ﻫﻢ ﺑﻪ ﻭﺭﻭﺩﻱ ﻫﺎﻱ ﺁﻥ ﻫﺎ ﻭ ﻫﻢ ﺑﻪ ﻣﺤﺘﻮﺍﻱ ﺣﺎﻟﺖ ﺩﺭﻭﻧﻲ ﺁﻧﻬﺎ ﺑﺴﺘﮕﻲ‬
‫ﺩﺍﺭﺩ‪ .‬ﻣﺎﻧﻨﺪ ﺧﺮﻭﺟﻲ ﻭﺍﺣﺪ ﻋﻤﻠﻴﺎﺗﻲ ﻛﻪ ﻧﻤﺎﻳﺎﻧﮕﺮ ﺭﺟﻴﺴﺘﺮﻫﺎﺳﺖ ﻫﻢ ﺑﻪ ﺷﻤﺎﺭﻩ ﻓﺮﺍﻫﻢ‬
‫ﺷﺪﻩ ﺑﺴﺘﮕﻲ ﺩﺍﺭﺩ ﻭ ﻫﻢ ﺑﻪ ﻧﻮﺷﺘﻪ ﭘﻴﺸﻴﻦ ﺭﺟﻴﺴﺘﺮﻫﺎ‬

‫‪Advanced Computer Architecture & Design‬‬

‫‪19‬‬
‫‪Science & Research Branch‬‬
 ‫ﺭﻭﺵ ﺳﺎﻋﺖ ﺯﻧﯽ‬
‫• ﺍﻳﻦ ﺭﻭﺵ ﻣﺸﺨﺺ ﻣﯽ ﮐﻨﺪ ﮐﻪ ﭼﻪ ﻫﻨﮕﺎﻡ ﻣﯽ ﺗﻮﺍﻥ ﺳﻴﮕﻨﺎﻝ‬
‫ﻫﺎ ﺭﺍ ﺧﻮﺍﻧﺪ ﻭ ﭼﻪ ﻫﻨﮕﺎﻡ ﻣﯽ ﺗﻮﺍﻥ ﺁﻧﻬﺎ ﺭﺍ ﻧﻮﺷﺖ‪.‬‬
‫• ﺗﻌﻴﻴﻦ ﺯﻣﺎﻧﺒﻨﺪی ﺧﻮﺍﻧﺪﻥ ﻭ ﻧﻮﺷﺘﻦ ﻣﻬﻢ ﺍﺳﺖ‪.‬‬

‫ﺍﮔﺮ ﺳﻴﮕﻨﺎﻟﯽ ﺩﺭ ﻫﻤﺎﻥ ﺯﻣﺎﻥ ﮐﻪ ﻧﻮﺷﺘﻪ‬

‫ﻣﯽ ﺷﻮﺩ ﺧﻮﺍﻧﺪﻩ ﻫﻢ ﺷﻮﺩ ﻣﯽ ﺗﻮﺍﻧﺪ‬
‫ﻫﻤﺎﻥ ﻣﻘﺪﺍﺭ ﻗﺒﻠﯽ ﻣﻘﺪﺍﺭ ﺟﺪﻳﺪ ﻧﻮﺷﺘﻪ‬
‫ﺷﻮﺩ ﻭ ﻳﺎ ﺗﺮﮐﻴﺒﯽ ﺍﺯ ﻫﺮ ‪ 2‬ﺑﺎﺷﺪ ﮐﻪ ﺩﺭ‬
‫ﮐﺎﺭ ﻣﺎﺷﻴﻦ ﺧﻠﻞ ﺍﻳﺠﺎﺩ ﻣﯽ ﮐﻨﺪ‬

‫‪Advanced Computer Architecture & Design‬‬

‫‪20‬‬
‫‪Science & Research Branch‬‬
 ‫• ﺑﺮﺍﻱ ﺳﺎﺩﮔﻲ ﺭﻭﺵ ﺳﺎﻋﺖ ﺯﻧﻲ ﺣﺴﺎﺱ ﺑﻪ ﻟﺒﻪ ﺭﺍ ﺩﺭ ﻧﻈﺮ ﻣﻲ‬
‫ﮔﻴﺮﻳﻢ‪.‬ﭘﺲ ﻣﻘﺎﺩﻳﺮ ﺫﺧﻴﺮﻩ ﺷﺪﻩ ﻓﻘﻂ ﺩﺭ ﻟﺒﻪ ﺳﺎﻋﺖ ﺗﻐﻴﻴﺮ ﻣﻲ‬
‫ﻛﻨﺪ‪.‬‬
‫• ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﻓﻘﻂ ﻋﻨﺎﺻﺮ ﺣﺎﻟﺖ ﻣﻲ ﺗﻮﺍﻧﻨﺪ ﻣﻘﺪﺍﺭ ﺩﺍﺩﻩ ﺭﺍ ﺫﺧﻴﺮﻩ‬
‫ﻛﻨﻨﺪ ﻭﺭﻭﺩﻱ ﻫﺮ ﻣﺠﻤﻮﻋﻪ ﺍﺯ ﻋﻨﺎﺻﺮ ﺗﺮﻛﻴﺒﻲ ﺍﺯ ﻣﺪﺍﺭﺍﺕ ﺗﺮﺗﻴﺒﻲ‬
‫ﮔﺮﻓﺘﻪ ﻣﻲ ﺷﻮﺩ ﻭ ﺧﺮﻭﺟﻲ ﻫﺎﻱ ﺁﻥ ﺩﺭ ﻣﺠﻤﻮﻋﻪ ﺍﻱ ﺍﺯ ﻋﻨﺎﺻﺮ‬
‫ﺣﺎﻟﺖ ﺫﺧﻴﺮﻩ ﻣﻲ ﺷﻮﺩ‪.‬‬

‫ﺧﺮﻭﺟﯽ ﻫﺎ ﻣﻘﺎﺩﻳﺮی‬ ‫ﻭﺭﻭﺩی ﻫﺎ ﻣﻘﺎﺩﻳﺮی‬

‫ﻫﺴﺘﻨﺪ ﮐﻪ ﻣﯽ ﺗﻮﺍﻧﻨﺪ‬ ‫ﻫﺴﺘﻨﺪ ﮐﻪ ﺩﺭ ﭼﺮﺧﻪ‬
‫ﺩﺭ ﭼﺮﺧﻪ ﺳﺎﻋﺖ‬ ‫ﺳﺎﻋﺖ ﻗﺒﻠﯽ ﻧﻮﺷﺘﻪ‬
‫ﺑﻌﺪی ﺍﺳﺘﻔﺎﺩﻩ ﺷﻮﻧﺪ‬ ‫ﺷﺪﻩ ﺍﻧﺪ‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 ‫‪ 2‬ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﻭ ﻣﺠﻤﻮﻋﻪ ﺍی ﺍﺯ ﻣﻨﻄﻖ ﺗﺮﮐﻴﺒﯽ‬
‫ﺩﺭ ﻳﮏ ﭼﺮﺧﻪ ﺳﺎﻋﺖ‬
‫• ﺩﺭ ﻳﻚ ﺳﻴﺴﺘﻢ ﺩﻳﺠﻴﺘﺎﻝ ﻫﻤﮕﺎﻡ ‪،‬ﭘﺎﻟﺲ ﺳﺎﻋﺖ‪،‬ﺯﻣﺎﻧﻲ ﺭﺍ ﻛﻪ ﻋﻨﺎﺻﺮ ﺣﺎﻟﺖ ﺩﺍﺭ‬
‫ﺩﺭ ﻋﻨﺼﺮ ﺫﺧﻴﺮﻩ ﺳﺎﺯﻱ ﺩﺍﺧﻠﻲ ﻣﻘﺪﺍﺭﻱ ﻣﻲ ﻧﻮﻳﺴﻨﺪ ﺭﺍ ﺗﻌﻴﻴﻦ ﻣﻲ ﻛﻨﺪ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 ‫ﺭﻭﺵ ﺣﺴﺎﺱ ﺑﻪ ﻟﺒﻪ‬
‫• ﺭﻭﺵ ﺣﺴﺎﺱ ﺑﻪ ﻟﺒﻪ ﺍﺟﺎﺯﻩء ﺧﻮﺍﻧﺪﻥ ﻣﺤﺘﻮﻳﺎﺕ ﻳﻚ ﺭﺟﻴﺴﺘﺮ‪ ،‬ﻓﺮﺳﺘﺎﺩﻥ ﺍﻳﻦ‬
‫ﻣﻘﺪﺍﺭ ﺑﻪ ﻣﻨﻄﻖ ﺗﺮﻛﻴﺒﻲ ﻭ ﻧﻮﺷﺘﻦ ﺩﺭ ﺁﻥ ﺭﺟﻴﺴﺘﺮ ﺭﺍ ﺩﺭ ﻳﻚ ﭼﺮﺧﻪ ﺳﺎﻋﺖ‬
‫ﺍﻧﺠﺎﻡ ﻣﻲ ﺩﻫﺪ‪ .‬ﻳﻌﻨﻲ ﻣﻲ ﺗﻮﺍﻥ ﺍﺯ ﻳﻚ ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﺧﻮﺍﻧﺪ ﻭ ﺩﺭ ﺁﻥ ﻧﻮﺷﺖ‬
‫ﺑﺪﻭﻥ ﺁﻧﻜﻪ ﺑﻴﻦ ﺁﻧﻬﺎ ﺭﻗﺎﺑﺘﻲ ﺑﻪ ﻭﺟﻮﺩ ﺁﻳﺪ ﻛﻪ ﻣﻨﺠﺮ ﺑﻪ ﻣﻘﺎﺩﻳﺮ ﺩﺍﺩﻩ‬
‫ﻧﺎﻣﺸﺨﺺ ﺷﻮﺩ‪.‬‬

‫• ﺑﺎﻻﺭﻭﻧﺪﻩ ﻭ ﭘﺎﻳﻴﻦ ﺭﻭﻧﺪﻩ ﻓﺮﻗﻲ ﻧﻤﻲ ﻛﻨﺪ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪Science & Research Branch‬‬
 ‫ﻧﮑﺘﻪ‬

‫• ﺩﺭ ﺑﻌﻀﯽ ﺟﺎﻫﺎ ﺑﺎ ﺗﺮﮐﻴﺐ ﭼﻨﺪ ﮔﺬﺭﮔﺎﻩ )‪ (Bus‬ﻳﮏ ﮔﺬﺭﮔﺎﻩ‬

‫ﭘﻬﻦ ﺗﺮ ﺑﺪﺳﺖ ﻣﯽ ﺁﻳﺪ‪.‬ﻣﺜﻼ ﺗﺮﮐﻴﺐ ‪ 2‬ﮔﺬﺭﮔﺎﻩ ‪ 16‬ﺑﻴﺘﯽ ﻳﮏ‬
‫ﮔﺬﺭﮔﺎﻩ ‪ 32‬ﺑﻴﺘﯽ ﺍﻳﺠﺎﺩ ﻣﯽ ﮐﻨﺪ‪.‬‬

‫‪Advanced Computer Architecture & Design‬‬

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‫‪ 2‬ﻋﻨﺼﺮ ﺣﺎﻟﺖ ﺑﺮﺍﻱ ﺫﺧﻴﺮﻩ ﻭ ﺩﺳﺘﺮﺳﻲ ﺑﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﻭ‬
‫ﻳﻚ ﺟﻤﻊ ﻛﻨﻨﺪﻩ ﺑﺮﺍﻱ ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﻌﺪﻱ‬

‫‪State Element‬‬

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 ‫ﻣﺮﺍﺣﻞ ﻃﺮﺍﺣﯽ ﻳﮏ ﭘﺮﺩﺍﺯﻧﺪﻩ‬
‫ﺑﺎ ﺁﻧﺎﻟﻴﺰ ﻣﺠﻤﻮﻋﻪ ﺩﺳﺘﻮﺭﺍﺕ ﻧﻴﺎﺯﻣﻨﺪﻳﻬﺎی ‪ Data Path‬ﺭﺍ‬ ‫•‬
‫ﻣﺸﺨﺺ ﻣﯽ ﮐﻨﻴﻢ‬
‫ﺍﺟﺰﺍ ‪ Data Path‬ﻭ ﺭﻭﺵ ‪ Clocking‬ﺭﺍ ﺍﻧﺘﺨﺎﺏ ﻣﻴﮑﻨﻴﻢ‬ ‫•‬
‫ﺍﺟﺰﺍ ‪ Data Path‬ﺭﺍ ﺩﺭ ﮐﻨﺎﺭ ﻫﻢ ﻗﺮﺍﺭ ﻣﯽ ﺩﻫﻴﻢ‬ ‫•‬
‫ﺑﺎ ﺁﻧﺎﻟﻴﺰ ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻧﻘﺎﻁ ﮐﻨﺘﺮﻟﯽ ﺭﺍ ﮐﻪ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺭﺍ‬ ‫•‬
‫ﺗﺤﺖ ﺗﺎﺛﻴﺮ ﻗﺮﺍﺭ ﻣﯽ ﺩﻫﻨﺪ ﺭﺍ ﻣﺸﺨﺺ ﻣﯽ ﮐﻨﻴﻢ‬
‫ﻣﻨﻄﻖ ‪Control‬ﺭﺍ ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﻣﻴﮑﻨﻴﻢ‬ ‫•‬

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 Data Path & Control path
‫ ﻣﺴﻴﺮی ﺍﺳﺖ ﮐﻪ ﻣﺸﺨﺺ ﻣﻴﮑﻨﺪ ﺩﺍﺩﻩ ﻫﺎ ﭼﮕﻮﻧﻪ ﺑﻴﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ‬Data path •
:‫ ﺍﺟﺰﺍی ﺁﻥ ﻋﺒﺎﺭﺗﻨﺪ ﺍﺯ‬.‫ﻭ ﺳﺎﻳﺮ ﺍﻟﻤﺎﻧﻬﺎی ﺍﺻﻠﯽ ﺭﺩ ﻭ ﺑﺪﻝ ﻣﻴﺸﻮﺩ‬

combinational elements –
state (sequential) elements –

‫ ﻣﺸﺨﺺ ﻣﯽ ﮐﻨﺪ ﮐﻪ ﺳﻴﮕﻨﺎﻟﻬﺎی ﮐﻨﺘﺮﻟﯽ ﻭ‬Control path •

.‫ ﻣﻴﺮﺳﺪ‬Data Path ‫ ﭼﮕﻮﻧﻪ ﺑﻪ ﺍﻟﻤﺎﻧﻬﺎی‬،‫ﺯﻣﺎﻧﺒﻨﺪی‬
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 ‫ﺍﺟﺰﺍی ﻣﻮﺭﺩ ﻧﻴﺎﺯ ﺑﺮﺍی ﻃﺮﺍﺣﯽ ﻣﺴﻴﺮ ﺩﺍﺩﻩ‬
Program counter •
Instruction memory •
Data memory •
Register file •
ALU •

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 RAMemWrite

RAMemRead

RARegWrite
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 CarryIn
A
Adder • 32

Adder
Sum
32
B Carry
32

Selec
t
MUX • A
32
MUX

Y
32
B
32

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 ‫ﭘﻴﺶ ﻧﻴﺎﺯﻫﺎی ﻃﺮﺍﺣﯽ ﻣﺴﻴﺮ ﺩﺍﺩﻩ‬

‫–ﻭﺍﮐﺸﯽ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬
‫–ﮐﺪﺑﺮﺩﺍﺭی ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﻭ ﺧﻮﺍﻧﺪﻥ ﻋﻤﻠﻮﻧﺪﻫﺎ‬
‫–ﻣﺤﺎﺳﺒﻪ ﮐﺮﺩﻥ ﻋﻤﻞ‬
‫–ﺑﺎﺯﻧﻮﻳﺴﯽ ﻧﺘﻴﺠﻪ‬

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 ‫ﺳﺎﺧﺖ ﻳﮏ ﻣﺴﻴﺮ ﺩﺍﺩﻩ‬

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 The MIPS Instructions
31 26 21 16 11 6 0
R-type • op rs rt rd shamt funct
add rd, rs, rt – 6 bits 5 bits 5 bits 5 bits
Read registers rs and rt
5 bits
.1
6 bits

sub, and, or, slt – Feed them to ALU .2

Update register file .3
31 26 21 16 0
LOAD and STORE • op rs rt immediate
lw rt, rs, imm – 6 bits 5 bits 5 bits 16 bits
Read register rs (and rt for store) .1
sw rt, rs, imm – Feed rs and immed to ALU .2
Move data between mem and reg .3

31 26 21 16 0
BRANCH: •
op rs rt displacement
beq rs, rt, imm – 6 bits 5 bits 5 bits 16 bits
Read registers rs and rt .1
Feed to ALU to compare .2
Add PC to disp; update PC .3
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 ‫ﺩﺭ ﺍﻳﻨﺠﺎ ﺩﺭﺑﺎﺭﻩ ‪ R-format‬ﺻﺤﺒﺖ ﻣﯽ ﮐﻨﻴﻢ‪:‬‬
‫• ﺍﻳﻦ ﺷﻜﻞ ﻧﺸﺎﻥ ﻣﻲ ﺩﻫﺪ ﻛﻪ ﭼﮕﻮﻧﻪ ﺍﻳﻦ ﺳﻪ ﻋﻨﺼﺮ ﺑﺎ ﻫﻢ ﺗﺮﻛﻴﺐ ﻣﻲ ﺷﻮﻧﺪ ﺗﺎ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺍﻱ ﺭﺍ‬
‫ﺗﺸﻜﻴﻞ ﺩﻫﻨﺪ ﻛﻪ ﻭﻇﻴﻔﻪ ﺑﺮﺩﺍﺷﺖ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﻭ ﺍﻓﺰﺍﻳﺶ ‪ PC‬ﺑﺮﺍﻱ ﺑﻪ ﺩﺳﺖ ﺁﻭﺭﺩﻥ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺗﺮﺗﻴﺒﻲ ﺑﻌﺪﻱ ﺭﺍ ﺑﻪ ﺍﻧﺠﺎﻡ ﻣﻲ ﺭﺳﺎﻧﺪ‪.‬‬

‫• ﺗﻤﺎﻡ ﺍﻳﻦ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ‪ 2 ،‬ﺭﺟﻴﺴﺘﺮ ﺭﺍ ﻣﻲ ﺧﻮﺍﻧﻨﺪ‪،‬ﻳﻚ ﻋﻤﻞ ‪ ALU‬ﺭﺍ ﺑﺮ ﺭﻭﻱ ﻣﺤﺘﻮﻳﺎﺕ ﺍﻳﻦ‬
‫‪ 2‬ﺭﺟﻴﺴﺘﺮ ﺍﻧﺠﺎﻡ ﻣﻲ ﺩﻫﻨﺪ ﻭ ﻧﺘﻴﺠﻪ ﺭﺍ ﻣﻲ ﻧﻮﻳﺴﻨﺪ‪.‬‬

‫• ﺭﺟﻴﺴﺘﺮﻫﺎﻱ ﻫﻤﻪ ﻣﻨﻈﻮﺭﻩ ‪ 32‬ﺑﻴﺘﻲ ﺩﺭ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﺫﺧﻴﺮﻩ ﻣﻲ ﺷﻮﺩ‪.‬‬

‫• ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎﻱ ﺑﺎ ﻗﺎﻟﺐ ‪ 3 ،R‬ﺭﺟﻴﺴﺘﺮ ﻋﻤﻠﻮﻧﺪ ﺩﺍﺭﻧﺪ‪ ،‬ﺑﺮﺍﻱ ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

‫ﺍﺣﺘﻴﺎﺝ ﺑﻪ ﺧﻮﺍﻧﺪﻥ ‪ 2‬ﻛﻠﻤﻪ ﺩﺍﺩﻩ ﺍﺯ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﻭ ﻧﻮﺷﺘﻦ ﻳﻚ ﻛﻠﻤﻪ ﺩﺍﺩﻩ ﺩﺭ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ‬
‫ﻣﻲ ﺑﺎﺷﺪ ﻛﻪ ﺩﺍﺭﺍﻱ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟﻲ ﻣﻲ ﺑﺎﺷﺪ‪.‬‬

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 ‫‪R-Type Instruction‬‬
‫‪6‬‬ ‫‪5‬‬ ‫‪5‬‬ ‫‪5‬‬ ‫‪5‬‬ ‫‪6‬‬
‫‪opcode‬‬ ‫‪rs‬‬ ‫‪rt‬‬ ‫‪rd shamt‬‬ ‫‪func‬‬
‫‪R-Type Format‬‬ ‫ﺑﺮﺍی ﺩﺳﺘﻮﺭﺍﺕ ﻣﺤﺎﺳﺒﺎﺗﯽ ﻭ ﻣﻨﻄﻘﯽ‬ ‫•‬
‫ﮐﻪ ﺗﻮﺳﻂ ﺍﻳﻦ ﻓﺮﻣﺖ ﻧﺸﺎﻥ ﺩﺍﺩﻩ‬
‫ﻣﻴﺸﻮﻧﺪ ﻻﺯﻡ ﺍﺳﺖ ﺗﺎ ﺩﻭ ﺭﺟﻴﺴﺘﺮ ﺍﺯ‬
‫ﺭﺟﻴﺴﺘﺮ ﻓﺎﻳﻞ ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﻭ ﺩﺍﺩﻩ ﺁﻧﻬﺎ‬
‫‪ALUop‬‬ ‫ﺑﻪ ‪ ALU‬ﻣﻨﺘﻘﻞ ﺷﻮﺩ‪.‬‬
‫ﻋﻤﻞ ‪ ALU‬ﺑﺮ ﺍﺳﺎﺱ ﻧﻮﻉ ﺩﺳﺘﻮﺭ‬ ‫•‬
‫‪5‬‬ ‫‪Read reg 1‬‬ ‫‪Read‬‬ ‫ﺗﻌﻴﻴﻦ ﺷﺪﻩ ﻭ ﺑﺮ ﺭﻭی ﻣﺤﺘﻮی‬
‫‪Instruction‬‬ ‫‪5‬‬
‫‪data 1‬‬
‫‪zero‬‬ ‫ﺭﺟﻴﺴﺘﺮﻫﺎ ﺍﻧﺠﺎﻡ ﻣﻴﺸﻮﺩ‪.‬‬
‫‪Read reg 2‬‬ ‫‪ALU‬‬
‫‪Register‬‬ ‫‪ALU‬‬
‫‪5‬‬
‫‪Write reg File‬‬ ‫ﻧﺘﻴﺠﻪ ﺩﺭ ﺭﺟﻴﺴﺘﺮ ﻣﻘﺼﺪ ﻧﻮﺷﺘﻪ‬ ‫•‬
‫‪Write data‬‬ ‫‪Read‬‬ ‫ﻣﻴﺸﻮﺩ‪.‬‬
‫‪data 2‬‬
‫ﺳﻴﮕﻨﺎﻟﻬﺎی ﮐﻨﺘﺮﻟﯽ ﺑﺎﻳﺪ ﺍﻳﺠﺎﺩ ﺷﻮﺩ ﺗﺎ‬ ‫•‬
‫ﻧﺘﻴﺠﻪ ﺩﺭ ﻟﺒﻪ ﮐﻼک ﺩﺭ ﺭﺟﻴﺴﺘﺮ‬
‫‪RegWrite‬‬
‫ﻣﻘﺼﺪ ﻧﻮﺷﺘﻪ ﺷﻮﺩ‪ .‬ﻫﻤﭽﻨﻴﻦ ﺳﻴﮕﻨﺎﻝ‬
‫‪ ALUop‬ﺑﺎﻳﺪ ﺗﻮﻟﻴﺪ ﺷﻮﺩ ﺗﺎ ﻋﻤﻞ‬
‫‪ ALU‬ﺭﺍ ﺗﻌﻴﻴﻦ ﮐﻨﺪ‪.‬‬
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 ‫ﺍﺩﻏﺎﻡ ﺑﺎ ﻣﺮﺣﻠﻪ ﺍﺟﺮﺍ‬:‫ﻣﺮﺣﻠﻪ ﭼﻬﺎﺭﻡ‬

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 I-Type Instruction: load/store
6 5 5 16
I-Type opcode rs rt immediate ‫• ﺑﺮﺍی ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﺑﺎﻳﺪ‬
‫ ﺑﻴﺘﯽ‬16 ‫ﻣﻘﺪﺍﺭ ﺁﻓﺴﺖ‬
‫ﻣﻮﺟﻮﺩ ﺩﺭ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬
‫ﺑﺼﻮﺭﺕ ﻳﮏ ﻋﺪﺩ ﻋﻼﻣﺖ‬
16 sign
extend
32
‫ ﺑﻴﺘﯽ ﺗﺒﺪﻳﻞ ﺷﺪﻩ ﻭﺑﺎ‬32 ‫ﺩﺍﺭ‬
rs ‫ﻣﻘﺪﺍﺭ ﭘﺎﻳﻪ ﻣﻮﺟﻮﺩ ﺩﺭ‬
.‫ﺟﻤﻊ ﺷﻮﺩ‬

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 ‫ﮔﺴﺘﺮﺵ ﻋﻼﻣﺖ‬
‫• ﺑﺎ ﻋﻼﻣﺖ ﻳﺎ ﺑﯽ ﻋﻼﻣﺖ ﺑﻮﺩﻥ ﻋﻼﻭﻩ ﺑﺮ ﻋﻤﻠﻴﺎﺕ ﺣﺴﺎﺑﯽ ﺑﻪ‬
‫ﻋﻤﻠﻴﺎﺕ ﺑﺎﺭ ﮐﺮﺩﻥ ﻧﻴﺰ ﺍﻋﻤﺎﻝ ﻣﯽ ﺷﻮﺩ‪.‬ﻭﻇﻴﻔﻪ ﻳﮏ ﺑﺎﺭ ﮐﺮﺩﻥ‬
‫ﺑﺎ ﻋﻼﻣﺖ‪،‬ﮐﭙﯽ ﮐﺮﺩﻥ ﻋﻼﻣﺖ ﺑﻪ ﻃﻮﺭ ﺗﮑﺮﺍﺭی ﺑﺮﺍی ﭘﺮ‬
‫ﮐﺮﺩﻥ ﺑﻘﻴﻪ ﺭﺟﻴﺴﺘﺮ ﺍﺳﺖ ﮐﻪ ﮔﺴﺘﺮﺵ ﻋﻼﻣﺖ ﻧﺎﻣﻴﺪﻩ ﻣﯽ‬
‫ﺷﻮﺩ‪.‬‬
‫• ﻫﺪﻑ ﺁﻥ ﻗﺮﺍﺭ ﺩﺍﺩﻥ ﻧﻤﺎﻳﺶ ﺩﺭﺳﺖ ﻋﺪﺩ ﺩﺭ ﺁﻥ ﺭﺟﻴﺴﺘﺮ‬
‫ﺍﺳﺖ‪.‬ﺩﺭ ﺑﺎﺭ ﮐﺮﺩﻥ ﺑﯽ ﻋﻼﻣﺖ‪،‬ﺳﻤﺖ ﭼﭗ ﺩﺍﺩﻩ‪،‬ﺑﻪ ﺳﺎﺩﮔﯽ ﺑﺎ‬
‫ﺻﻔﺮﻫﺎ ﭘﺮ ﻣﯽ ﺷﻮﺩ‪.‬‬

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‫• ﺣﺎﻝ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی ﺑﺎﺭ ﮐﺮﺩﻥ ﻭ ﺫﺧﻴﺮﻩ ﮐﺮﺩﻥ ﮐﻠﻤﻪ ﺭﺍ ﺩﺭ‬
‫ﻧﻈﺮ ﺑﮕﻴﺮﻳﺪ‪:‬‬

‫)‪Lw $t1, offset-value($t2‬‬ ‫ﻣﻘﺪﺍﺭ ﺭﺍ ﺩﺭ ‪ RF‬ﻣﯽ ﻧﻮﻳﺴﻴﻢ‬

‫)‪sw $t1, offset-value($t2‬‬ ‫ﻣﻘﺪﺍﺭ ﺭﺍ ﺍﺯ ‪ RF‬ﻣﯽ ﺧﻮﺍﻧﻴﻢ‬

‫ﺍﻳﻦ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﺁﺩﺭﺱ ﺣﺎﻓﻈﻪ ﺭﺍ ﺑﺎ ﺟﻤﻊ ﮐﺮﺩﻥ ﺭﺟﻴﺴﺘﺮ‬

‫ﭘﺎﻳﻪ )‪ ($t2‬ﺑﺎ ﻣﻴﺪﺍﻥ ﺁﻓﺴﺖ ‪ 16‬ﺑﻴﺘﯽ ﻋﻼﻣﺖ ﺩﺍﺭ ﻣﺤﺎﺳﺒﻪ ﻣﯽ‬
‫ﮐﻨﻨﺪ‪.‬‬

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 Datapath Building Blocks: load/store
6 5 5 16
I-Type opcode rs rt immediate
ALUop
MemWrite

5 Read
Instruction
Read reg 1
data 1 zero
5
Read reg 2 ALU
5 Registers ALU Read
Write reg Address
data
Write data Read Data
data 2 Memory

Write
data
RegWrite

16 sign 32 MemRead
extend

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 ‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ‪beq‬‬
‫ﺍﻳﻦ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺳﻪ ﻋﻤﻠﻮﻧﺪ ﺩﺍﺭﺩ‪:‬‬
‫‪ 2 ‬ﺭﺟﻴﺴﺘﺮ ﺑﺮﺍی ﻣﻘﺎﻳﺴﻪ ﺑﺎ ﻫﻢ‬
‫‪ ‬ﻳﮏ ﺁﻓﺴﺖ ‪ 16‬ﺑﻴﺘﯽ ﺑﺮﺍی ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﺍﻧﺸﻌﺎﺏ ﻧﺴﺒﺖ ﺑﻪ‬
‫ﺁﺩﺭﺱ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬
‫ﻗﺎﻟﺐ ﺩﺳﺘﻮﺭ‪: beq‬‬
‫‪beq $t1,$t2,offset‬‬
‫‪ ‬ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯی ﺍﻳﻦ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‪ ،‬ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ ﺑﺎ‬
‫ﺍﻓﺰﻭﺩﻥ ﺑﺨﺶ ﺁﻓﺴﺘﯽ ﮐﻪ ﻋﻼﻣﺖ ﺁﻥ ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ﺑﻪ ‪PC‬‬
‫ﺑﺪﺳﺖ ﻣﯽ ﺁﻳﺪ‪.‬‬
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 I-Type Instruction: bne
‫ ﺍﺯ ﺁﻧﺠﺎﺋﻴﮑﻪ ﺍﻳﻦ‬.‫ ﺑﺪﺳﺖ ﻣﯽ ﺁﻳﺪ‬PC ‫• ﻣﻘﺼﺪ ﺩﺳﺘﻮﺭ ﺍﻧﺸﻌﺎﺏ ﺍﺯ ﺟﻤﻊ ﻣﻘﺪﺍﺭ ﺍﻓﺴﺖ ﺑﺎ‬
‫ ﻧﻴﺎﺯ ﺍﺳﺖ ﺗﺎ ﻣﻘﺪﺍﺭ ﺍﻓﺴﺖ ﺑﻪ ﺍﻧﺪﺍﺯﻩ‬، (‫ﺑﺎﺷﺪ)ﺁﻓﺴﺖ ﮐﻠﻤﻪ‬4 ‫ﻣﻘﺼﺪ ﺑﺎﻳﺪ ﻣﻀﺮﺑﯽ ﺍﺯ‬
.‫ ﺑﺎﺭ ﺑﻪ ﺳﻤﺖ ﭼﭗ ﺷﻴﻔﺖ ﺩﺍﺩﻩ ﺷﻮﺩ‬2
6 5 5 16
I-Type opcode rs rt immediate

• if Reg[rs] != Reg[rd],
– PCcurrent=(PCprevious+4) + (offset*4)

• else if Reg[rs] == Reg[rt]

– PCcurrent=(PCprevious+4)

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 ‫• ﻋﻼﻭﻩ ﺑﺮ ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ ﺑﺎﻳﺪ ﺗﻌﻴﻴﻦ ﮐﻨﻴﻢ ﮐﻪ ﺁﻳﺎ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﻌﺪی ﺑﻪ ﺻﻮﺭﺕ ﺗﺮﺗﻴﺒﯽ ﺍﺳﺖ ﻳﺎ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ‬
‫ﺍﺳﺖ‪.‬‬
‫• ﺍﮔﺮ ﺷﺮﻁ ﺑﺮﻗﺮﺍﺭ ﺑﺎﺷﺪ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ ﺑﻪ ﻋﻨﻮﺍﻥ ﻣﻘﺪﺍﺭ ﺟﺪﻳﺪ ﺩﺭ‬
‫‪ PC‬ﻗﺮﺍﺭ ﻣﯽ ﮔﻴﺮﺩ ﭘﺲ ﺍﻧﺸﻌﺎﺏ ﺻﻮﺭﺕ ﭘﺬﻳﺮﻓﺘﻪ‪.‬‬
‫• ﺍﮔﺮ ﺑﺮﺍﺑﺮ ﻧﺒﺎﺷﻨﺪ ﻣﻘﺪﺍﺭ ﺍﻓﺰﺍﻳﺶ ﻳﺎﻓﺘﻪ ‪ PC‬ﺑﺎﻳﺪ ﺑﻪ ﺟﺎی ﻗﺒﻠﯽ ﻗﺮﺍﺭ ﮔﻴﺮﺩ‬
‫ﭘﺲ ﺍﻧﺸﻌﺎﺏ ﺻﻮﺭﺕ ﻧﭙﺬﻳﺮﻓﺘﻪ‪.‬‬
‫• ﺩﺭ ﻧﺘﻴﺠﻪ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺍﻧﺸﻌﺎﺏ ﺩﻭ ﻋﻤﻞ ﺍﻧﺠﺎﻡ ﻣﯽ ﺩﻫﺪ‪:‬‬
‫ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ‬
‫ﻣﻘﺎﻳﺴﻪ ﻣﺤﺘﻮﻳﺎﺕ ﺭﺟﻴﺴﺘﺮﻫﺎ‬
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 We need a second adder, since the ALU
is already doing subtraction for the beq

Multiply constant
by 4 to get offset

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 ‫ﺍﻳﺠﺎﺩ ﻳﮏ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﻭﺍﺣﺪ‬
‫• ﺑﺮﺍﻱ ﺳﺎﺧﺘﻦ ﺳﺎﺩﻩ ﺗﺮﻳﻦ ﻣﺴﻴﺮ ﺩﺍﺩﻩ‪ ،‬ﻣﻤﻜﻦ ﺍﺳﺖ ﺳﻌﻲ ﺑﺮ ﺍﻳﻦ ﺑﺎﺷﺪ ﻛﻪ ﺗﻤﺎﻡ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﺩﺭ ﻳﻚ ﭼﺮﺧﻪ ﺳﺎﻋﺖ ﺍﺟﺮﺍ ﺷﻮﻧﺪ‪.‬‬
‫• ﻻﺯﻣﻪ ﭼﻨﻴﻦ ﺍﻣﺮﻱ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﺑﻪ ﺍﺯﺍﻱ ﻫﺮ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﻴﭻ ﻛﺪﺍﻡ ﺍﺯ ﻣﻨﺎﺑﻊ ﻣﺴﻴﺮ‬
‫ﻫﺮ ﻋﻨﺼﺮﻱ ﻛﻪ ﺑﻴﺶ ﺍﺯ‬ ‫ﺩﺍﺩﻩ ﺭﺍ ﻧﻤﻲ ﺗﻮﺍﻥ ﺑﻴﺶ ﺍﺯ ﻳﻚ ﺑﺎﺭ ﺍﺳﺘﻔﺎﺩﻩ ﻛﺮﺩ‬
‫ﺑﻪ ﺣﺎﻓﻈﻪ ﺟﺪﺍ ﺑﺮﺍﻱ‬ ‫ﻳﻚ ﺑﺎﺭ ﺑﻪ ﺁﻥ ﻧﻴﺎﺯ ﺍﺳﺖ ﺑﺎﻳﺪ ﺗﻜﺮﺍﺭ ﺷﻮﺩ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﻭ ﺑﺮﺍﻱ ﺩﺍﺩﻩ ﻫﺎ ﻧﻴﺎﺯ ﺩﺍﺭﻳﻢ‪.‬‬
‫• ﺑﺮﺍﻱ ﺑﻪ ﺍﺷﺘﺮﺍﻙ ﮔﺬﺍﺷﺘﻦ ﻳﻚ ﻋﻨﺼﺮ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺑﻴﻦ ﺩﻭ ﻛﻼﺱ ﻣﺨﺘﻠﻒ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎ ﻣﻤﻜﻦ ﺍﺳﺖ ﻻﺯﻡ ﺑﺎﺷﺪ ﻛﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻳﻚ ﻣﺎﻟﺘﻲ ﭘﻠﻜﺴﺮ ﻭ‬
‫ﺳﻴﮕﻨﺎﻝ ﻛﻨﺘﺮﻟﻲ ﺟﻬﺖ ﺍﻧﺘﺨﺎﺏ ﻳﻜﻲ ﺍﺯ ﻭﺭﻭﺩﻱ ﻫﺎ ﭼﻨﺪ ﺍﺗﺼﺎﻝ ﻣﺨﺘﻠﻒ ﺑﻪ ﻭﺭﻭﺩﻱ‬
‫ﻳﻚ ﻋﻨﺼﺮ ﺑﺮﻗﺮﺍﺭ ﻣﻲ ﮔﺮﺩﺩ‬
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 ‫ﻣﺜﺎﻝ‪:‬ﺳﺎﺧﺘﻦ ﻳﮏ ﻣﺴﻴﺮ ﺳﺎﺩﻩ‬
‫ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی ﺣﺴﺎﺑﯽ ﻣﻨﻄﻘﯽ ﻭ ﺣﺎﻓﻈﻪ ﺍی‪:‬‬

‫‪ ‬ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی ﺣﺴﺎﺑﯽ ﺍﺯ ‪ ALU‬ﺑﺎ ﻭﺭﻭﺩی ﻫﺎﻳﯽ ﮐﻪ ﺍﺯ ‪ 2‬ﺭﺟﻴﺴﺘﺮ ﮔﺮﻓﺘﻪ‬

‫ﻣﯽ ﺷﻮﻧﺪ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻴﮑﻨﻨﺪ ﻭﻟﯽ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﻫﺎی ﺣﺎﻓﻈﻪ ﺍی ﻣﻤﮑﻦ ﺍﺳﺖ‬
‫ﺍﺯ‪ ALU‬ﺑﺮﺍی ﻣﺤﺎﺳﺒﻪ ﺁﺩﺭﺱ ﻫﻢ ﺍﺳﺘﻔﺎﺩﻩ ﮐﻨﻨﺪ ﮐﻪ ﺩﺭ ﺍﻳﻦ ﺻﻮﺭﺕ ﻭﺭﻭﺩی ﺩﻭﻡ‬
‫‪ ALU‬ﻣﻴﺪﺍﻥ ﺁﻓﺴﺖ ‪ 16‬ﺑﻴﺘﯽ ﺍﺯ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺎ ﻋﻼﻣﺖ ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ﺍﺳﺖ‪.‬‬

‫‪ ‬ﻣﻘﺪﺍﺭ ﺫﺧﻴﺮﻩ ﺷﺪﻩ ﺩﺭﻳﮏ ﺭﺟﻴﺴﺘﺮ ﻣﻘﺼﺪ ﺍﺯ ‪ ALU‬ﻳﺎ ﺣﺎﻓﻈﻪ ﻣﯽ ﺁﻳﺪ‪.‬‬

‫ﻧﺸﺎﻥ ﺩﻫﻴﺪ ﮐﻪ ﭼﮕﻮﻧﻪ ﻳﮏ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺑﺮﺍی ﻳﮏ ﺑﺨﺶ ﻋﻤﻠﮑﺮﺩی ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

‫ﻫﺎی ﺣﺴﺎﺑﯽ ﺑﺴﺎﺯﻳﻢ ﮐﻪ ﺍﺯ ﻳﮏ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﻭﺍﺣﺪ ﻭ ﻳﮏ ‪ ALU‬ﺑﺮﺍی ﺍﻧﺠﺎﻡ‬
‫ﻫﺮ ﺩﻭ ﻧﻮﻉ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺍﺳﺘﻔﺎﺩﻩ ﻣﯽ ﮐﻨﺪ‪.‬ﺗﻌﺪﺍﺩ ﻣﺎﻟﺘﯽ ﭘﻠﮑﺴﺮ ﺁﺯﺍﺩ ﺍﺳﺖ‪.‬‬
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 ‫ﭘﺎﺳﺦ‬

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 MIPS ‫ﻳﮏ ﻣﺴﻴﺮﺩﺍﺩﻩ ﺳﺎﺩﻩ ﺑﺮﺍی ﻣﻌﻤﺎﺭی‬
PCSrc=1
branches
To PC+4+(offset×4).
PCSrc=0
continues
4 to PC+4

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 ‫ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ‬

‫• ﺣﺎﻻ ﺑﺎﻳﺪ ﺑﻪ ﺳﺮﺍﻍ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺑﺮﻭﻳﻢ‪:‬‬

‫ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺑﺎﻳﺪ ﺑﺘﻮﺍﻧﺪ ﻭﺭﻭﺩی ﻫﺎ ﺭﺍ ﮔﺮﻓﺘﻪ ﻭ ﻳﮏ ﺳﻴﮕﻨﺎﻝ‬
‫ﻧﻮﺷﺘﻦ ﺑﺮﺍی ﻫﺮ ﻋﻨﺼﺮ ﺣﺎﻟﺖ‪ ،‬ﮐﻨﺘﺮﻝ ﺍﻧﺘﺨﺎﺑﮕﺮ ﺑﺮﺍی ﻫﺮ‬
‫ﻣﺎﻟﺘﯽ ﭘﻠﮑﺴﺮ ﻭ ﮐﻨﺘﺮﻝ ‪ ALU‬ﺗﻮﻟﻴﺪ ﮐﻨﺪ‪.‬‬

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 ‫ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ‬
Instruction<31:0>

<26:31>

<0:5>

<21:25>

<16:20>

<11:15>
Inst

<0:15>
Memory
Adr
Op Fun Rt Rs Rd Imm16

Control

nPC_sel RegWr RegDst MemtoReg ALUSrc ALUctr MemWr Equal

DATA PATH

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 ‫ﻃﺮﺍﺣﯽ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺍﺻﻠﯽ‬
31 25 20 15 10 5 0

R-type:
op rs rt rd shamt funct

31 25 20 15 0

I-Type: address offset

op rs rt

31 25 0

J-type:
op target address

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 ALU Control
Plan to control ALU: main control sends a 2-bit ALUOp control field
to the ALU control. Based on ALUOp and funct field of instruction the
ALU control generates the 3-bit ALU control field
ALU Function
operation 2

Main 3
000 and ALUOp ALU
Control To
Unit Control ALU ALU
001 or
control
010 add input
110 sub
6
111 slt (set less than)
Instruction
funct field

ALU must perform

add for load/stores (ALUOp 00)
sub for branches (ALUOp 01)
one of and, or, add, sub, slt for R-type instructions, depending on the instruction’s 6-bit
funct field (ALUOp 10) 56
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 2

Main 3
ALUOp ALU
Control To
Unit Control ALU
ALU
control
input

Instruction
funct field

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 ‫ﮐﻨﺘﺮﻝ ‪ALU‬‬

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 ‫ﺍﻓﺰﻭﺩﻥ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺍﺻﻠﯽ‬

‫ﺍﻳﻦ ﻭﺍﺣﺪ ﺑﺎﻳﺪ ‪:‬‬

‫ﻋﻤﻠﻴﺎﺕ‪ Alu‬ﺭﺍ ﻣﺸﺨﺺ ﻧﻤﺎﻳﺪ‪ ،‬ﺳﻴﮕﻨﺎﻟﻬﺎﻱ ﺭﺟﻴﺴﺘﺮ ﻓﺎﻳﻞ ﻭ ﺣﺎﻓﻈﻪ ﺭﺍ ﺗﻮﻟﻴﺪ ﻧﻤﺎﻳﺪ‪ ،‬ﺟﺮﻳﺎﻥ ﺩﺍﺩﻩ ﺍﺯ ﻃﺮﻳﻖ‬ ‫•‬
‫ﻣﺎﻟﺘﻲ ﭘﻠﻜﺴﺮﻫﺎ ﺭﺍ ﻛﻨﺘﺮﻝ ﻧﻤﺎﻳﺪ‪.‬‬

‫ﻣﻼﺣﻈﺎﺕ‬

‫– ﻣﻘﺪﺍﺭ ﺍﭘﻜﺪ ﻫﻤﻴﺸﻪ ﺩﺭ ﺑﻴﺖ ﻫﺎﻱ ‪ 26-31‬ﻗﺮﺍﺭﺩﺍﺭﺩ‬

‫– ﺁﺩﺭﺱ ﺭﺟﻴﺴﺘﺮﻫﺎﺋﻲ ﻛﻪ ﺑﺎﻳﺪ ﺧﻮﺍﻧﺪﻩ ﺷﻮﻧﺪ ﺗﻮﺳﻂ ﻓﻴﻠﺪ ‪) rs‬ﺑﻴﺖ ﻫﺎﻱ ‪ (21-25‬ﻭﻓﻴﻠﺪ ‪) rt‬ﺑﻴﺖ‬
‫ﻫﺎﻱ ‪(20-16‬ﻣﺸﺨﺺ ﻣﻴﺸﻮﻧﺪ‪.‬‬

‫– ﺁﺩﺭﺱ ﺭﺟﻴﺴﺘﺮﻱ ﻛﻪ ﺑﺎﻳﺪ ﻧﻮﺷﺘﻪ ﺷﻮﻧﺪ ﺩﺭﻳﻜﻲ ﺍﺯ ﺩﻭ ﻣﻜﺎﻥ ﺍﺳﺖ‪ :‬ﻓﻴﻠﺪ ‪ rt‬ﺑﺮﺍﻱ ﺩﺳﺘﻮﺭ ‪ lw‬ﻭ ﻓﻴﻠﺪ‬
‫‪rd‬ﺑﺮﺍﻱ ﺩﺳﺘﻮﺭﺍﺕ ‪R-Type‬‬

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‫– ﻣﻘﺪﺍﺭ ﺍﻓﺴﺖ ﺩﺭ ﺑﻴﺖ ﻫﺎﻱ ‪ 15-0‬ﺍﺳﺖ‪.‬‬
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 ‫• ﺩﺭ ﺷﻜﻞ ﺑﻌﺪ ﺑﻠﻮﻙ ﻛﻨﺘﺮﻝ‪ ALU‬ﻧﻴﺰ ﺍﺿﺎﻓﻪ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬

‫• ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ‪ PC‬ﺩﺭ ﭘﺎﻳﺎﻥ ﻫﺮ ﭼﺮﺧﻪ ﺳﺎﻋﺖ ﻧﻮﺷﺘﻪ ﻣﻲ ﺷﻮﺩ‬

‫ﺍﺣﺘﻴﺎﺟﻲ ﺑﻪ ﺳﻴﮕﻨﺎﻝ ﻛﻨﺘﺮﻝ ﻧﻮﺷﺘﻦ ﻧﺪﺍﺭﺩ‪.‬‬

‫• ﻣﻨﻄﻖ ﻛﻨﺘﺮﻟﻲ ﺍﻧﺸﻌﺎﺏ ﺗﻌﻴﻴﻦ ﻣﻲ ﻛﻨﺪ ﻛﻪ ﭼﻪ ﺯﻣﺎﻥ ‪ PC‬ﺑﺎﻳﺪ‬

‫ﺍﻓﺰﺍﻳﺶ ﻳﺎﻓﺘﻪ ﻭ ﭼﻪ ﺯﻣﺎﻥ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ ﺩﺭ ﺁﻥ ﻧﻮﺷﺘﻪ‬
‫ﺷﻮﺩ‪.‬‬

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 51 ‫ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺷﮑﻞ ﺻﻔﺤﻪ‬ :‫ﻃﺮﺍﺣﯽ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺍﺻﻠﯽ‬

69 Computer Architecture & Design

Advanced
Science & Research Branch
 Advanced Computer Architecture & Design
70
Science & Research Branch
 ‫ﺗﺎﺛﻴﺮ ﻫﺮﮐﺪﺍﻡ ﺍﺯ ‪ 7‬ﺳﻴﮕﻨﺎﻝ ﮐﻨﺘﺮﻟﯽ‬

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 Single Cycle Datapath with Control Unit

72
 ‫ﺗﻨﻈﻴﻢ ﺧﻄﻮﻁ ﮐﻨﺘﺮﻟﯽ ﺑﺎ ﻣﻴﺪﺍﻥ ﻫﺎی ﮐﺪ ﻋﻤﻞ ﺍﺯ‬
‫ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬

Advanced Computer Architecture & Design

73
Science & Research Branch
 ‫ﻋﻤﻠﮑﺮﺩ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﻧﻮﻉ ‪R‬‬
‫ﻣﺮﺍﺣﻞ ﺑﻪ ﺗﺮﺗﻴﺐ ﺟﺮﻳﺎﻥ ﺍﻃﻼﻋﺎﺕ‪:‬‬
‫‪ -1‬ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺮﺩﺍﺷﺖ ﻣﯽ ﺷﻮﺩ ﻭ ‪ PC‬ﺍﻓﺰﺍﻳﺶ ﻣﯽ ﻳﺎﺑﺪ‬
‫‪-2‬ﺩﻭ ﺭﺟﻴﺴﺘﺮ ‪ $t2,$t3‬ﺍﺯ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﺧﻮﺍﻧﺪﻩ ﻣﯽ ﺷﻮﺩ ﻭ ﻧﻴﺰ ﺩﺭ ﻃﻮﻝ ﺍﻳﻦ‬
‫ﻣﺮﺣﻠﻪ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺍﺻﻠﯽ ﭼﮕﻮﻧﮕﯽ ﺗﻨﻈﻴﻢ ﺧﻄﻮﻁ ﮐﻨﺘﺮﻟﯽ ﺭﺍ ﻣﺤﺎﺳﺒﻪ ﻣﯽ‬
‫ﮐﻨﺪ‪.‬‬
‫‪ ALU-3‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﮐﺪ ﻋﻤﻠﮑﺮﺩ ﺑﺮ ﺭﻭی ﺩﺍﺩﻩ ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﻋﻤﻞ ﻣﻨﺎﺳﺐ ﺭﺍ ﺑﻪ‬
‫ﺍﻧﺠﺎﻡ ﻣﯽ ﺭﺳﺎﻧﺪ‪.‬‬
‫‪-4‬ﻧﺘﻴﺠﻪ ﺣﺎﺻﻞ ﺍﺯ‪ ALU‬ﺩﺭ ‪ RF‬ﻧﻮﺷﺘﻪ ﻣﯽ ﺷﻮﺩ‪.‬ﺑﺮﺍی ﺍﻧﺘﺨﺎﺏ ﺭﺟﻴﺴﺘﺮ ﻣﻘﺼﺪ ﺩﺭ‬
‫‪ RF‬ﺍﺯ ﺑﻴﺘﻬﺎی ‪ 15:11‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﯽ ﺷﻮﺩ‪.‬‬
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 R-type Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 zero
Data 1
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

75
‫ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺍی ﺩﺭ ﺣﺎﻝ ﮐﺎﺭ ﺑﺮﺍی ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺎﺭ ﮐﺮﺩﻥ‬

‫‪ -1‬ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺮﺩﺍﺷﺖ ﻣﯽ ﺷﻮﺩ ﻭ ‪ PC‬ﺍﻓﺰﺍﻳﺶ ﻣﯽ ﻳﺎﺑﺪ‬

‫‪-2‬ﻣﻘﺪﺍﺭ ﺭﺟﻴﺴﺘﺮ ‪ $t2‬ﺍﺯ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﺧﻮﺍﻧﺪﻩ ﻣﯽ ﺷﻮﺩ‬
‫‪ ALU-3‬ﻣﺠﻤﻮﻉ ﻣﻘﺪﺍﺭ ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﺍﺯ ‪ RF‬ﻭ ‪ 16‬ﺑﻴﺖ ﮐﻢ ﺍﺭﺯﺵ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ‬
‫ﮐﻪ ﺑﻴﺖ ﻋﻼﻣﺖ ﺁﻥ ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ﺭﺍ ﻣﺤﺎﺳﺒﻪ ﻣﯽ ﮐﻨﺪ‪.‬‬
‫‪-4‬ﺣﺎﺻﻞ ﺟﻤﻊ ﺑﻪ ﺩﺳﺖ ﺁﻣﺪﻩ ﺍﺯ‪ ALU‬ﺑﻪ ﻋﻨﻮﺍﻥ ﺁﺩﺭﺱ ﺣﺎﻓﻈﻪ ﺍی ﻣﻮﺭﺩ‬
‫ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﻣﯽ ﮔﻴﺮﺩ‪.‬‬
‫‪-5‬ﺩﺍﺩﻩ ﺩﺭﻳﺎﻓﺘﯽ ﺍﺯ ﻭﺍﺣﺪ ﺣﺎﻓﻈﻪ ﺩﺭ ‪ RF‬ﻧﻮﺷﺘﻪ ﻣﯽ ﺷﻮﺩ‪.‬ﺭﺟﻴﺴﺘﺮ ﻣﻘﺼﺪ ﺑﺎ‬
‫ﺑﻴﺘﻬﺎی ‪ 20:16‬ﺍﺯ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ‪ $t1‬ﻣﺸﺨﺺ ﻣﯽ ﺷﻮﺩ‪.‬‬
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 Load Word Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 zero
Data 1
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

78
 ‫ﻋﻤﻠﮑﺮﺩ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺍﻧﺸﻌﺎﺏ ﺩﺭ ﺻﻮﺭﺕ ﺑﺮﺍﺑﺮی‬
‫‪ -1‬ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﺑﺮﺩﺍﺷﺖ ﻣﯽ ﺷﻮﺩ ﻭ ‪ PC‬ﺍﻓﺰﺍﻳﺶ ﻣﯽ ﻳﺎﺑﺪ‬
‫‪-2‬ﺩﻭ ﺭﺟﻴﺴﺘﺮ ‪ $t2,$t3‬ﺍﺯ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﺧﻮﺍﻧﺪﻩ ﻣﯽ ﺷﻮﺩ‬
‫‪ ALU-3‬ﺑﺮ ﺭﻭی ﻣﻘﺎﺩﻳﺮ ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﺍﺯ ﻓﺎﻳﻞ ﺭﺟﻴﺴﺘﺮ ﻋﻤﻞ ﺗﻔﺮﻳﻖ ﺭﺍ ﺍﻧﺠﺎﻡ‬
‫ﻣﯽ ﺩﻫﺪ‪.‬ﻣﻘﺪﺍﺭ ‪ PC+4‬ﺑﺎ ‪ 16‬ﺑﻴﺖ ﮐﻢ ﺍﺭﺯﺵ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻞ ﮐﻪ ‪ 2‬ﺑﻴﺖ ﺑﻪ‬
‫ﺳﻤﺖ ﭼﭗ ﺷﻴﻔﺖ ﻳﺎﻓﺘﻪ ﻭ ﺑﻴﺖ ﻋﻼﻣﺖ ﺁﻥ ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ﺟﻤﻊ ﻣﯽ‬
‫ﺷﻮﺩ‪.‬ﻧﺘﻴﺠﻪ ﺣﺎﺻﻞ ﺁﺩﺭﺱ ﻫﺪﻑ ﺍﻧﺸﻌﺎﺏ ﺍﺳﺖ‪.‬‬
‫‪ -4‬ﺧﺮﻭﺟﯽ ﺻﻔﺮ‪ ALU‬ﺗﻌﻴﻴﻦ ﻣﯽ ﮐﻨﺪ ﮐﻪ ﻧﺘﻴﺠﻪ ﮐﺪﺍﻡ ﺟﻤﻊ ﮐﻨﻨﺪﻩ ﺩﺭ ‪PC‬‬
‫ﺫﺧﻴﺮﻩ ﻣﯽ ﺷﻮﺩ‪.‬‬
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 Branch Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 zero
Data 1
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

81
 Adding the Jump Operation

Instr[25-0] 1
Shift
28 32
26 left 2
PC+4[31-28]
0
Add 0
Add 1
4 Shift
left 2 PCSrc
Jump
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 zero
Data 1
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

82