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10029476DSD

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0% found this document useful (0 votes)
8 views1 page

10029476DSD

Lshbdisje

Uploaded by

Children Academy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Paper / Subject Code: 50313 / Digital System Design

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Time: 3 hours Max. Marks: 80

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N.B. 1) Question No. 1 is compulsory.

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2) Attempt any three from the remaining questions.

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1 Solve the following questions:

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a) State and prove Demorgan’s theorem with the help of proper

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example.

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b) Represent the decimal number 27 in binary form using 5

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1) Binary code 2) Gray code 5

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c) Explain working of universal shift register with the help of

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different operating modes.

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d) Design 4:1 multiplexer using VHDL/Verilog code.

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2 a) i) Convert the following binary numbers to their decimal 10
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equivalent numbers.
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1) 10010111 2) 10111.0110
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ii) Convert the following decimal numbers to their binary


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equivalent numbers.

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1) (79.515)10 2) (109.125)10

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b) Simplify the following three-variable expression using Boolean 10

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algebra. 5A
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Y (A, B, C) = ∑m (0, 1, 3, 4, 7)
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i)
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Z (A, B, C) = ∑m (0, 1, 2, 3, 4, 5, 6, 7)
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ii)

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3 a) Simplify the following four-variable Boolean functions using 10

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Quine-McCluskey method. 78
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Y (A, B, C, D) = ∑m (2, 4, 5, 9, 12, 13)


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b) i) Convert S-R Flip-Flop to T Flip-Flop. 10


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ii) Convert J-K Flip-Flop to T Flip-Flop.


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4 a) Simplify the following Boolean expressions using K-map 10


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and implement obtained expressions using suitable gates.


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Q (A, B, C, D) = πM (1, 2, 5, 6, 8, 9, 15)


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i)
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R (A, B, C, D) = πM (0, 1, 2, 3, 5, 6, 7, 12)


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ii)
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b) Differentiate between PAL (Programmable Logic Array) 10


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and PLA (Programmable Array Logic) with the help of


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suitable example.
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5 a) Design and explain 2-bit magnitude comparator. 10


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b) Prove that NAND and NOR gates are universal gates


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6 a) Explain working of PISO (Parallel Input Serial Output) and 10


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SIPO (Serial Input Parallel Output) types of shift registers.


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b) Implement half subtractor using suitable gates


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c) Design 8:1 Mux using 4:1 Mux.


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******************
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