Memory Test The Types of Semiconductor Memory

• Memory market and memory complexity • Dynamic Random Access Memory (DRAM)
• Notation • Static Random Access Memory (SRAM)
• Memory Tests • Cache DRAM (CDRAM)
• March Test • Read-Only Memories (ROMs)
• March Test Algorithm • Erasable, Programmable Read-Only Memories (EPROMs)
• Functional Faults • Electrically Erasable, Programmable ROMs (EEPROMs
• Neighborhood Pattern Sensitive Faults
• Memory BIST

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Memory Density and Defect Trends Memory Cells Per Chip

◼ In order to keep memory prices economical, the test cost per

memory chip (which is directly related to the test time)
cannot increase significantly.
◼ The number of bits per chip continues to increase
exponentially and fault sensitivity increases, so faults become
more complex.
◼ Tests for detecting the coupling faults between adjacent
memory cells are more complicated and take longer than
individual cell tests.

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Defect Trends Test Time Complexity

◼ We have exponentially less charge stored per memory cell, as well ◼ Memory tests should deliver the best fault coverage possible given a
as much closer proximity of memory cells to each other, cell certain test time.
coupling faults are now common and should be routinely tested for. ◼ Also, we must consider the distinction between memory
manufacturing test and memory end-user test.
◼ Also, cells are becoming more vulnerable to manufacturing process
◼ Manufacturing test will end with the defective memory rows and
disturbances.
columns being rewired to spare rows and columns.
◼ Assume that multiple memory faults will be present, and test ◼ Manufacturing test must also include diagnosis, which not only
appropriately. indicates that the memory chip is defective, but also shows
◼ During initial manufacturing test, the manufacturer develops a map which location is defective.
of the faulty rows and columns in the array. ◼ The manufacturer use a variety of tests, such as initial production
◼ The column and row address decoders are rewired to reroute these characterization tests, to determine which failures are really
defective rows and columns to working spare rows and columns occurring, versus a variety of production tests for high-volume,
high-yield production.
included in the memory.

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Test Time Complexity Notation

◼ The major change in memory testing is that tests are based on ◼ 0 -- A cell is in logical state 0
fault models, and tests are proven to have complete coverage ◼ 1 -- A cell is in logical state 1
for particular fault models. ◼ X -- A cell is in logical state X
◼ A fault model is an abstraction of the error caused by a ◼ A -- A memory address
particular physical fault(s). ◼ ABF -- AND Bridging Fault
◼ The purpose of the fault model is to simplify the testing ◼ AF -- Address Decoder Fault
procedure and reduce its cost, while still retaining the ◼ B -- Memory # bits in a word
capability of detecting the presence of the modeled fault. ◼ BF -- Bridging Fault
◼ Fault model need not accurately model the physical fault, as ◼ C -- A Memory Cell
long as it still indicates the presence of the physical fault. ◼ CF -- Coupling Fault
◼ Also, tests are proven to be minimal length for the given set of ◼ CFdyn -- Dynamic Coupling Fault
fault models covered by the tests. ◼ CFid -- Idempotent Coupling Fault

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Notation Fault Category

◼ CFin -- Inversion Coupling Fault Faults can either be permanent or non-permanent.

◼ DRF -- RAM Data Retention Fault
Permanent: These faults are caused by the following mechanisms,
◼ k -- Size of a neighborhood
and can be modeled with a fault model, since they will exist
◼ M -- memory cells, words, or address set
◼ n -- # of Memory bits indefinitely.
◼ N -- Number of address bits: n = 2N • Bad Electrical Connections (missing or added)
◼ NPSF -- Neighborhood Pattern Sensitive Fault • Broken Components (this could be an IC mask defect or a
◼ OBF -- OR Bridging Fault silicon-to-metal or a metal-to-package connection problem)
◼ SAF -- Stuck-at Fault • Burnt-Out Chip Wire
◼ SCF -- State Coupling Fault
• Corroded Connection Between Chip and Package
◼ SOAF -- Stuck-Open Address Decoder Fault
◼ TF -- Transition Fault • Chip Logic Error

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Fault Category Fault Category

Non-Permanent: Non-permanent faults are present only part of Here are the common causes of transient faults:
the time, and occur randomly. ▪ Cosmic Rays
They have no well-defined fault model. These faults particularly ▪ ionized Helium atoms
afflict memory integrated circuits, but memory system ▪ Air Pollution (causes temporary wire short or open)
designers handle these problems by including information ▪ Humidity (causes temporary wire short)
redundancy, or redundant error-correcting codes, in each ▪ Temperature (causes temporary logic malfunction)
system memory location. Here are the common causes of intermittent faults:
• Loose Connections
Non-permanent faults are further subdivided into transient and
• Aging Components (logic gate delays change and relative signal
intermittent faults. arrival times therefore change)
Transient faults are caused by environmental conditions, while • Hazards and Races in Critical Timing Paths (from bad design)
intermittent faults are cause by non-environmental conditions. • Resistors, Capacitors, and Inductors Vary (causing timing faults)

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Memory Test Levels Memory Test Levels

◼ Figure shows the chip, array, and board levels of functional

memory testing.
◼ Chip testing must be done with a memory fault model to
make it economical.
◼ Memory array testing must also test the chip select and
control logic.
◼ Memory board testing must test the memory array, the refresh
logic, the error detection and correction logic, the board
selector hardware, and the memory board controller.
◼ Electrical parametric tests are also important for memory
systems.

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March Test Notation March Test Notation

◼ r -- Read a memory location

◼ w -- Write a memory location
◼ r0 -- Read a 0 from a memory location
◼ r1 -- Read a 1 from a memory location
◼ w0 -- Write a 0 to a memory location
◼ w1 -- Write a 1 to a memory location
◼ -- Write a 1 to a cell containing 0
◼ -- Write a 0 to a cell containing 1

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March Tests MATS+ March Test Algorithms

Suk and Reddy described the march tests, which consist of a finite
operation sequence
The march test is applied to each cell in memory before proceeding to the next
cell, which means that if a specific pattern is applied to one cell, then it
must be applied to all cells.
This is either done in increasing memory address order ( or from 0 to n – 1) or
decreasing order The address order may be irrelevant.
Note, however, that the only real requirement for the march tests is that the
address orders ↑ and ↓ must be the inverses of each other.
An operation can be r0, r1, w0, or w1, which were defined earlier. Consider
the MATS+ march test, written as

It has the three march elements

These are written with commas or semicolons separating them, and the entire
march sequence is enclosed in braces. All operations of a march element
are done before proceeding to the next address

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Functional Memory Model
Simplified Functional Memory Model

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Subset of functional memory faults Reduced Functional Faults

Fault
SAF Stuck-at fault
TF Transition fault
CF Coupling fault
NPS Neighborhood Pattern Sensitive fault
F

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Stuck-at Faults Transition Faults

◼ Condition: For each cell, must read a 0 and a 1. ◼ Cell fails to make 0-→1 or 1-→0 transition

◼ < /0> (< /1>) ◼ Condition: Each cell must undergo a transition and

transition, and be read after such, before undergoing any

further transitions.

◼ <↑/0>, <↓/1>

< /0> transition fault

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Coupling Faults

◼ Coupling Fault (CF): Transition in bit j causes unwanted Inversion Coupling Faults:
change in bit i An inversion coupling fault (CFin) means that ↑ or ↓ or
◼ 2-Coupling Fault is a coupling fault involving two cells. transition in cell j inverts the contents of cell i.
◼ A write operation that generates an ↑ or ↓transition in Cell i is said to be coupled to cell j, which is the coupling
cell j changes the contents of cell i. cell.
◼ The 2-coupling fault is a special case of the k-coupling We use the notation<↑; > for Ci, and Cj and where the
fault, which has the 2-coupling fault behavior with means that cellCi contents were inverted.
respect to cells i and j, except that faulty behavior occurs The two possible CFin types are <↑; > and<↓; >
only when another k – 2 cells are in a particular state. Bridging Faults: A bridging fault (BF) is a short circuit
between two or more cells or lines. It is a bidirectional
fault, so either cell/line can affect the other cell/line

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Address Decoder Faults (ADFs)

Idempotent Coupling Faults.: An idempotent coupling fault ◼ An address decoder fault (AF) represents an address
(CFid) is where an ↑ or ↓ transition in cell Cj sets cell Ci to 0 decoding error, in which we assume that the decoder
or 1. This is denoted as< ↑;0> or < ↑;1> depending on whether logic does not become sequential We also assume that
cell i is set to 0 or 1, for a rising transition for cell j. The other the fault is the same during both read and write
two idempotent coupling faults are <↓;0> and < ↓;1> .
operations. Van de Goor, classifies these faults into four
Dynamic Coupling Faults. A dynamic coupling fault (CFdyn) cases:
occurs between cells in different words. A read or write
operation on one cell forces the contents of the second cell
either to 0 or 1. This is a more general case of the CFid,
because a CFdyn can be sensitized by any read or write
operation, where as a CFid can only be sensitized by a writing
a change (transition write operation) to the coupling cell.

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Three types of NPSFs:

Neighborhood Pattern Sensitive Faults
◼ In a pattern sensitive fault (PSF), the content of cell i (or the Active NPSF (ANPSF) (also called dynamic ), the base cell
ability of cell i to change) is influenced by the contents of all changes due to a change in the pattern of the deleted
other memory cells, which may be either a pattern of 0s and 1s neighborhood.
or a pattern of transitions.
◼ The PSF is the most general k-coupling fault, where (all of the A passive NPSF (PNPSF) means that a certain
memory.) neighborhood pattern prevents the base cell from
◼ The neighborhood is the total number of cells involved in this changing.
fault, where the base cell is the cell-under-test, and the deleted A static NPSF (SNPSF) the base cell is forced into a
neighborhood is the neighborhood without the base cell. particular state when the deleted neighborhood contains
◼ In the PSF model, the neighborhood could be anywhere in the a particular pattern.
memory array, whereas in a neighborhood pattern sensitive
fault (NPSF), the neighborhood must be in a single position
surrounding the base cell.

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Active NPSF (ANPSF) Type-1 Active NPSF
◼ Active: Base cell changes when any one deleted neighborhood
A Type-1 neighborhood (figure next page) has four deleted
neighborhood cells. cell has a transition
We describe a fault as Ci.j <d0,d1,d3,d4;b> . Ci.j is the base cell ◼ Condition for detection and location: Each base cell must be
location, d0,d1,d3 and d4 are the deleted neighborhood read in state 0 and state 1, for all possible deleted neighborhood
patterns, and b is the fault effect in the base cell Ci.j pattern changes.
<0,↓,1,1;1> . denotes an ANPSF fault where the base cell Ci.j
◼ Notation: C i,j < d0, d1, d3, d4 ; b >
is initially 0, d1 experiences a ↓ transition, while d0,d3and d4 0
contain 011. ◼ Examples:
1 2 3
The fault effect is to switch the base cell to 1. When the base cell ANPSF: C i,j < 0, ↓ , 1, 1; 0 > 4
becomes 0, we write this as Ci.j <0,↓,1,1;0> and when the base
cell is inverted, we write this a Ci.j <0,↓,1,1; > ANPSF: C i,j < 0, ↓ , 1, 1; >
2 – base cell k=5
0, 1, 3 and 4 – deleted neighborhood cells
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Passive NPSF
Type-2 Active NPSF
◼ Passive NPSF: A certain neighborhood pattern prevents the base cell from
◼ Used when diagonal couplings are significant changing.
◼ Condition for detection and location: Each base cell must be written and
read in state 0 and in state 1, for all deleted neighborhood pattern changes.

0 1 2 ◼ ↑ / 0 ( ↓ / 1 ) – Base cell fault effect indicating that base

4 – base cell
0, 1, 2, 3, 5, 6, 7 and 8 – deleted 3 4 5 cannot changed from 0 (or 1).
neighborhood cells
6 7 8 The fault preventing the base cell from changing from 0 is denoted as
Ci,j<0,0,1,1;↑ /0>
If it cannot change from 1, we write Ci,j<0,0,1,1;↓ /1>
k=9 If it cannot change regardless of content, we write this as Ci,j<0,0,1,1; /x>

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Static NPSF Memory

Test
◼ Static NPSF: Base cell forced into a particular state when • Memory market and memory complexity
deleted neighborhood contains particular pattern. • Notation
◼ Differs from active – need not have a transition to sensitize an • Memory Tests
SNPSF • March Test
◼ Condition for detection and location: Apply all 0 and 1 • March Test Algorithm
combinations to k-cell neighborhood, and verify that each • Functional Faults
base cell was written with a 1 and a 0.
• Neighborhood Pattern Sensitive Faults
◼ Examples:

• Memory BIST
Ci,j < 0, 1, 0, 1; - / 0 > means that base cell forced to 0
Ci,j < 0, 1, 0, 1; - / 1 > means that base cell forced to 1

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 Introduction

• Memory BIST We have entered an era of integration of various layouts or cores,

• Mutual Comparator from different companies, onto a single chip.
• Parallel Memory BIST For example, one custom VLSI chip may now contain an
• Static RAM March Test BIST embedded RAM, a microprocessor, a DSP processor, and
various analog circuit layouts.
• SRAM BIST with a MISR
Embedded RAM memories are perhaps the hardest type of digital
circuit to test, because memory testing requires delivery of a
huge number of pattern stimuli to the memory and the readout
of an enormous amount of cell information.

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Introduction Definitions

• The difficulty and time required to propagate all of that • Concurrent BIST – The memory can be tested concurrently
information through the various glue logic and busses in an with normal system operation.
embedded core chip almost forces the use of memory BIST. • Non-Concurrent BIST – Requires interruption of the normal
• Most memory BIST schemes exploit parallelism within the system function in order to perform the testing.
memory device to achieve a reduction in test time (cost). • The original memory contents are lost.
• More than one memory cell is accessed with each address, • Transparent Testing – A memory test mechanism that
usually by accessing the entire row of cells on a word line for requires interruption of the normal system function for testing.
a single read or write operation. The original memory contents are preserved in the memory
after testing is finished.

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LFSR and Inverse Pattern LFSR Normal LFSR

• Memory BIST requires an address generator or stepper (often • NOR gate forces LFSR into all-0 state: Get all 2n patterns
an LFSR) and a data generator.
• The LFSR can be adjusted to provide the all-zero pattern and G (x) = x3 + x + 1
the forward and exact reverse LFSR sequence.
• It satisfies all of the address ordering conditions for detecting
address decoder faults with march tests.
• A reverse sequence LFSR generator have a characteristic
polynomial that is the reciprocal characteristic polynomial of
the LFSR, and it must shift in the opposite direction from the
original LFSR.
• This is achieved by numbering the cells of the LFSR in the
reverse order.

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Inverse LFSR

• NOR gate forces LFSR into all-0 state: Get all 2n patterns
G (x) = x3 + x2 + 1

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LFSR and Inverse Pattern LFSR

• The NOR gate forces the LFSR into the all-zero state.
• These two LFSRs can be combined into a single LFSR,
by adding a few additional logic gates.
• Advantage of the LFSR over a counter is that the probability
of an address bit changing is equal for all address bits.
• This enables detection of write recovery faults.
• The test data can either be produced by a finite state machine
or from the address.

Source :https://www.youtube.com/watch?v=9mlT3SPJoMg&t=1148s

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Mutual Comparator Mutual Comparator System

• Test four or more memory arrays at same time:

▪ Apply same test commands and addresses to all four arrays • Memory BIST with mutual comparator
at same time
▪ Assess errors when one of the di (responses) disagrees with
the others

• Benefit: Need not have good machine response stored or

generated

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Memory BIST Parallel Memory BIST

• The march tests are appropriate for SRAM testing. ▪ The memory must be equipped with this test hardware:
• For DRAM testing, a neighborhood pattern sensitive fault ▪ A memory BIST Controller.
(NPSF) testing model is more appropriate, since it provides ▪ An Address Stepper.
better DRAM fault coverage.
▪ A MUX circuit feeding the memory during self-test from
• Since the operation count is much longer for NPSF tests than the controller.
for march tests, the benefit of BIST is greater when the NPSF ▪ A Comparator for response checking.
tests are implemented on-chip.
▪ A Background Pattern inserter or Data Generator for
• No NPSF test can detect address decoder faults, whereas all
inserting test patterns into memory columns.
march tests can.
• Therefore, an appropriate scheme would be to put both test
algorithms in the BIST hardware.

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Parallel Memory BIST Parallel Memory March C

• Add MUX to inputs of write drivers:

• Selects normal data input or left neighbor sense amplifier output
• Creates shift register during self-test
• Generalize any March test to test n-bit words in array rows
• (x)n means repeat x operations n times

• Example: March Cn
◼ { (w0)n (r0, w0)n; (r0, w1)n (r1, w1)n;
(r1, w0)n (r0, w0)n; (r0, w1)n (r1, w1)n;
(r1, w0)n (r0, w0)n; (r0, w0)n (r0, w0)n}

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MATS+ RAM BIST SRAM BIST with MISR

• For single-bit word – can generalize to n-bit words • A memory BIST scheme accounts for the memory layout, and
• Need Address MUX – switch row decoder from normal input the memory address scrambling from the logical address
to address stepper (which is the Up/Down LFSR) space to the physical memory address space.
• The memory location is written with the value of its address
• # states needed:
or the bitwise complement of its address, so a data generator
• 2 x # March elements + 3 is not needed.
• Three extra states: • Each location contains unique data.
• Start Error Correct • A series of up and down marches are performed using the
• Chip area overhead: 1 to 2 % -- widely used Up/Down LFSR to detect stuck-at faults and transition faults.
• Another scheme uses a binary counter to provide addresses,
input test data, and testing control signals.

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 SRAM BIST with MISR
Counter Test Technique for RAM BIST
• Figure illustrated the test hardware and RAM together.
• A MISR is used to compact the output from the memory.
• The MISR must be initialized before BIST, and must be
disabled when shifting or loading new data into the RAM,
since the output of the RAM is unknown during writes to the
RAM.
• The same counter bit that enables writing also disables the
LFSR in the MISR.
• Use MISR to compress memory outputs

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Summary

• No single type of test (march, NPSF…) is sufficient for

current
RAM testing needs, so a combination of various tests is used.
• Fault analysis is now necessary, to ensure that the actual
defects that are occurring are mapped into a fault model, and
then appropriate tests can be selected for that fault model.
• With memory BIST, the memory testing algorithm is
implemented on-chip, and operates at the speed of the circuit,
which is 2 to 3 orders of magnitude faster than a existing
memory test.
• A 2% chip area overhead for memory BIST can be expected.

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