UNIT-V EC3552-VLSI AND CHIP DESIGN

UNIT V ASIC DESIGN AND TESTING

Introduction to wafer to chip fabrication process flow. Microchip design process & issues in test and
verification of complex chips, embedded cores and SOCs, Fault models, Test coding. ASIC Design
Flow, Introduction to ASICs, Introduction to test benches, Writing test benches in Verilog HDL,
Automatic test pattern generation, Design for testability, Scan design: Test interface and boundary
scan.

Introduction:

 ASIC - Application Specific Integrated Circuit is an Integrated Circuit (IC) designed to perform
a specific function for a specific application.
 Levels of integration:
The levels of integration are:
 SSI - Small scale integration
 MSI - Medium scale integration
 LSI - Large scale integration
 VLSI - Very large scale integration
 USLI - Ultra large scale integration
 Implementation technology
 The implementation technologies used in ASIC are:
 TTL – Transistor Transistor Logic
 ECL – Emitter Coupled Logic
 MOS – Metal Oxide Semiconductor (NMOS, CMOS)
5.1: Types of ASICs

 Explain about different types of ASICs with neat diagram. (April 2016, 2017, 2018)
 Write brief notes on: (a) Full custom ASIC (b) Semi custom ASIC (May 2010, May 2016)
 Compare the different types of ASICs. (Nov 2007, Nov 2008)

 The ASICs are classified as follows:

I. Full-Custom ASICs
II. Semi-custom ASICs
a. Standard-Cell–Based ASICs (CBIC)
b. Gate-Array–Based ASICs (MPGA)
i. Channeled Gate Array
ii. Channelless Gate Array
iii. Structured Gate Array
III. Programmable ASICs
a. Complex Programmable Logic Devices (CPLD)
b. Field-Programmable Gate Arrays (FPGA)

5.1.1:Full-Custom ASICs

Explain the full custom ASICs.

 In full custom ASIC, engineer can design full logic cells in IC. So, this technique is known as
Full custom ASIC technique.
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 Engineer uses mixed analog and digital technique to manufacture IC. All the logic cells are
specifically designed for one ASIC.
Uses of bipolar technology:
 The characteristics of bipolar components in the same IC are matched very well.
 But the characteristic of components in different IC are not matched well
Uses of CMOS:
 This is widely used technology to manufacture IC.
 Mixing of analog and digital function are integrated in the same IC for which CMOS technology
suits well.
 Designers give importance to performance.
 When large volume is manufactured, overall cost will be reduced.
 In super computer, quality is important so this design is implemented.
 All mask layers are customized in a full-custom ASIC
 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
 Critical (timing) paths are usually laid out completely by hand
 Full-custom design offers the highest performance and lowest part cost (smallest die size) for a
given design.
 The disadvantages of full-custom design include increased design time, complexity, design
expense, and highest risk.
 Microprocessors (strategic silicon) were exclusively full-custom, but designers are increasingly
turning to semicustom ASIC techniques in this area as well.

5.1.2: Semi-custom ASICs – Design

 Briefly explain the semi-custom Asics with its classification. (May 2016, NOV 2016)

I. Standard cell based design:

 Standard cells are referred to AND gate, OR gate, multiplexer, flip flop, NOR gate etc.
 Standard cells can be used with larger predefined cells.
 This approach standardizes design entry level at logic gate.
 A design is generated automatically from HDL language.
 Then layout is created. In standard cell design, cells are placed in rows, and rows are separated by
routing channel.
 All cells in library are in identical heights, widths of the cells can be varied to accommodate for
variations in complexity between cells.
 A substantial fraction of area is allotted for signal routing.
 The minimization of interconnect overhead is most important goal of standard-cell placement
routing tools. It is done by feed through cells.
 By using feed through cell, cells in different rows can be connected through vertical routing. So
length of wire is reduced by feed through cells.
Semi-custom ASICs – CBIC
 CBIC means Cell Based ASICs.
 All the mask layers of CBIC are customized.
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 It allows mega cells (SRAM, MPEG, decoder etc) to be placed in the same IC with standard cells
(adder, gates etc).
 Mega cells are supplied by ASIC Company.
 Data path logic means the logic that operates on multiple signals across a data bus.
 Some of the ASIC library companies provide data path compiler which automatically generate data
path logic.
 Data path library contains cells like adders, multiplexer, simple ALUs.
 ASIC Library Company provide data book which has functional description.

Features:
 It is a cell-based ASIC ( CBIC —“sea-bick”)
 It has Standard cells. Standard cell is logic elements used CMOS technology.
 Possibly megacells , megafunctions , full-custom blocks , system-level macros (SLMs), fixed
blocks , cores , or Functional Standard Blocks ( FSBs )
 All mask layers are customized - transistors and interconnect
 Automated buffer sizing, placement and routing. And custom blocks can be embedded.

 A “wall” of standard cells forms a flexible block.

II. Gate Array Based ASICs:

 Explain gate array based ASICs with diagrams. (April 2008, May 2009)
 Gate array is known as GA.
 In GA based ASIC, the transistors are predefined on the silicon wafer.
 Base array: the predefined pattern of transistors on a gate is known as base array.
 Base cell: the small element which is replicated to make the base array is known as base cell or
primitive cell.
 Masked Gate array: Interconnect is defined by using top few layers of metal.
 This type of gate array is known as masked gate array.
 Gate array library is provided by ASIC Company.
 The designer can choose the predefined logic cells from a gate array library. These logic cells are
known as Macros.
 Cell-layout is same for each logic cell. But interconnect is customized.
 It is also called as pre-diffused array because the transistors are diffused at first.
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Types of MPGAs (Mask Programmable Gate Arrays):

 Channeled Gate Array
 Channel less Gate Array
 Structured Gate Array

(a) Channeled Gate Array:

 It is similar to CBIC (cell based ASIC).
 In the both types, rows of cells are separated by channels. These channels are used for
interconnect.
 Space between rows of cells is fixed in a channeled gate array. But space between rows of cells
may be adjusted in a CBIC.
Features:
 Only interconnect is customized.
 The interconnect uses predefined spaces between rows of base cells.
 Manufacturing lead time is between two days and two weeks.

Figure: Channel Gate Array

(b) Channel less Gate Array:
 Channel less Gate Array is also called as channel free GA.
 In this array, there is no predefined space between rows for routing.
 Top few layers are used for defining interconnect connections.
 There are no predefined areas set aside for routing - routing is over the top of the gate-array
devices.
 Achievable logic density is higher than for channeled gate arrays.
 Each logic cell or macro in a gate-array library is predesigned using fixed tiles of transistors
known as the gate-array base cell (or just base cell).

Figure: Channel less Gate Array

 Channeled and channelless gate arrays may use either gate isolation or oxide isolation.
 Isolate the transistors on a gate array from one another either with thick field oxide or by using other
transistors that are wired permanently off.

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(c ) Structured Gate Array:

 Structured Gate Array is also called as embedded gate array or master slice or master image gate.
 It combines some of the features of CBIC and Masked gate array (MGA).
 In this array, some of the area is used for implementation of specially designed embedded block.
 Embedded area either can contain a different base cell that is more suitable for building memory
cells, or a complete circuit block, such as a microcontroller.
Special features:
o Only the interconnect is customized
o Custom block can be embedded
o Manufacturing lead time is 2 days to 2 weeks
o Area efficiency is increased
o Performance is increased with low cost
Disadvantages: the embedded function is fixed.
 For ex: if embedded block has 32K bit memory. But the customer needs only 18K bit,
the 16K memory is wasted.

Figure: Structured Gate Array

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5.2: ASIC Design Flow / Cycle

Explain the ASIC design flow with a neat diagram. (Nov 2007, April 2008, Nov 2008)
Draw the flowchart of digital circuit design techniques. (NOV 2018)

1. Design entry - Using a hardware description language ( HDL ) or schematic

entry
2. Logic synthesis - Produces a netlist - logic cells and their connections
3. System partitioning - Divide a large system into ASIC-sized pieces
4. Prelayout simulation - Check to see if the design functions correctly
5. Floorplanning - Arrange the blocks of the netlist on the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks
8. Extraction - Determine the resistance and capacitance of the interconnect
9. Post layout simulation - Check to see the design still works with the added loads of
the interconnect
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5.3: ASIC Cell Libraries

Explain the standard Cell libraries in ASIC.

Give a note on standard cell design. (Nov 2019)

 The cell library is the key part of ASIC design.

 For a programmable ASIC the FPGA Company supplies a library of logic cells in the form of a
design kit.
 For MGAs and CBICs you have three choices:
 ASIC vendor will supply a cell library, or you can buy a cell library from a third-party library
vendor, or you can build your own cell library.
 The first choice, using an ASIC-vendor library, requires you to use a set of design tools approved by
the ASIC vendor to enter and simulate your design.
 Some ASIC vendors (especially for MGAs) supply tools that they have developed in-house.
 An ASIC vendor library is normally a phantom library the cells are empty boxes, or phantoms, but
contain enough information for layout.
 After you complete layout you hand off a netlist to the ASIC vendor,
 The second and third choices require making a buy-or-build decision.
 If complete an ASIC design using a cell library that you bought, you also own the masks that are
used to manufacture your ASIC. This is called customer-owned tooling.
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 A library vendor normally develops a cell library using information about a process supplied by an
ASIC foundry.
 An ASIC foundry only provides manufacturing, with no design help. If the cell library meets the
foundry specifications, we call this a qualified cell library.
 These cell libraries are normally expensive, but if a library is qualified at several foundries.
 The third choice is to develop a cell library in-house. Many large computer and electronics
companies make this choice.
 However, created each cell in an ASIC cell library must contain the following:
 A physical layout
 A behavioral model
 A Verilog/VHDL model
 Detailed timing models.
 A test strategy
 A circuit schematic
 A cell icon
 A wire-load model
 A routing models.

 The ASIC designer needs a high-level behavioral model for each cell.
 Because simulation at the detailed timing level takes too long for a complete ASIC design.
 The designer may require Verilog and VHDL models in addition to the models for a particular logic
simulator.
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5.4: Library-Cell Design

Explain the important of Library –cell design in detail.

 Design rules for each ASIC vendor are slightly different even for the same generation of technology.
 For example, two companies may have very similar 0.35 nm CMOS process technologies, but the
third-level metal spacing might be slightly different.
 A library constructed in this fashion may not be competitive with one that is constructed specifically
for each process.
 ASIC vendors prize their design rules as secret, it turns out that they are similar except for a few
details.
 We would like all vendors to agree on a common set of design rules.
 The reason that most vendors have similar rules is because most vendors use the same
manufacturing equipment and a similar process.
 Layout of library cells is either hand-crafted or uses some form of symbolic layout.
 Symbolic layout is usually performed in one of two ways: using either interactive graphics or text
layout language.
 Shapes are represented by simple lines or rectangles, known as sticks, in a symbolic layout.
 The actual dimensions of the sticks are determined after layout is completed in a Post processing
step.
 Graphical symbolic layout uses a text layout language, like a programming language such as C that
directs a program to assemble layout.
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CMOS Testing
Explain about Microchip design process.
Microchip design process:
The microchip design process involves several stages from conceptualization to production. Here is an
overview of the typical steps involved:
1. Specification: In this stage, the requirements and functionality of the microchip are defined.
Designers work closely with stakeholders to understand the application and performance targets.

2. Architecture Design: The chip's high-level architecture is developed, including the selection of
components, interconnections, and overall system design. This stage focuses on defining the chip's
functionality and how different components will interact.

3. RTL Design: The Register Transfer Level (RTL) design is created, describing the chip's behavior
using hardware description languages like Verilog or VHDL. RTL design forms the basis for later
stages.

4. Functional Verification: The RTL design is extensively tested to ensure it behaves as intended.
Various verification techniques, such as simulation, formal verification, and hardware emulation, are
employed to catch design bugs and issues.

5. Synthesis and Physical Design: The RTL code is synthesized into a gate-level netlist, which
represents the chip's physical implementation. The physical design phase involves floor planning,
placement, routing, and optimization to meet timing and area constraints.

6. Design for Testability (DFT): Techniques like scan chains, built-in self-test (BIST) structures, and
boundary scan are added to make the chip more testable during manufacturing and in the field.

7. Manufacturing: The final design is sent to a semiconductor foundry for fabrication. This process
involves photolithography and other steps to create the actual silicon chip.

8. Testing and Quality Assurance: After manufacturing, the chips undergo various testing
methodologies to ensure they meet the desired specifications and are free from defects.
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Explain the Issues in Test and Verification of Complex Chips, Embedded Cores, and SoCs:

Issues in Test and Verification of Complex Chips, Embedded Cores, and SoCs:

1. Complexity: As chips and systems-on-chip (SoCs) become more complex, the verification effort
increases exponentially. Ensuring all possible scenarios and corner cases are covered in testing becomes
challenging.

2. Verification Time and Cost: With the growing complexity, the time and cost required for functional
verification can become substantial.

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3. Integration Testing: Integrating various IP cores and subsystems onto a single chip or SoC
introduces new challenges in testing the interactions between these components.

4. Power and Clock Domains: Handling multiple power domains and clock domains in a chip requires
careful verification to ensure proper functionality and minimize power consumption.

5. Performance Verification: Ensuring that the chip operates at the desired performance levels under
all conditions and workloads is crucial, especially for high-performance chips.

6. Test Generation: Generating effective and efficient test patterns to cover various fault models is a
non-trivial task, especially for complex designs.

7. Debugging: Identifying and debugging issues in large and complex designs can be time-consuming
and requires advanced debugging techniques.

Fault Models:

Fault models are representations of potential defects that can occur in a chip or design. Common fault
models include:

1. Stuck-at Faults: These faults assume that a particular node in the circuit is stuck at either '0' or '1'.

2. Transition Delay Faults: These faults model timing-related issues, where a signal changes too
slowly or too fast.

3. Path Delay Faults: These faults model delays along specific paths in the circuit.

4. Bridge Faults: These faults represent a short circuit between two nets or nodes.

5. Cell-Aware Faults: These are specific to certain types of cells and are critical for nanometer-scale
technologies.

Test Coding:

Test coding involves writing test patterns to test the functionality and detect faults in a chip. Various
methods and languages can be used for test coding, such as:

1. ATPG (Automatic Test Pattern Generation): ATPG tools automatically generate test patterns
based on fault models.

2. BIST (Built-In Self-Test): BIST structures are embedded within the chip to facilitate self-testing.

3. Scan Chains: These enable efficient testing by serially scanning in test data and capturing results.

4. Testbenches: Testbenches are used for simulation-based verification, where test stimuli are applied to
the design, and responses are analyzed.
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5. High-Level Test Languages: Some specialized languages and tools are used for high-level test
descriptions, which can be automatically converted to lower-level test patterns.

 In conclusion, designing and testing complex chips, embedded cores, and SoCs require a
thorough understanding of various verification techniques, fault models, and test coding
methods.
 As technology continues to advance, the challenges in test and verification continue to evolve,
demanding innovative solutions and methodologies.

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Explain about the test benches.
Introduction to test benches:

 Test benches are an essential part of digital hardware and software development, especially in
the field of electronic design automation (EDA). They play a crucial role in verifying and
validating the functionality of digital circuits, integrated circuits (ICs), and other electronic
systems.
 A test bench serves as a virtual environment in which designers can simulate the behavior of
their design, apply test stimuli, and observe the responses to ensure the correctness and
functionality of the design before it is physically implemented or manufactured.

Here's an introduction to test benches:

1. Purpose: The primary purpose of a test bench is to thoroughly test the functionality of a digital
design or electronic system before its physical implementation. It allows designers to catch and fix
design errors and functional bugs in a controlled, simulated environment, reducing the risk of costly and
time-consuming errors in the final product.

2. Simulation Environment: A test bench is created as a separate entity from the actual design being
tested. It provides an environment that emulates the behavior of the design under test (DUT) and
contains the necessary stimuli to drive inputs and monitor outputs.

3. Simulation Types: Test benches are used in various types of simulations, such as functional
simulation, timing simulation, and power analysis. Each type of simulation focuses on different aspects
of the design and provides valuable insights into its behavior.

4. Test Stimuli: In a test bench, test stimuli are applied to the inputs of the DUT to simulate different
scenarios and conditions. These stimuli can be pre-defined patterns, random data, or specific corner
cases to test the design's robustness.

5. Output Monitoring: The test bench also includes monitors that observe and record the DUT's
outputs during the simulation. This allows designers to compare the expected outputs with the actual
outputs to check for correctness.

6. Debugging and Analysis: Test benches facilitate debugging by providing detailed information about
the DUT's behavior during simulation. Designers can analyze the waveform results to pinpoint errors
and verify that the design meets the required specifications.

7. Languages and Tools: Test benches are typically written using hardware description languages
(HDLs) like Verilog or VHDL. There are also higher-level verification languages, like SystemVerilog,
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which provide more advanced features for test bench creation. EDA tools such as simulation tools (e.g.,
ModelSim, VCS) and hardware description and verification languages make the process of test bench
creation more efficient and manageable.

8. Coverage Analysis: Test benches are instrumental in evaluating the functional coverage, code
coverage, and other metrics to assess the effectiveness and completeness of the tests.

9. Regression Testing: As designs evolve, test benches can be used for regression testing, ensuring that
any new changes or optimizations do not introduce new errors or regressions in the design.

 In summary, test benches are an integral part of the hardware and software development process,
enabling designers to validate and verify digital designs through simulation.
 They are crucial for achieving high-quality, bug-free, and robust designs, leading to reduced
development time and costs while ensuring the functionality and reliability of the final product.
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1. Explain the following: (NOV 2012)

(i) Silicon debug principles. (MAY 2013, MAY 2014)
(ii) Fault models

Silicon debug principles

 A major challenge in silicon debugging is when the chip operates incorrectly. There are several
techniques for directly accessing silicon.
 Specific signals can be brought to the top of the chip as probe points.
 These are small squares of top-level metal that connect to key points in the circuit.
 The designer has included before debug.
 The over glass cut mask should specify a hole in the passivation over the probe pads so the metal
can be reliably contacted.
 The exposed squares can be probed with a Pico probe in a fixture under a microscope.
 The die can be probed electrically or optically if mechanical contact is not feasible.
 An electron beam (ebeam) probe uses a scanning electron microscope to produce a tightly
focused beam of electrons to measure on-chip voltages.
 Laser Voltage Probing (LVP) involves shining a laser at a circuit and observing the reflected
light. The reflections are modulated by the electric fields so switching waveforms can be
deduced.
 Picosecond Imaging Circuit Analysis (PICA) captures faint light emission naturally produced by
switching transistors.
 Silicon is partially transparent to infrared light, so both LVP and PICA can be performed through
the substrate from the backside of a chip in a flip-chip package.
 Infrared (IR) imaging can be used to examine “hot spots” (a resistive short between power rails)
in a chip.
 There are liquid crystal materials, which can be “painted on” to a die to indicate temperature
problems. If the location of the fault is known, a Focused Ion Beam (FIB) can be used to cut
wires or lay new conductors down.

(a) Types of failures:

 There are three types of failures, manufacturing, functional and electrical failure.
 Manufacturing failures occur when a chip has a defect or is outside of parametric specifications.
 Functional failures are logic bugs or physical design errors that cause the chip to fail under all
conditions.
 Electrical failures occur when the chip is logically correct, but malfunctions under certain
conditions such as voltage, temperature, or frequency.
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(b) Shmoo Plot

 Shmoo plot is used to debug electrical failures in silicon.
 A shmoo plot is a plot with voltage on one axis and speed on the other.
 The test vectors are applied at each combination of voltage and clock speed, and the success of
the test.
is recorded.
 A shmoo can also plot operating speed against temperature.
 At cold temperatures, FETs are faster, have lower effective resistance, and have higher threshold
voltages. Failures at low temperature could indicate coupling or charge sharing noise.
 Failures at high temperatures could indicate excessive leakage or noise problems.

2. Explain the manufacturing test principles in detail. (NOV 2011, NOV 2012, NOV 2013)
Explain the chip level test techniques. (NOV 2007, MAY 2008, NOV 2021)

Manufacturing test principles

 The purpose of the manufacturing test is to screen out the defective parts before they are shipped
to customers.

(a)Fault models
 To deal with the existence of good and bad parts, it is necessary to propose a fault model, i.e., a
model of how faults occur and their impact on circuits.
(i) Stuck at faults.
 In the Stuck-At model, a faulty gate input is modeled as a stuck at zero (Stuck-At-0, S-A-0) or
stuck at one (Stuck-At-l, S-A-l).
 These faults most frequently occur due to gate oxide shorts (the nMOS gate to GND or the
pMOS gate to VDD) or metal-to-metal shorts.

(ii) Short circuit fault

 Two bridging or shorted faults are shown in Figure.
 The short S1 results in an S-A-0 fault at input A, while short S2 modifies the function of the
gate.
 For instance, in the case of a simple NAND gate, the intermediate node between the series
nMOS transistors is hidden by the schematic.
 The probable bridging fault in CMOS circuit can be grouped into three categories. There are
metal polysilicon short, polysilicon n-diffusion short and polysilicon p-diffusion short.

Figure: Bridging fault / Short circuit fault

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(iii) Open circuit fault

 A fault can convert a combinational circuit into a sequential circuit. This is illustrated in Figure
for the case of a 2-input NOR gate.
 If nMOS transistor A is stuck open, then the function displayed by the gate will be
Z  A  B  BZ  where Z  is the previous state of the gate.
 Stuck closed states can be detected by observing the static VDD current (IDD) while applying
test
vectors.

Figure: Open circuit fault

(b) Observability
 The observability of a particular circuit node is the degree to which can observe that node at the
outputs of an integrated circuit (i.e., the pins).
 This metric is relevant, when want to measure the output of a gate within a larger circuit to check
that it operates correctly.
 Given the limited number of nodes that can be directly observed, it is the aim of good chip
designers to have easily observed gate outputs.

(c) Controllability
 The controllability of an internal circuit node within a chip is a measure of the ease of setting the
node to a 1 or 0 state.
 This metric is of importance when assessing the degree of difficulty of testing a particular signal
within a circuit.
 An easily controllable node would be directly settable via an input pad.

(d) Repeatability
 The repeatability of system is the ability to produce the same outputs given the same inputs.
(e) Survivability
 The survivability of a system is the ability to continue function after a fault. For example, error-
correcting codes provide survivability in the event of soft errors.
(f) Fault coverage
 A measure of goodness of a test program depend the amount of fault coverage by the test
program.
 The fault coverage of a set of test vectors is the percentage of the total nodes that can be detected
as faulty when the vectors are applied.
 Each circuit node is taken in the sequence and held to S_a_0, and then simulation started. The
chip’s outputs are compared with outputs of good machine.
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 If the outputs of IC are not matched with the outputs of good, and then fault is marked and the
simulation is stopped.
 The same procedure is repeated to set the node to logic 1. This method is known as sequential
fault grading.
 Fault coverage is defined as ratio of the number of nodes detected as faults and total number of
nodes in the circuit.
(g) Automatic Test Pattern Generation (ATGP)
 If want to test the gate which is embedded in large logic circuit, use existing circuit to create a
specific path from the location of gate which is going to be checked finding fault.
 This technique is known as path sensitization. This process of creating the path is known as
propagation.

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3. Explain with diagram the design strategies for testing the CMOS devices. (NOV 2008, NOV
2009)
Write briefly about different test strategies of testing digital circuits. (MAY 2009)
Explain any two approaches of DFT (Design for Testability) in brief with example. (MAY 2010,
NOV 2009, MAY 2013)[Apr/May 2022]
Explain the three main approaches commonly used for design for testability (DFT). [May 2021]

Design for Testability

 The keys to designing circuits that are testable are controllability and observability.
 Controllability is the ability to set (to 1) and reset (to 0) every node internal to the circuit.
 Observability is the ability to observe, either directly or indirectly, the state of any node in the
circuit.
 Good observability and controllability reduce the cost of manufacturing testing because they
allow high fault coverage with relatively few test vectors.
 Three types of testing are,
 Adhoc testing
 Scan based approaches
 Built -in self -test (BIST)

4. Describe the adhoc testing to design for testability in detail. (NOV 2011) [Nov/Dec 2022]

(a) Adhoc Testing

 Ad hoc test techniques are collections of ideas aimed at reducing the combinational explosion of
testing.
 It is useful for small designs where scan, ATPG, and BIST are not available.
 A complete scan-based testing methodology is recommended for all digital circuits. Common
techniques for ad hoc testing are
 Partitioning large sequential circuits
 Adding test points
 Adding multiplexers
 Providing for easy state reset

 A technique classified in this category is the use of the bus in a bus-oriented system for test
purposes.
 Each register has been made loadable from the bus and capable of being driven onto the bus. The
internal logic values that exist on a data bus are enabled onto the bus for testing purposes.
 The tester can access all the subsystems which are connected by the buses. The tester can
disconnect any functional unit from the bus by setting its output into high impedance state.
 Test pattern for each subsystem can be applied separately.
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 Multiplexers can be used to provide alternative signal paths during testing. In CMOS,
transmission gate multiplexers provide low area and delay overhead.
 Any design should always have a method of resetting the internal state of the chip within a single
cycle or at most a few cycles.
 Apart from making testing easier, this also makes simulation faster as a few cycles are required
to initialize the chip.

5. Explain in detail Scan based test techniques. (NOV 2009)[Nov/Dec 2022]

Describe the scan based approaches to design for testability in detail. (NOV 2011)

(b) Scan based approaches

 The scan-design strategy for testing provides observability and controllability at each register. In
this method, the registers operate in one of two modes are scan mode and normal mode.
 In normal mode, registers behave as expected.
 In scan mode, registers are connected to form a giant shift register called a scan chain spanning
the whole chip.
 By applying N clock pulses in scan mode, all N bits of state in the system can be shifted out and
new N bits of state can be shifted in.
 Therefore, scan mode gives easy observability and controllability of every register in the system.
 Modern scan is based on the use of scan registers, as shown in Figure.

Figure: Scan based testing

 The scan register is a D flip-flop preceded by a multiplexer.
 When the SCAN signal is deasserted, the register behaves as a conventional register, storing data
on the D input.
 When SCAN is asserted, the data is loaded from the SI pin, which is connected in shift register
fashion to the previous register Q output in the scan chain.
 For the circuit to load the scan chain, SCAN is asserted and CLK is pulsed eight times to load the
first two ranks of 4-bit registers with data.
 SCAN is deasserted and CLK is asserted for one cycle to operate the circuit normally with
predefined inputs.
 SCAN is then reasserted and CLK asserted eight times to read the stored data out. At the same
time, the new register contents can be shifted in for the next test.
 The disadvantage is the area and delay impact of the extra multiplexer in the scan register.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

(i) Parallel scan approach

 The serial scan chains can become quite long, and the loading and unloading can dominate
testing time.
 A simple idea is to split the chains into smaller segments.
 This can be done on a module-by-module basis or completed automatically to some specified
scan length.
 This is similar to that used inside FPGAs to load and read the control RAM.
 The figure shows a two-by-two register section. Each register receives a column (column<m>)
and row (row<n>) access signal along with a row data line (data<n>).

Figure: Parallel scan testing

 A global write signal (write) is connected to all registers.

 By asserting the row and column access signals in conjunction with the write signal, any register
can be read or written as conventional RAM.
 Implementing the logic required at the transistor level can reduce the overhead for each register.

(ii) Scannable register design

 An ordinary flip-flop can be made scannable by adding a multiplexer on the data input, as shown
in Figure (a).
 Figure (b) shows a circuit design for such a scan register using a transmission-gate multiplexer.
 The setup time increases by the delay of the extra transmission gate in series with the D input as
compared to the ordinary static flip-flop.

Figure: Scannable flip-flop

(iii) Level sensitive scan design (LSSD)

 During scan mode, the flip-flops are connected back-to-back. Clock skew can lead to hold time
problems in the scan chain.
 These problems can be overcome by adding delay buffers on the SI input to flip-flops.
 Another approach is to use non-overlapping clocks to ensure hold times.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

 The Level Sensitive Scan Design (LSSD) methodology developed at IBM uses flip-flops with
two-phase non-overlapping clocks.
 During scan mode, a scan clock φs is toggled in place of φ2.
 The non-overlapping clocks also prevent hold time problems in normal operation, but increase
the sequencing overhead of the flip-flop.

Figure: LSSD Flipflop

 Alternatively, φ1 and φ2 can be complementary clocks, but φs can be nonoverlapping to prevent
races.
 Figure (c) shows a conventional design using a weak feedback inverter on the master latch that
can be overpowered when either the φ2 or φs transmission gates are on.

6. Explain Built in self-test. (MAY 2008, NOV 2012, NOV 2021)

(c) Build in- Self –Test

(i) Pseudo-random sequence generator

 Self-test and built-in test techniques allow the circuit to perform operations upon themselves that
prove correct operation.
 These techniques add area to the chip for the test logic, but reduce the test time required and thus
can lower the overall system cost.
 One method of testing a module is to use signature analysis or cyclic redundancy checking.
 This involves using a pseudo-random sequence generator (PRSG) to produce the input signals
for a section of combinational circuitry and a signature analyzer to observe the output signals.
 A PRSG of length n is constructed from a linear feedback shift register (LFSR), which in turn is
made of n flip-flops connected in a serial fashion, as shown in Figure (a).
 The XOR of particular outputs are fed back to the input of the LFSR.
 An n-bit LFSR will cycle through 2n–1 states before repeating the sequence. LFSRs are
described by a characteristic polynomial indicating which bits are fed back.
 A complete feedback shift register (CFSR), shown in Figure (b), includes the zero state that may
be required in some test situations.
 n-bit LFSR is converted to an n-bit CFSR by adding an n – 1 input NOR gate connected to all
but the last bit.
 When in state 0…01, the next state is 0…00. When in state 0…00, the next state is 10…0.
Otherwise, the sequence is the same.
 The bottom n bits of an n + 1-bit LFSR can be used to cycle through the all zeros state without
the delay of the NOR gate.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

(Sub)-Circuit

Stimulus Generator Under Response Analyzer

Test

Test Controller

Figure: Pseudo-random sequence generator

 A signature analyzer receives successive outputs of a combinational logic block and produces a
syndrome that is a function of these outputs.
 The syndrome is reset to 0, and then XORed with the output on each cycle.
 The syndrome is swizzled each cycle so that a fault in one bit is unlikely to cancel itself out.
 At the end of a test sequence, the LFSR contains the syndrome that is a function of all previous
outputs.
 This can be compared with the correct syndrome to determine whether the circuit is good or bad.

(ii) Build in- Self –Test (BIST) or Built –In Logic Block Observation (BILBO)
 The combination of signature analysis and the scan technique creates a structure known as
BIST—for Built-In Self-Test or BILBO—for Built-In Logic Block Observation.
 The 3-bit BIST register shown in Figure is a scannable, resettable register that also can serve as a
pattern generator and signature analyzer.

Figure: BIST (a) 3-bit register, (b) use in a system

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UNIT-V EC3552-VLSI AND CHIP DESIGN

 C[1:0] specifies the mode of operation.

 In the reset mode (10), all the flip-flops are synchronously initialized to 0.
 In normal mode (11), the flip-flops behave normally with their D input and Q output.
 In scan mode (00), the flip-flops are configured as a 3-bit shift register between SI and SO.
 In test mode (01), the register behaves as a pseudo-random sequence generator or signature
analyzer.
 If all the D inputs are held low, the Q outputs loop through a pseudo-random bit sequence, which
can serve as the input to the combinational logic.
 If the D inputs are taken from the combinational logic output, they are swizzled with the existing
state to produce the syndrome.

7. Explain how to detect a stuck at fault with examples. (NOV 2012)

IDDQ Testing
 A method of testing for bridging faults is called IDDQ test (VDD supply current Quiescent) or
supply current monitoring.
 When a CMOS logic gate is not switching, it draws no DC current (except for leakage).
 When a bridging fault occurs, then for some combination of input conditions, a measurable DC
IDD will flow.
 Testing consists of applying the normal vectors, allowing the signals to settle, and then
measuring IDD.
 In addition, to be effective, any circuits that draw DC power such as pseudo-nMOS gates or
analog circuits have to be disabled.
 Dynamic gates can also cause problems. As current measuring is slow, the tests must be run
slower than normal, which increases the test time.
 IDDQ testing can be completed externally to the chip by measuring the current drawn on the
VDD line or internally using specially constructed test circuits.
 This technique gives a form of indirect massive observability at little circuit overhead.
 However, as subthreshold leakage current increases, IDDQ testing ceases to be effective
because variations in subthreshold leakage exceed currents caused by the faults.

8. Explain the system level test techniques. (NOV 2007, MAY 2008, NOV 2008)
Explain in detail boundary – scan test. (MAY 2008, MAY 2013, NOV 2013, MAY 2014)

System level testing (Boundary scan testing)

 System defects occur at the board level, including open or shorted printed circuit board traces
and incomplete solder joints.
 At the board level, “bed-of-nails” testers used to test boards.
 In this type of a tester, the board-under-test is lowered onto a set of test points (nails) that probe
points of interest on the board.
 These can be sensed (the observable points) and driven (the controllable points) to test the
complete board.
 At the chassis level, software programs are frequently used to test a complete board set.
 System designers agreeing on a unified scan-based methodology called boundary scan for testing
chips at the board (and system) level.
 Boundary scan was originally developed by the Joint Test Access Group (JTAG)
 Boundary scan has become a popular standard interface for controlling BIST features as well.
 The IEEE 1149 boundary scan architecture is shown in Figure.
 All of the I/O pins of each IC on the board are connected serially in a standardized scan chain
accessed through the Test Access Port (TAP)
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UNIT-V EC3552-VLSI AND CHIP DESIGN

 So that every pin can be observed and controlled remotely through the scan chain.
 At the board level, ICs obeying the standard can be connected in series to form a scan chain
spanning the entire board.
 Connections between ICs are tested by scanning values into the outputs of each chip and
checking that those values are received at the inputs of the chips they drive.
 Moreover, chips with internal scan chains and BIST can access those features through boundary
scan to provide a unified testing framework.

Figure: Boundary scan architecture

 The below figure shows a complete implementation of boundary scan for a chip with four inputs
and four outputs.
 It consists of the TAP controller state machine and state decoder, a 3-bit instruction register with
instruction decode, the bypass register, four boundary scan input pads, and four boundary scan
output pads.
 The other pads comprise the test access port. The boundary scan register control signals
(UpdateDR, ClockDR, ShiftDR, mode_in, and mode_out) are shown as the Control bus.

Figure: Complete Boundary scan implementation

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UNIT-V EC3552-VLSI AND CHIP DESIGN

 Boundary scan testing typically begins with the SAMPLE/PRELOAD instruction. Then, a data
value is preloaded into the boundary scan registers.
 Next, the EXTEST or INTEST instruction is applied to activate the loaded value. Subsequent
data values are shifted into the boundary scan registers and the results of the tests are shifted out.
 The TAP controller is initially reset. At this point, the core logic operates normally with an input
pattern of 0000 and an output pattern of 0001. Then the IR is loaded with 101
(SAMPLE/PRELOAD).
 The data pattern 0111 is shifted in. The IR is loaded with 1000 (INTEST).
 This sends the 0111 pattern to the core logic, producing an output pattern of 0110.
 Finally, the data pattern 1111 is shifted in and the old output 0110 is shifted out.
 Because the INTEST is still active, the 1111 is applied to the core, producing a new output of
1100.
 It provides a uniform interface to single- and multiple-chip testing and circuit-board testing.

The Test Access Port (TAP):

 The Test Access Port has four or five single-bit connections:
 TCK Test Clock Input Clocks tests into and out of the chip
 TMS Test Mode Select Input Controls test operations
 TDI Test Data In Input Test data into the chip
 TDO Test Data Out Output Test data out of the chip; driven only
when TAP
controller is shifting out test data.
 TRST* Test Reset Signal Input Optional active low signal to
asynchronously reset
the TAP controller if no power-up reset
signal is automatically generated by the
chip.
 When the chip is in normal mode, TRST* and TCK are held low and TMS is held high to disable
boundary scan.
 To prevent race conditions, inputs are sampled on the rising edge of TCK and outputs toggle on
the falling edge.
The Test Logic Architecture and Test Access Port:
 The basic test architecture is shown in Figure. It consists of the following:
 The TAP interface pins
 A set of two or more test-data registers (DR) to collect data from the chip
 An instruction register (IR) specifying the type of test to perform
 A TAP controller, which controls the scan of bits through the instruction and testdata
registers

Figure: TAP Architecture

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UNIT-V EC3552-VLSI AND CHIP DESIGN

 The specification requires at least two test-data registers are the boundary scan register and the
bypass register.
 The boundary scan register is associated with all the inputs and outputs on the chip so that
boundary scan can observe and control the chip I/Os.
 The bypass register is a single flip-flop used to accelerate testing by avoiding shifting data into
the boundary scan registers of idle chips.
 When only a single chip on the board is being tested. Internal scan chain, BIST, or configuration
registers can be treated as optional additional data registers controlled by boundary scan.
The TAP Controller:
 The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and
TMS signals.
 It provides signals that control the test-data registers and the instruction register. These include
serial shift clocks and update clocks.
 The state transition diagram is shown in Figure. The TAP controller is initialized to Test-Logic-
Reset on power-up by TRST* or an internal power-up detection circuit.
 It moves from one state to the next on the rising edge of TCK based on the value of TMS.

Figure: TAP controller state diagram

The Instruction Register (IR):

 The instruction register has to be at least 2 bits long. The instruction register specifies which data
register will be placed in the scan chain when the DR is selected.
 It also determines from where the DR will load its value in the Capture-DR state, and whether
the values will be driven to output pads or core logic.
 The following three instructions are required to be supported:
 BYPASS—This instruction places the bypass register in the DR chain so that the path from
TDI to TDO involves only a single flip-flop.
 SAMPLE/PRELOAD—This instruction places the boundary scan registers in the DR chain.
In the Capture-DR state, it copies the chip’s I/O values into the DRs.
 EXTEST—This instruction allows for the testing of off-chip circuitry.
 In addition to these instructions, the following are also recommended:
 INTEST— This instruction allows for single-step testing of internal circuitry via the
boundary scan registers. It is similar to EXTEST.
 RUNBIST— This instruction is used to activate internal self-testing procedures within a
chip.

The Data Register:

 The test data registers are used to set the inputs of modules to be tested and collect the results of
running tests.
 The simplest data register configuration consists of a boundary scan register and a bypass
register (1-bit long).

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UNIT-V EC3552-VLSI AND CHIP DESIGN

Figure: Test Data Register

The Boundary scan register:

 The boundary scan register connects to all of the I/O circuitry.
 It internally consists of a shift register for the scan chain and an additional bank of flip-flops to
update the outputs in parallel.
 An extra multiplexer on the output allows the boundary scan register to override the normal path
through the I/O pad so it can observe and control inputs and outputs.
 The schematic and symbol for a single bit of the boundary scan register are shown in Figure.

Figure: Boundary scan register bit

The Bypass Register:

 When executing the BYPASS instruction, the single-bit Bypass register is connected between
TDI and TDO.
 It consists of a single flip-flop that is cleared during Capture-DR, and then scanned during Shift-
DR.

Figure: Bypass register

*************************************************************
Explain the Writing test benches in Verilog HDL.

Writing test benches in Verilog HDL:

Writing test benches in Verilog HDL involves creating a module that emulates the environment in which
the Design Under Test (DUT) will be tested. Test benches provide stimuli to the DUT's inputs and
monitor its outputs to verify its functionality.

Here's a step-by-step guide on how to write a basic test bench in Verilog:

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UNIT-V EC3552-VLSI AND CHIP DESIGN

1. Module Declaration: Begin by declaring the test bench module, including the module name and any
ports that need to be connected to the DUT.

```verilog
module tb_example;
// Declare the DUT inputs and outputs
// (e.g., input ports and output ports)
// ...

// Declare any internal signals or wires (optional)

// ...

// Instantiate the DUT

// ...

// Test bench code goes here

// ...

endmodule
```

2. Instantiate the Design Under Test (DUT): In the test bench, instantiate the module representing the
DUT. Connect the DUT's input and output ports to the corresponding signals or wires in the test bench.

```verilog
module tb_example;
// Declare the DUT inputs and outputs
// ...

// Declare any internal signals or wires (optional)

// ...

// Instantiate the DUT

DUT_module DUT_inst (
// Connect DUT inputs to test bench signals/wires
.input_signal_1(input_signal_1),
.input_signal_2(input_signal_2),
// ...

// Connect DUT outputs to test bench signals/wires

.output_signal_1(output_signal_1),
.output_signal_2(output_signal_2),
// ...
);

// Test bench code goes here

// ...

endmodule
```

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UNIT-V EC3552-VLSI AND CHIP DESIGN

3. Test Stimuli: Within the test bench, apply test stimuli to the DUT's inputs. This can be done using
initial blocks or always blocks.

```verilog
module tb_example;
// Declare the DUT inputs and outputs
// ...

// Declare any internal signals or wires (optional)

// ...

// Instantiate the DUT

// ...

// Apply test stimuli

initial begin
// Initialize input signals with test values
input_signal_1 = 0;
input_signal_2 = 1;
// ...

// Add delays between input changes (optional)

#5; // Delay of 5 time units

// Change input values during simulation

input_signal_1 = 1;
#10; // Delay of 10 time units
input_signal_2 = 0;

// Add more test cases as needed

// ...

// End the simulation after all test cases have been executed
$finish;
end

// Test bench code goes here

// ...

endmodule
```

4. Output Monitoring: Use `initial` or `always` blocks to monitor and check the DUT's outputs during
simulation. You can use `$display`, `$monitor`, or assertion-based methods for this purpose.

```verilog
module tb_example;
// Declare the DUT inputs and outputs
// ...

// Declare any internal signals or wires (optional)

// ...

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UNIT-V EC3552-VLSI AND CHIP DESIGN

// Instantiate the DUT

// ...

// Apply test stimuli

// ...

// Monitor the DUT outputs

always @(posedge clock) begin
// Display or check DUT outputs during simulation
$display("Output signal 1: %b, Output signal 2: %b", output_signal_1, output_signal_2);

// Add assertions to check specific conditions (optional)

// assert (output_signal_1 == expected_output_1) else $error("Output signal 1 mismatch");
// assert (output_signal_2 == expected_output_2) else $error("Output signal 2 mismatch");
// ...
end

// Test bench code goes here

// ...

endmodule
```

5. Simulating the Test Bench: To simulate the test bench, use a Verilog simulator such as ModelSim,
VCS, or Questa. The simulation will execute the test cases defined in the test bench and display the
results and any assertion failures.

That's a basic outline of writing a test bench in Verilog HDL. Keep in mind that test benches can
become more complex, depending on the complexity of the DUT and the desired test scenarios.
Advanced test benches may include random stimulus generation, coverage analysis, and other
verification methodologies to thoroughly validate the DUT's functionality.

*******************************************

Explain about Automatic Test Pattern Generation

Automatic Test Pattern Generation:
Automatic Test Pattern Generation (ATPG) is a crucial technique in semiconductor testing and
verification. It involves generating a set of test patterns automatically to detect and diagnose faults or
defects in a digital integrated circuit or design. The generated test patterns are applied to the design
under test (DUT) during manufacturing testing or in-field testing to ensure its functionality and
reliability. Here's an overview of how ATPG works:

1. Fault Modeling: The first step in ATPG is to create a fault model that represents the potential defects
or faults in the DUT. Common fault models include stuck-at faults, transition faults, path delay faults,
and bridging faults. Each fault model describes a specific type of fault that can occur in the DUT.

2. Design Representation: The DUT's design is represented at the gate level, typically in the form of a
gate-level netlist. The netlist contains information about the gates, their connections, and the logical
behavior of the design.

3. Test Cube: A test cube represents the inputs and outputs of the DUT that are relevant to testing a
specific fault. It specifies the input patterns needed to activate the fault and the expected output
responses. The ATPG tool generates test patterns based on these test cubes.
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UNIT-V EC3552-VLSI AND CHIP DESIGN

4. Algorithmic Generation: ATPG algorithms employ different techniques to automatically generate

test patterns. Some popular algorithms include the D-algorithm, the Path Sensitization algorithm, and the
Boolean Satisfiability (SAT) solver-based algorithms. These algorithms consider the fault models and
the design's structure to generate effective test patterns.

5. Test Generation Flow:

a. The ATPG tool reads the DUT's gate-level netlist and the fault model.
b. It identifies target faults that need to be tested based on the fault model.
c. ATPG applies different algorithms to identify test cubes that activate each target fault.
d. For each test cube, the ATPG tool generates input patterns and expected output responses, creating
test patterns for the target faults.
e. The generated test patterns are saved in a test vector format (e.g., STIL, WGL) or other formats
suitable for test equipment.

6. Simulation and Verification: The generated test patterns are then applied to the DUT in a simulation
environment or during manufacturing testing. The DUT's responses are compared with the expected
outputs to detect any faults. If the DUT fails the test, the specific fault(s) that caused the failure can be
identified for further diagnosis and debugging.

ATPG is a powerful technique that significantly improves the efficiency and coverage of semiconductor
testing. It helps ensure the quality and reliability of integrated circuits, enabling the detection of
manufacturing defects and design errors, thereby enhancing the overall product yield and performance.

*******************************************************

Explain the Process involved in wafer to chip fabrication.

Introduction to wafer to chip fabrication process flow

 Wafer to chip fabrication, also known as semiconductor manufacturing, is the process of

transforming a silicon wafer into individual semiconductor chips or integrated circuits (ICs).
 The process involves a series of steps that are meticulously executed in a cleanroom environment
to ensure the highest possible quality and yield.

Here's an overview of the typical wafer to chip fabrication process flow:

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UNIT-V EC3552-VLSI AND CHIP DESIGN

1. Wafer Ingot Growth: The process begins with the growth of a silicon ingot. The silicon ingot is
sliced into thin, circular wafers using a diamond-tipped saw. These wafers serve as the base material for
manufacturing chips.

2. Wafer Cleaning: The wafers undergo rigorous cleaning processes to remove any contaminants or
particles that might have accumulated during handling or previous steps. Cleanliness is crucial to ensure
defect-free manufacturing.

3. Oxidation: The wafers are exposed to high-temperature oxygen or steam to create a thin layer of
silicon dioxide (SiO2) on their surface. This layer serves as an insulating material and also provides a
base for subsequent processes.

4. Photolithography: In this step, a photoresist material is applied to the wafer's surface. Light is then
shone through a photomask that contains the pattern of the desired circuit. The photoresist is exposed to
this patterned light, creating a mask on the wafer. This process defines the circuit pattern for the
subsequent steps.

5. Etching: The exposed parts of the wafer's surface are either removed or modified using chemical or
physical etching processes. This step transfers the pattern from the photomask onto the wafer, defining
the circuit layout.

6. Doping: Dopants (impurity atoms) are selectively introduced into specific areas of the wafer to
modify its electrical properties. This process creates regions with either excess or deficient electrons,
forming the various components of transistors (source, drain, gate, etc.).

7. Thin Film Deposition: Thin films of various materials, such as metal, polysilicon, or insulators, are
deposited onto the wafer surface using techniques like chemical vapor deposition (CVD) or physical
vapor deposition (PVD). These films serve as conductors or insulators in the circuit.

8. Chemical Mechanical Polishing (CMP): CMP is used to planarize the wafer's surface, making it
smooth and even. This is essential for accurate layering and subsequent processing steps.

9. Annealing: The wafer is heated in a controlled environment to activate dopants, repair crystal
damage, and improve the electrical properties of the fabricated components.

10. Chemical Mechanical Polishing (CMP): CMP is used to planarize the wafer's surface, making it
smooth and even. This is essential for accurate layering and subsequent processing steps.

11. Annealing: The wafer is heated in a controlled environment to activate dopants, repair crystal
damage, and improve the electrical properties of the fabricated components.

12. Testing: Throughout the process, various tests are conducted to ensure the quality of the chips being
manufactured. These tests help identify defects and ensure that the chips meet the required
specifications.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

13. Packaging: Once all the chips on the wafer are deemed functional, they are separated and assembled
into their respective packages. The packages provide protection and electrical connections to the chips,
enabling them to be mounted on printed circuit boards (PCBs).

14. Final Testing: After packaging, the chips undergo final testing to verify their functionality and
performance. Defective chips are discarded, and only fully functional chips are sent for distribution and
integration into electronic devices.

 It's important to note that the above process is a simplified overview, and the actual fabrication
process can be much more complex, involving multiple iterations of the steps to create multiple
layers and intricate circuitry on a single chip.
 Semiconductor manufacturing is a continuously evolving field, with advancements in technology
and miniaturization constantly pushing the boundaries of what is possible.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

TWO MARK QUESTIONS & ANSWERS

UNIT V - ASIC DESIGN AND TESTING
1. List out the Implementation technologies in ASIC.
The implementation technologies used in ASIC are:
TTL – Transistor Transistor Logic
ECL – Emitter Coupled Logic
MOS – Metal Oxide Semiconductor (NMOS, CMOS)

2. What are the types of ASICs?

The ASICs are classified as follows:

I. Full-Custom ASICs
II. Semi-custom ASICs
a. Standard-Cell–Based ASICs (CBIC)
b. Gate-Array–Based ASICs (MPGA)
 Channeled Gate Array
 Channel less Gate Array
 Structured Gate Array
III. Programmable ASICs
a. Complex Programmable Logic Devices (CPLD)
b. Field-Programmable Gate Arrays (FPGA)

3. What is meant by Full-Custom design? (May 2009)

 All mask layers are customized in a full-custom ASIC

 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
 Critical (timing) paths are usually laid out completely by hand.

4. What are the features of Full-Custom ASICs? (May 2016)

List the advantages of Full-Custom ASICs.
 Full-custom design offers the highest performance, minimizes its area and lowest part cost
(smallest die size) for a given design.

5. What are the disadvantages of Full-Custom ASICs?

The disadvantages of full-custom design include increased design time, complexity, design
expense, and highest risk.

6. Give examples of Full-Custom ASICs.

 Microprocessors (strategic silicon) were exclusively full-custom, but designers are

increasingly turning to semicustom ASIC techniques in this area as well.
 Other examples of full-custom ICs or ASICs are requirements for high-voltage (automobile),
analog/digital (communications), sensors and actuators, and memory (DRAM)

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UNIT-V EC3552-VLSI AND CHIP DESIGN

7. What are Semi-custom ASICs?

 Semi-custom ASIC is a cell-based ASIC (CBIC — “sea-bick”)

 It has Standard cells.
 Possibly megacells, megafunctions, full-custom blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks (FSBs)
 All mask layers are customized - transistors and interconnect.

8. What is meant by standard cell?

A standard cell is a group of transistors and interconnect structure that provides a Boolean logic
function (e.g., AND, OR, XOR, Inverter) or a function (flip-flop or latch).

9. What is the standard cell-based ASIC design? (Nov 2016)

 In semiconductor design, standard cell methodology is a method of designing
application-specific integrated circuits with digital logic features.
 A standard cell is a group of transistors and interconnect structure that provides a
Boolean logic function (e.g., AND, OR, XOR, Inverter) or a function (flip-flop or latch).

10. What is meant by CBIC? (Nov 2009, April 2017)

Cell-Based Integrated Circuit consists of standard cells. CBIC based circuit is fixed and
cannot be reconfigured.

11. What is Channeled Gate Array?

 Only the interconnect is customized.
 The interconnect uses predefined spaces between rows of base cells.
 The manufacturing lead time is between two days and two weeks

12. What is Channel less Gate Array?

 There are no predefined areas set aside for routing - routing is over the top of the gate-array
devices
 Achievable logic density is higher than for channeled gate arrays
 Manufacturing lead time is between two days and two weeks

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UNIT-V EC3552-VLSI AND CHIP DESIGN

13. What is Structured Gate Array?

 Only the interconnect is customized
 Custom blocks (the same for each design) can be embedded
 These can be complete blocks such as a processor or memory array
 An array of different base cells better suited to implementing a specific function
 Manufacturing lead time is between two days and two weeks.

14. What is Ratio factor?

The ratio factor is the relative balance between the two partitions with respect to cell area.
It is used to prevent all cells from clustering into one partition.
The ratio factor r is defined as
area( A)
r
area( A)  area( B)
where area(A) and area(B) are the total respective areas of partitions A and B

15. Write the Goals and Objectives of floor planning?

The goals of floor planning are to:
 arrange the blocks on a chip,
 decide the location of the I/O pads,
 decide the location and number of the power pads,
 decide the type of power distribution, and
 decide the location and type of clock distribution.
 The objectives of floor planning are to minimize the chip area and minimize delay.
 Measuring area is straightforward, but measuring delay is more difficult.

16. What is Channel Definition?

During the floorplanning step, we assign the areas between blocks that are to be used for
interconnect. This process is known as channel definition or channel allocation.

17. What is placement?

 After completing a floorplan, we can begin placement of the logic cells within the flexible
blocks.
 Placement is much more suited to automation than floor planning.
 Thus we shall need measurement techniques and algorithms.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

18. What are the different placement algorithms in ASIC.

There are two classes of placement algorithms commonly used in commercial CAD tools:
constructive placement and iterative placement improvement.

19. What is synthesis?

The initial synthesis contains little or no information on any interconnect loading. The output of
the synthesis tool is the input to the floor planner.
20. What is Timing-driven placement?
After placement using constraints from the synthesis tool, the location of every logic cell on the
chip is fixed and accurate estimates of interconnect delay can be passed back to the synthesis
tool.
21. What is Routing?
Once the designer has floor planned a chip and the logic cells within the flexible blocks have
been placed, it is time to make the connections by routing the chip.
22. What are the two different types of routing? (April 2018)
Two types of routing are Global routing and Hierarchical routing.
23. What is Global Routing?
A global router does not make any connections, it just plans them. We typically global route the
whole chip before detail routing the whole chip (or the pieces).

24. What are the methods of Global Routing?

 Sequential routing
 Order-independent routing
25. What is hierarchical routing?
Hierarchical routing handles all nets at a particular level at once. Rather than handling all of the
nets on the chip at the same time.
26. What is Reserved-layer routing?
Reserved-layer routing restricts all interconnects on each layer to flow in one direction in each
routing area.

27. What is Special Routing?

The routing of nets that require special attention, clock, and power nets for example, is normally
done before detailed routing of signal nets.

28. What is meant by standard cell library? (NOV 2016)

What is the role of cell libraries in ASIC design? (April 2018)
 The cell library is the key part of ASIC design.
 For a programmable ASIC the FPGA Company supplies a library of logic cells in the
form of a design kit.

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29. What are the models should have in a cell library?

Each cell in an ASIC cell library must contain the following:
 A physical layout
 A behavioral model
 A Verilog/VHDL model
 A detailed timing model
 A test strategy
 A circuit schematic
 A cell icon
 A wire-load model
 A routing model
30. What is meant by library cell design?
 Layout of library cells is either hand-crafted or uses some form of symbolic layout.
 Symbolic layout is usually performed in one of two ways: using either interactive
graphics or a text layout language.
 Shapes are represented by simple lines or rectangles, known as sticks or logs , in
symbolic layout.
31. List out the basic elements of the FPGA structure.
State the three important blocks in FPGA architecture. (April 2019)
State the building blocks of FPGA. (Nov 2019)
The basic elements of FPGA structure are:

1.Logic blocks
 Based on memories (LUT – Lookup Table) Xilinx
 Based on multiplexers (Multiplexers) Actel
 Based on PAL/PLA (PAL - Programmable Array Logic, PLA – Programmable Logic Array)
Altera
 Transistor Pairs
2. Interconnection Resources
 Symmetrical FPGA-s
 Row-based FPGA-s
 Sea-of-gates type of FPGA-s
 Hierarchical FPGA-s (CPLD)
3. Input-output cells (I/O Cell)
32. Name the elements in a Configuration Logic Block. (April 2017)

Configuration Logic blocks:

 Memories (LUT – Lookup Table, Flip-flop) - Xilinx
 Multiplexers -Actel
 PAL/PLA (PAL - Programmable Array Logic, PLA – Programmable Logic Array) - Altera
 Transistor Pairs
33. Write the features of Xilinx FPGA. (April 2008)

The features of Xilinx FPGA are:

 High-performance
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UNIT-V EC3552-VLSI AND CHIP DESIGN

-5 ns pin-to-pin logic delays on all pins

 Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates
 5 V in-system programmable
 Endurance of 10,000 program/erase cycles

34. Give the functions of Input Output Block.

 The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins.
 Each IOB includes an input buffer, output driver, output enable selection multiplexer, and
user programmable ground control.

35. Write about various ways of routing procedure. (Nov 2017)

 Hierarchical Routing Architecture
 Island-Style Routing Architecture
 Xilinx Routing Architecture
 Altera Routing Architecture
 Actel Routing Architecture

36. What is VLSI and ULSI? (Nov 2017)

Very large-scale Integration:
Very large-scale Integration (VLSI) with gates counting upto lakhs.
Ultra large-scale Integration:
Ultra large-scale integration (ULSI) is the process of integrating millions of transistors on a
single silicon semiconductor microchip.

37. What is feed through cells? State their uses. (May 2016)
A Feed through is a connection that needs to cross over a row of standard cells.
Feed through cells needed for vertical routing for routing using the same metal layer(s) as within
cells.

38. What is a programmable logic device?

A programmable logic device (PLD) is an electronic component used to build reconfigurable
digital circuits.
Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of
manufacture.

39. What are the types of programmable logic device (Programmable ASIC)?
 PLA
 PAL
 FPGA
40. What is meant by ASIC?
Application Specific Integrated Circuit is an Integrated Circuit (IC) designed to perform a
specific function for a specific application.
41. What is an antifuse? State its merits and demerits. (Nov 2016)
 Antifuse is nothing high resistance (>100 MΩ) is changed into low resistance(200-500Ω) by
applying programming voltage.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

 Merit: Antifuses separate interconnect wires on the FPGA chip and the programmer blows
an antifuse to make a permanent connection.
 Demerit: Once an antifuse is programmed, the process can’t be reversed.

42. What is PLA?

Programmable logic arrays (PLAs) is a type of fixed architecture logic devices with
programmable AND gates followed by programmable OR array.

Figure: Programmable logic array

43. What is PAL?
The PAL is a programmable logic device with a fixed OR array and a programmable AND array.

Figure: Programmable Array Logic

44. What are the types FPGA programming technologies?
What are the different types of programming structure available in PAL? (Nov 2008)
There are three types of programming technology.
 Fusible link programming (Anti fuse)
 SRAM Programming
 EPROM and EEPROM programming

45. What is meant by Reprogrammable Gate array (FPGA)?

What is the significance of field programmable gate arrays? [May 2021][Apr/May 2022]
A field programmable gate array (FPGA) is a VLSI circuit that can be programmed at the
user’s location.
A typical FPGA consists of an array of millions of logic blocks, surrounded by
programmable input, and output blocks and connected together via programmable
interconnections.
46. Differentiate between Full custom and Cell based ASICs. (April 2008)
Full Custom ASICs:
 All mask layers are customized in a full-custom ASIC
 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
Cell based ASICs:
 It has Standard cells, Possibly mega cells, mega functions, full-custom blocks, system-
level macros (SLMs), fixed blocks, cores or Functional Standard Blocks
 All mask layers are customized - transistors and interconnect.

47. What is needed for testing? [Nov/Dec-2013] [Apr/May-2008]

Physical defects are likely in manufacturing.
– Missing connections (opens)
– Bridged connections (shorts)
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UNIT-V EC3552-VLSI AND CHIP DESIGN

– Imperfect doping, processing steps

– Packaging
Need to weed out bad die before assembly. Need to test during operation – Electromagnetic
interference, mechanical stress, electromigration, alpha particles.

48. What are different stages of testing on a chip? [Nov/Dec-2012]

Different stages of testing are wafer level, circuit level, chip level, board level, field level, logic
level.

49. What is meant by tester in VLSI testing?

A tester is a device that can apply a sequence of stimuli to a chip or system under test and record
the results.

50. Distinguish testers and test fixtures. [Nov/Dec-2012]

Testers: equipment used for testing.
Test fixtures: components through which the equipment’s are connected with testing block.

51. State all the test vectors to test 3 input NAND gate. [May/June-2009]
Three inputs test vector are 000, 001, 010, 011, 100, 101, 110 and 111.

52. What are the test fixtures required to test a chips? [Nov/Dec-2011]

To test a chip, various types of test fixtures may be required. These are
 Probe card: It is used to test at the wafer level or unpackaged die level with a chip tester.
 Load board: It is used to test a packaged part with a chip tester.
 Printed circuit board (PCB): It is used for bench-level testing (with or without a tester).
 PCB with the chip in situ: It is used for demonstrating the system application for which the
chip is used.
53. What is meant by test program?
The tester requires a test program. This program is written in a high-level language that supports
a library of primitives for a particular tester.

54. What is handler?

Used for feeding Ics to a test fixture which is attached to a tester? It has mechanical positioning
equipment. Status is indicated at the top, to check if the handler is functioning or not. It can
handle 2 to 4 chips at a time.

55. How is testing classified?

List out the basic types of CMOS testing (or) What are the different types of CMOS
testing? [May/June-2013] [Nov/DEC-2008]
The basic types of CMOS testing are functionality testing and Manufacturing testing.

56. What is functionality test?

State the objective of functionality test. [Nov/Dec-2011]

Functionality test is to check whether logic block works with correct logic. It leads to
imperfection of logic function. It is done before fabrication process.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

57. What is manufacturability test?

Manufacturing test is to check is there any defects occurred in circuit after fabrication process. It
leads to nodes to float, shorted to power or ground. It is done after fabrication process.

58. Distinguish functionality test and manufacturing test. [Nov/Dec-2007]

Functionality: Functionality test is to check whether logic block works with correct
logic. It leads to imperfection of logic function. It is done before the fabrication process.
Manufacturing: Manufacturing test is to check is there any defects occurred in circuit
after fabrication process. It leads to nodes to float, shorted to power or ground. It is done after
fabrication process.

59. What is the principle behind logic verification? [Nov/Dec-2013]

Verifying the logical principles of the circuit by the following ways:
Test benches & Harness, Regression testing, Version control and Bug tracking.

60. Define test benches and harness.

A verification test bench or harness is a piece of HDL code.
In the simplest test bench, input vectors are applied to the module under test and at each cycle,
the outputs are taken and compared with the output of another model.

61. What is shmooing?

The ability of varying the voltage and timing on a per-pin basis with a tester allows a process
known as shmooing.
62. What is shmooing plots?
In this plot, voltage is taken in x-axis and speed is taken in y-axis. The test vectors are applied
and the output is recorded.
63. What is VCD?
Vector Change Description - It is used to compact stimulation results.

64. What is version control?

It is used in regression testing. It is orderly management of different design iterations.

65. What is regression testing?

Stimulation performed automatically. Verify that no functionality has changed in a model.
Regression conducted after design activities every day.

66. What is meant by Bug tracking?

Bug tracking is nothing but allows the management of wide variety of Bugs(error checks).

67. What is meant by silicon debugging principles and name some probes used for it?
Silicon debugging principles are those technique which can directly access the silicon for testing.
LVP-Laser Voltage Probing, PICA-Picasecond Imaging Circuit Analysis.

68. What is hotspot and how it is examined?

Hotspots are examined using infrared imaging techniques.

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69. How the temperature is examined in a chip?

Liquid Crystal material can be painted to a die to identify the temperature related problems.
70. What is FIB?
Focused Ion Beam (FIB): If the fault locations are identified, then FIB can be used to cut wires
(or) lay new conductors down.

71. What is electrical failure?

Electrical failur occurs if the chip is logically correct but malfunctions occur due to temperature.

72. What is struck at fault? [Nov/DEC-2008]

If any input line is struck at logic ‘0’ or logic ‘1’ permanently called as struck at fault. If it struck
at logic ‘1’ then called as struck-at-1 or s-a-1 and if it struck at logic ‘0’ then called as struck-at-0
or s-a-0.

73. What is struck open fault? [Nov/DEC-2008]

Due to defects while manufacturing leads to permanent disconnect of drain to source terminal
called as struck open fault.

74. What is bridging fault or short circuit fault?

Due to defects while manufacturing leads to shorting of inputs between themselves or shorting of
inputs to outputs(feedback) occurs called as bridging fault.

75. List any two faults that occur during manufacturing. [Nov/DEC-2008]
Struck at faults and struck open fault.

76. Define fault coverage?

Fault coverage is defined as ratio of the number of nodes detected as faults and total number of
nodes in the circuit.
Total no. of nodes in which fault identified
Fault coverage = ----------------------------------------------------------------
Total no. of nodes in circuit

77. How is the bridging fault categorized?

Bridging faults are categorized as
Input bridging
Feedback bridging
Non-feedback bridging

78. What is observability? [Nov/Dec 2022]

The observability of a particular circuit node is the degree to which we can observe that node at
the outputs of an integrated circuit.
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79. What is controllability? [Nov/Dec 2022]

The measure of ease of forcing/setting a node to 0 or 1 by driving input pins of the chip is called
controllability.

80. What is meant by ATPG?

Automatic Test Pattern Generation (ATPG) – Block generates input patterns automatically by
itself for testing its own logic block and stores the output pattern and compare it with defined
pattern for error identification.

81. What are the 3 approaches in design for testability? (or) List out design required for
testing in CMOS chip design. [Apr/May-2008]
Three approaches in design for testability are
Adhoc testing
Scan based testing
BIST- Built In Self Test

82. What do you mean by DFT? [Nov/Dec-2009]

Good observability and controllability reduce the cost of manufacturing testing because they
allow high fault coverage with relatively few test vectors.
Three main approaches to what is commonly called Design for Testability
(DFT). These may be categorized as follows:
Adhoc testing
Scan based testing
BIST- Built In Self Test
83. What is serial scan & parallel scan?
In serial scan based approaches, logic is connected to form a giant shift register called as a scan
chain spanning the whole chip.
In parallel scan based approaches, logic is split the chain into smaller segments. This can be done
on a module –by-module basis or completely automatically to some specified scan length.

84. List the common techniques for ad hoc testing. (NOV 2021)
1. Buddy testing 2. Pair testing 3. Monkey testing
85. What is signature analyzer?
Signature analyzer is a block which observes the output signal.

86. What is the drawback of scan based approaches?

Drawbacks of scan based approaches are area and delay impact of the extra multiplexer in the
scan register.

87. What is the aim of Adhoc test techniques?[Nov/Dec-2007] [Apr/may-2010]

Ad hoc test techniques are collections of ideas aimed at reducing the combinational explosion of
testing. They are only useful for small designs where scan, ATPG, and BIST are not available. A
complete scan-based testing methodology is recommended for all digital circuits.

88. What is the MUX test technique?

Multiplexers can be used to provide alternative signal paths during testing. In CMOS,
transmission gate multiplexers provide low area and delay overhead.
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UNIT-V EC3552-VLSI AND CHIP DESIGN

89. Write a note on partition and MUX technique

What are common techniques used in adhoc testing? [Apr/May-2011]
(i) Partitioning large sequential circuits
(ii) Adding test points
(iii) Adding multiplexers (iv) Storing output datas

90. What are scannable elements for circuit design?

Mutliplexer, Flipflop and CMOS transmission gates are scannable elements in circuit design.

91. What is the necessary for non-overlapping clocks?

The non-overlapping clocks in LSSD prevents hold time problems in normal operation, but
increase the sequencing overhead of the flipflop.

92. What is syndrome?

Syndrome is output pattern generated for the applied input pattern in testing.

93. What is LSSD?

Level Sensitive Scan Design : In this method, flipflops with two phase non-overlapping clocks
are used in testing circuit.

94. What is BIST or BILBO?

The Combination of scan technique with PRSG & signature analysis creates a structure called as
Built-in Logic Block Observer (BILBO).

(Sub)-Circuit

Stimulus Generator Under Response Analyzer

Test

Test Controller

95. What is needed for IDDQ testing? [Apr/May-2011] [Apr/May-2010]

List out design guidelines for IDDQ testing.
A method of testing for bridging faults is called IDDQ test (VDD supply current Quiescent) or
supply current monitoring. This relies on the fact that when a CMOS logic gate is not switching,
it draws no DC current (except for leakage).
When a bridging fault occurs, then for some combination of input conditions, a measurable DC
IDD will flow. Testing consists of applying the normal vectors, allowing the signals to settle, and
then measuring IDD.

96. What are the limitations of IDDQ testing?(NOV 2021)[Apr/May 2022]

Compared to scan chain testing, IDDQ testing is time consuming and more expensive.
97. What is meant by system level (Boundary scan) testing?
System designers agree on a unified scan-based methodology called boundary scan for testing
chips at the board (and system) level.
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UNIT-V EC3552-VLSI AND CHIP DESIGN

98. Draw the boundary scan input logic diagram. [Nov/Dec-2009]

99. What is TAP?

All the input and output pins of each IC on the board are connected serially in a standardized
scan chain accessed through the TAP (Test Access Port), so that every pins can be observed and
controlled remotely through the scan chain.
100. What are the signals used in Tap Access port (TAP)?
The Test Access Port has four or five single-bit connections:
TCK Test Clock Input Clocks tests into and out of the chip
TMS Test Mode Select Input Controls test operations
TDI Test Data In Input Test data into the chip
TDO Test Data Out Output Test data out of the chip; driven only when TAP
controller is shifting out test data.
TRST* Test Reset Signal Input Optional active low signal to asynchronously
reset the TAP controller if no power-up reset signal is automatically generated by the chip.
101. Draw the Tap Access port (TAP) architecture.

Figure: TAP Architecture

102. What is meant by TAP controller?
The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK
and TMS signals.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

103. What is bypass register?

Single bit register connected between Test Data In (TDI) and Tata Data Out (TDO). It is
cleared during capture- DR, and then scanned during shift Data Read (DR).

Figure: Bypass register

104. What is instruction register?

Instruction register is a 2 bit register which specifies which data register will be placed in
the scan chain when DR – data register is selected.

105. What is Data Register (DR)?

The test data registers are used to set the inputs of modules to be tested and collect the results of
running tests.

Figure: Test Data Register

106. What is boundary scan register?
The boundary scan register connects to all of the I/O circuitry. It internally consists of a
shift register for the scan chain and an additional bank of flip-flops to update the outputs
in parallel.

Figure: Boundary scan register bit

107. What are logic verification principles? [May 2013, Nov 2013]
Verifying the logical principles of the circuit by the following ways test benches &
Harness, regression testing, version control and bug tracking.

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106. Compare full custom and semi-custom design. (Nov 2019)

Full-Custom design

 All mask layers are customized in a full-custom ASIC

 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
 Critical (timing) paths are usually laid out completely by hand.
Semi-custom ASICs

 Semi-custom ASIC is a cell-based ASIC ( CBIC —“sea-bick”)

 It has Standard cells
 Possibly megacells , megafunctions , full-custom blocks , system-level macros
(SLMs), fixed blocks, cores, or Functional Standard Blocks ( FSBs )
 All mask layers are customized - transistors and interconnect

107. Identify the ways to optimize the manufacturability, to increase yield. [May 2021]
Examine workflow
Invest in employee training.
Modernize your business process.
Invest in smart machining equipment.
Develop realistic expectations.
Stay organized.
Create a culture of collaboration.
Invest in preventative maintenance.

108. What are the advantages and disadvantages of BIST? [Nov/Dec 2022]
Advantages of implementing BIST include:
1) Lower cost of test, since the need for external electrical testing using an ATE will be
reduced, if not eliminated
2) Better fault coverage, since special test structures can be incorporated onto the chips
3) Shorter test times if the BIST can be designed to test more structures in parallel
4) Easier customer support
5) Capability to perform tests outside the production electrical testing environment. The last
advantage mentioned can actually allow the consumers themselves to test the chips prior to
mounting or even after these are in the application boards.

Disadvantages of implementing BIST include:

1) Additional silicon area and fab processing requirements for the BIST circuit
2) Reduced access times
3) Additional pin (and possibly bigger package size) requirements, since the BIST circuitry
need a way to interface with the outside world to be effective
4) Possible issues with the correctness of BIST results, since the on-chip testing hardware
itself can fail.
109. What is configurable logic block meant?
The programmable logic blocks of FPGAs are called Configurable Logic Blocks (CLBs).
CLBs contain LUT, FF, logic gates and Multiplexer to perform logic functions.

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UNIT-V EC3552-VLSI AND CHIP DESIGN

UNIT V
ASIC DESIGN AND TESTING
Question bank

1. Explain about wafer to chip fabrication process flow.

2. Describe about Microchip design process.
3. Explain the issues in test and verification of complex chips.
4. Write short notes on embedded cores and SOCs.
5. Explain the Fault models and Test coding.
6. Explain the ASIC Design Flow.
7. Explain the writing test benches in Verilog HDL
8. Explain the Automatic test pattern generation.
9. Explain the Design for testability. (Scan design: Test interface and boundary scan)

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