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Lec2 - ISA Vs Microarchitecture

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Lec2 - ISA Vs Microarchitecture

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Parallel Computing and Programming.

Lecture 2: ISA vs Microarchitecture

Dr. Rony Kassam

IEF Tishreen Uni

S1 - 2021
Index
n Von Neumann vs Dataflow Models.
n ISA vs Microarchitecture.
n Single-cycle vs Multi-cycle Microarchitectures.
n Instruction Level Parallelism: Pipelining Intro.
n Instruction Level Parallelism: Issues in Pipeline Design.
n Thread Level Parallelism: Data Dependence Solutions.
n Thread Level Parallelism: Shared Memory and OpenMP.

2
ISA Defintions
n ISA+implementation definition: The science and art of
designing, selecting, and interconnecting hardware
components and designing the hardware/software interface
to create a computing system that meets functional,
performance, energy consumption, cost, and other specific
goals.

n Traditional (ISA-only) definition: “The term

architecture is used here to describe the attributes of a
system as seen by the programmer, i.e., the conceptual
structure and functional behavior as distinct from the
organization of the dataflow and controls, the logic design,
and the physical implementation.”
Gene Amdahl, IBM Journal of R&D, April 1964
17
ISA vs. Microarchitecture
n ISA
q Agreed upon interface between software Problem
and hardware Algorithm
n SW/compiler assumes, HW promises
Program
q What the software writer needs to know
to write and debug system/user programs Microarchitecture
n Microarchitecture Circuits
q Specific implementation of an ISA Electrons

q Not visible to the software

n Microprocessor
q ISA, uarch, circuits
q “Architecture” = ISA + microarchitecture
18
ISA vs. Microarchitecture
n ISA
q Agreed upon interface between software Problem
and hardware Algorithm
n SW/compiler assumes, HW promises
Program
q What the software writer needs to know ISA
to write and debug system/user programs Microarchitecture
n Microarchitecture Circuits
q Specific implementation of an ISA Electrons

q Not visible to the software

n Microprocessor
q ISA, uarch, circuits
q “Architecture” = ISA + microarchitecture
18
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

satisfies the specification (ISA)

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

satisfies the specification (ISA)
q Add instruction vs. Adder implementation

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

satisfies the specification (ISA)
q Add instruction vs. Adder implementation
n Bit serial, ripple carry, carry lookahead adders are all part of
microarchitecture.

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

satisfies the specification (ISA)
q Add instruction vs. Adder implementation
n Bit serial, ripple carry, carry lookahead adders are all part of
microarchitecture.
q x86 ISA has many implementations: 286, 386, 486, Pentium,
Pentium Pro, Pentium 4, Core, Kaby Lake, Coffee Lake, …

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

n Microarchitecture usually changes faster than ISA

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

n Microarchitecture usually changes faster than ISA

q Few ISAs (x86, ARM, SPARC, MIPS, Alpha, RISC-V) but many uarchs

19
ISA vs. Microarchitecture
n What is part of ISA vs. Uarch?
q Internals of the engine: implement “acceleration”

n Implementation (uarch) can be various as long as it

n Microarchitecture usually changes faster than ISA

q Few ISAs (x86, ARM, SPARC, MIPS, Alpha, RISC-V) but many uarchs
q Why?

19
ISA
n Instructions
q Opcodes, Addressing Modes, Data Types
q Instruction Types and Formats
q Registers, Condition Codes
n Memory
q Address space, Addressability, Alignment
q Virtual memory management
n Call, Interrupt/Exception Handling
n Access Control, Priority/Privilege
n I/O: memory-mapped vs. instr.
n Task/thread Management
n Power and Thermal Management
n Multi-threading support, Multiprocessor support
n …
20
Microarchitecture
n Implementation of the ISA under specific design constraints
and goals

21
Microarchitecture
n Implementation of the ISA under specific design constraints
and goals
n Anything done in hardware without exposure to software

21
Microarchitecture
n Implementation of the ISA under specific design constraints
and goals
n Anything done in hardware without exposure to software
q Pipelining
q In-order versus out-of-order instruction execution
q Memory access scheduling policy
q Speculative execution
q Superscalar processing (multiple instruction issue?)
q Clock gating
q Caching? Levels, size, associativity, replacement policy
q Prefetching?
q Voltage/frequency scaling?
q Error correction?
21
Property of ISA vs. Uarch?

22
Property of ISA vs. Uarch?
n ADD instruction’s opcode

22
Property of ISA vs. Uarch?
n ADD instruction’s opcode
n Bit-serial adder vs. Ripple-carry adder

22
Property of ISA vs. Uarch?
n ADD instruction’s opcode
n Bit-serial adder vs. Ripple-carry adder
n Number of general purpose registers

22
Property of ISA vs. Uarch?
n ADD instruction’s opcode
n Bit-serial adder vs. Ripple-carry adder
n Number of general purpose registers
n Number of cycles to execute the MUL instruction

22
Property of ISA vs. Uarch?
n ADD instruction’s opcode
n Bit-serial adder vs. Ripple-carry adder
n Number of general purpose registers
n Number of cycles to execute the MUL instruction
n Number of ports to the register file

n Remember
q Microarchitecture: Implementation of the ISA under specific
design constraints and goals

22
Design Point
n A set of design considerations and their importance
q leads to tradeoffs in both ISA and uarch
Problem
Algorithm
Program
ISA
Microarchitecture
Circuits
Electrons

23
Design Point
n A set of design considerations and their importance
q leads to tradeoffs in both ISA and uarch
n Example considerations: Problem
Algorithm
Program
ISA
Microarchitecture
Circuits
Electrons

23
Design Point
n A set of design considerations and their importance
q leads to tradeoffs in both ISA and uarch
n Example considerations: Problem
q Cost Algorithm

q Performance Program

q Maximum power consumption, thermal ISA

Microarchitecture
q Energy consumption (battery life)
Circuits
q Availability
Electrons
q Reliability and Correctness
q Time to Market
q Security, safety, predictability, …

23
Design Point
n A set of design considerations and their importance
q leads to tradeoffs in both ISA and uarch
n Example considerations: Problem
q Cost Algorithm

q Performance Program

q Maximum power consumption, thermal ISA

Microarchitecture
q Energy consumption (battery life)
Circuits
q Availability
Electrons
q Reliability and Correctness
q Time to Market
q Security, safety, predictability, …

n Design point determined by the “Problem” space

(application space), the intended users/market
23
Application Space
Dream, and they will appear…