1/18/2024

Digital System Design

CS-431

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Testing & Verification

– Introduction
– DFT Techniques
❖ Terminology: Controllability & Observability
➢ BIST
➢ Adhoc Testing
➢ Scan Based Testing
❖Serial Scan
❖Parallel Scan
❖Partial Scan
❖Boundary Scan
❖TAP Controller
❖Faults & Errors

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 1

 1/18/2024

Adhoc Testing

• Adhoc (Latin word means "For this"); the term is generally used to imply
that something is intended for a particular situation or purpose.

• Definition:
• Adhoc testing combines a collection of tricks and techniques that can be
used to increase the observability and controllability of a design and
that are generally applied in an application dependent fashion.
• Ad hoc testing tries to avoid the overhead of a systematic approach of
testing.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Adhoc Testing

Some common techniques:

1. Partitioning large sequential circuits →Avoid large fan-in

2. Adding test points
3. Adding multiplexers
4. Providing for easy state reset.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 2

 1/18/2024

Adhoc Testing

Example technique #01

1. Partitioning large sequential circuits:
Let us take an example of 16-bit (N=16) counter. The time required to test the16-bit
counter is given below:
16 bit counter
Test time = 2^16 x tester period
where tester period is the time taken from applying the test pattern to analyzing the
output with expected outputs.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Adhoc Testing

Let us assume that we divide the 16-bit counter in to two 8-bit counters.

8bit counter 8bit counter

Test time =
2^8 x tester period 2^8 x tester period

Therefore, total test time = 2 x 2^8 x tester period

= 2^9x tester period

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 3

 1/18/2024

Adhoc Testing

Hence, we say that partitioning large circuits

• Reduces test pattern number as from 16-bits to 8-bits

• Reduces tester time/period
• Reduces test total time
• Increase internal access.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Adhoc Testing

Example techniques #2,3:

2. Adding test points Memory
3. Adding multiplexers/selectors.
• By looking at figure (a) above, we may observe Data Address
that the memory module is accessible only through
the processor i.e., we have reduced internal access
and therefore the testability (controllability and Processor
Observability) is also decreased.
• This overhead can be removed in this situation (ad I/O Bus

hoc) by using Adhoc techniques 2 and 3. Figure (a) Design with low testability

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 4

 1/18/2024

Adhoc Testing

• We may observe in figure (b) that by adding a Memory

multiplexer, we can access the same memory module
Data Address
from I/O bus directly instead of going through the
Test
processor. This can be achieved by setting test pin to Mux/Select
test mode for the purpose of testability otherwise to
normal mode.
Processor

I/O Bus
Figure (b)

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Adhoc

Example technique # 4
4. Providing easy state reset
• One of the major and the most important problems in sequential logic testing occurs at
the time of power-on, where the first state is random if there were no Initialization.
Therefore, impossible to start a test sequence correctly.
• The solution is to provide easy state reset of initialization to a known state or value.

Reset
Embedded Systems Design: A Unified Hardware/Software Introduction, (c)
2000 Vahid/Givargis

Dr. Majida Kazmi 5

 1/18/2024

Scan Based Testing Approaches

• The major difficulty in testing sequential circuits is determining the internal

state of the circuit.
• Objective: Scan design techniques are directed at improving the controllability
and observability of the internal states of a sequential circuit.
• Scan based designs can simply be viewed as depicted in the figure given
below.

DIN 0
Reg- Reg- Reg-
Dout
SIN 1 ister ister ister

Mode Sout
Selector

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Scan Based Testing Approaches

• In scan designs, the registers operate in one of the two modes. In normal mode, they
behave as expected (actual objective of design/circuit), and in scan mode, they are
connected to form a shift register called a ‘Scan Chain’ or ‘Scan Path’ as shown with
dotted line.
• Thus, the internal state of the circuit can be viewed, observed and controlled by
shifting (scanning) out the contents of the storage elements.
• Generally, the selection of the input source is achieved by using the multiplexer
controlled by an external mode signal.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 6

 1/18/2024

Scan Based Testing Approaches

The method of testing a circuit with the scan path is as follows:

1) Set test mode signal → Flip flops accept data from SIN input.
2) Verify the scan path by shifting in and out the test data.
3) Set the shift register to an initial value/register state.
4) Apply a test pattern. For n-bit register, apply n clock cycles.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Scan Based Testing Approaches

5) Set normal mode, the circuit settles and can monitor the primary output.
6) Activate the circuit clock for one more cycle.
7) Set the test mode again.
8) Apply n cycles again to scan out the contents of shift register at sout output.
Simultaneously apply new test value.

Embedded Systems Design: A Unified Hardware/Software Introduction, (c)

2000 Vahid/Givargis

Dr. Majida Kazmi 7