8 August 2022 1444 ‫ محرم‬11

‫ن ا ْلعِْل ِم إِاَّل قَلِ ًيل‬ ِ ِ

َ ‫َومَا أُوتيتُ ْم م‬
Ain Shams University – Faculty of Engineering – ECE Dept. – Integrated Circuits Lab.
Dr. Hesham Omran

Analog IC Design
Lab 06
Differential Amplifier

Intended Learning Objectives

In this lab you will:
• Design and simulate a differential amplifier.
• Learn how to simulate the small-signal differential characteristics of a differential amplifier.
• Learn how to simulate the small-signal common-mode characteristics of a differential amplifier.
• Learn how to simulate the large-signal differential characteristics of a differential amplifier.
• Learn how to simulate the large-signal common-mode characteristics of a differential amplifier.

PART 1: Sizing Chart

1) We can show that the intrinsic gain of a MOSFET is given by

2𝐼𝐷 𝑉𝐴 2𝑉𝐴
|𝐴𝑣 | ≈ 𝑔𝑚 𝑟𝑜 = × =
𝑉𝑜𝑣 𝐼𝐷 𝑉𝑜𝑣
 2𝐼𝐷
Interestingly, the gain only depends on 𝜆 and 𝑉𝑜𝑣 . However, to derive this expression we used 𝑔𝑚 = 𝑉𝑜𝑣
2𝐼
which is based on the square-law. For a real MOSFET, if we compute 𝑉𝑜𝑣 and 𝑔 𝐷 they will not be equal.
𝑚

Let’s define a new parameter called V-star (𝑉 ∗ ) which is calculated from actual simulation data using the
formula
2𝐼𝐷 2𝐼𝐷
𝑉∗ = ↔ 𝑔𝑚 = ∗
𝑔𝑚 𝑉
∗
For a square-law device, 𝑉 = 𝑉𝑜𝑣 , however, for a real MOSFET they are not equal. The actual gain is
now given by
2𝑉𝐴
|𝐴𝑣 | ≈ ∗
𝑉
The lower the 𝑉 ∗ the higher the gain, but the larger the area and the lower the speed.
2) We want to design a differential amplifier with the specifications below. Note that the bias current is
split between two transistors; each transistor gets 𝐼𝐷 = 20𝜇𝐴.
Parameter 130 nm 180 nm

𝑳 1𝜇𝑚 1𝜇𝑚

CM output level1 0.5 0.7

Differential gain 5 8

Supply 1.2𝑉 1.8𝑉

Bias current (𝑰𝑺𝑺 ) 40𝜇𝐴 40𝜇𝐴

3) Choose 𝑅𝐷 to meet the CM output level spec.

4) We can show that the differential amplifier gain is given by

2𝐼𝐷 2𝑉𝑅
|𝐴𝑣 | ≈ 𝑔𝑚 𝑅𝐷 = ∗
× 𝑅𝐷 = ∗𝐷
𝑉 𝑉
5) Choose 𝑉 ∗ to meet the differential gain spec.
6) The remaining variable in the design is to calculate 𝑊. Since the square-law is not accurate, we cannot
use it to determine the sizing. Instead, we will use a sizing chart generated from simulation. Create a
testbench for PMOS transistor as shown below (we will use PMOS only in this lab). Use 𝑊 = 10𝜇𝑚 (we
will understand why shortly).

7) Sweep VGS from 0 to ≈ 𝑉𝑇𝐻 + 0.4𝑉 with 10mV step. Set 𝑉𝐷𝑆 = 𝑉𝐷𝐷 /2.

1
ISS*RD must be smaller than (VDD – 𝑉𝑑𝑠𝑎𝑡3 ) for proper large signal characteristics (why?).

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8) We want to compare 𝑉 ∗ = 2𝐼𝐷 /𝑔𝑚 and 𝑉𝑜𝑣 = 𝑉𝐺𝑆 − 𝑉𝑇𝐻 by plotting them overlaid. Use the calculator to
create expressions for 𝑉 ∗ and 𝑉𝑜𝑣 . You can save the expressions to reuse them later.
9) Plot 𝑉 ∗ and 𝑉𝑜𝑣 overlaid vs VGS. Make sure the y-axis of both curves has the same range. You will notice
that at the beginning of the strong inversion region, 𝑉 ∗ and 𝑉𝑜𝑣 are relatively close to each other (i.e.,
square-law is relatively valid). For deep strong inversion (large 𝑉𝑜𝑣 : velocity saturation and mobility
degradation) or weak inversion (near-threshold and subthreshold operation) the behavior is quite far
from the square-law.
10) On the 𝑉 ∗ and 𝑉𝑜𝑣 chart locate the point at which 𝑉 ∗ is equal to the value your previously calculated to
meet the gain spec. Find the corresponding 𝑉𝑜𝑣𝑄 and 𝑉𝐺𝑆𝑄 .
11) Plot 𝐼𝐷 , 𝑔𝑚 , and 𝑔𝑑𝑠 vs 𝑉𝐺𝑆 . Find their values at 𝑉𝐺𝑆𝑄 . Let’s name these values 𝐼𝐷𝑋 , 𝑔𝑚𝑋 , and 𝑔𝑑𝑠𝑋 .
12) Now back to the assumption that we made that 𝑊 = 10𝜇𝑚. This is not the actual value that we will use
for our design. But the good news is that 𝐼𝐷 is always proportional to 𝑊 irrespective of the operating
region and the model of the MOSFET (regardless square-law is valid or no). Thus, we can use ratio and
proportion (cross-multiplication) to determine the correct width at which the current will be 𝐼𝐷𝑄 as given
in the specs. Calculate 𝑊 as shown below.
𝑾 𝑰𝑫

𝟏𝟎𝝁𝒎 𝐼𝐷𝑋 @𝑉𝑄∗ (from the chart)

? 𝐼𝐷𝑄 = 20𝜇𝐴 (from the specs)

13) Now we are almost done with the design of the amplifier. Note that 𝑔𝑚 is also proportional to 𝑊 as long
as 𝑉𝑜𝑣 is constant. On the other hand, 𝑟𝑜 = 1/𝑔𝑑𝑠 is inversely proportional to 𝑊 (𝐼𝐷 ) as long as 𝐿 is
constant. Before leaving this part, calculate 𝑔𝑚𝑄 and 𝑔𝑑𝑠𝑄 using ratio and proportion (cross-
multiplication).

PART 2: Differential Amplifier

1) Create a new cell for the diff amp “lab_06_diff_amp”. Create the schematic of a differential amplifier
with PMOS input stage and resistive load. Use a simple current mirror for the bias current source as
shown in the first figure in this document.
2) Create a symbol for the diff pair (use Create -> Cellview -> From Cellview).
3) Edit the diff amp symbol to be as shown below.

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4) Create a new cell for the testbench “lab_06_diff_amp_tb”. Create testbench schematic as shown below.
➔ Cadence Hint: Use ideal_balun from analogLib to separate common-mode and differential signals. In
Mentor tools you have to create the balun yourself.

5) Size the transistors as designed in Part 1.

6) Use IB = 20uA (the CM multiplies this by 2, so each half in the diff pair gets IB).
7) Connect floating wires to noConn instance from basic library to avoid floating signal warnings.
8) Use CL = 1pF.
9) Analytically calculate the valid range for Vicm: the common mode input range (CMIR). Set Vicm at the
center of this range.
➔ Cadence Hint: In adexl you can access the results of the last 10 simulation runs from the “History”
tab. We want to access the last two simulation runs in order to compare Avd and Avcm. Open both
simulations in the Results Browser.

Report the following:

1) OP simulation.
• Report the schematic of the diff pair with DC OP point clearly annotated: id, vgs, vds, vth, vdsat, gm,
gds, gmb, region.
• Check that all transistors operate in saturation.
2) Diff small signal ccs:
• Use AC magnitude = 1 for the diff source (and AC magnitude = 0 for the CM source).
• Set Vicm at the center of the CMIR.
• Run AC analysis (1Hz:10GHz, logarithmic, 10 points/decade).
• Report the Bode plot of small signal diff gain.
• Compare the DC diff gain and BW with hand analysis in a table.
3) CM small signal ccs:
• Use AC magnitude = 1 for the CM source (and AC magnitude = 0 for the diff source).
• Run AC analysis (1Hz:10GHz, logarithmic, 10 points/decade).
• Report the Bode plot of small signal CM gain.
• Compare the DC CM gain with hand analysis in a table. Is it smaller than “1”? Why?
• Justify the variation of Avcm vs frequency.
• Plot Avd/Avcm in dB. Compare Avd/Avcm @ DC with hand analysis in a table.

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 • Justify the variation of Avd/Avcm with frequency.
➔ Cadence Hint: Note that xf analysis cannot be used in this case because we have two outputs (Diff
and CM). xf analysis is useful for the case of single-ended output op-amp where there is only one
output terminal. It is also useful for fully diff op-amp to calculate CMRR(SE2diff), but not Avd/Avcm.
4) Diff large signal ccs:
• Use dc sweep (not parametric sweep) for Vid = -VDD:10m:VDD. Set Vicm at the center of the CMIR.
• Report diff large signal ccs (VODIFF vs VIDIFF). Compare the extreme values with hand analysis in a
table.
5) CM large signal ccs (region vs VICM):
• We will use the region parameter to know the operating region of each transistor vs sweep variable.
➔ Cadence Hint: The “region” meaning is as follows:
0: cut-off
1: triode
2: sat
3: subth
4: breakdown
• Use DC sweep (not parametric sweep) for Vicm = 0:10m:VDD (no need to run AC sim)
➔ Cadence Hint: To save the “region” parameter, add this this line to your save.scs file (in Model
Libraries):
save *:region sigtype=dev.
• Disable ac analysis.
• Plot “region” OP parameter vs VICM for the input pair and the tail current source.
• Find the CM input range (CMIR). Compare with hand analysis in a table.
• Note that the drawback of this method is that the “region” parameter cannot be experimentally
measured in the lab and is not quantitively related to circuit specifications.
6) CM large signal ccs (GBW vs Vicm):
• Use ac analysis (start = 1, stop = 1, pts(linear) = 1) to get Avd. Use parametric sweep (not dc sweep)
for Vicm = 0:20m:VDD.
➔ Cadence Hint: Instead of using parametric sweep, a better alternative in Cadence is to use AC sweep
but sweep a design variable (Vicm) instead of sweeping the frequency. The frequency is set at 1 Hz
(or any other small value) to get the low frequency gain (DC gain).
➔ Cadence Hint: Use the following expression in adexl to calculate Avd: ymax(mag(VF("/VODIFF")))
• Note that the bandwidth is determined by RD and CL, thus Avd variation is itself GBW variation.
• Report CM large signal ccs (Avd vs Vicm). Assume the valid range for Vicm (CMIR) is defined by the
condition that Avd is within 90% of the max gain, i.e., 10% drop in gain.
• Plot the results overlaid on the results of the previous method (region parameter). Find the CM input
range. Compare with the previous method in a table.

Lab Summary
• In Part 1 you learned:
o How to generate and use design charts for NMOS and PMOS transistors.
o How to design a resistive-loaded differential amplifier.

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 • In Part 2 you learned:
o How to use an ideal balun.
• In Part 3 you learned:
o How to simulate the small-signal differential gain of a differential amplifier.
o How to simulate the small-signal common-mode gain of a differential amplifier.
o How to simulate the large-signal differential characteristics of a differential amplifier.
o How to simulate the large-signal common-mode characteristics of a differential amplifier.

Acknowledgements
Thanks to all who contributed to these labs. Special thanks to Dr. Sameh A. Ibrahim for reviewing and editing
the labs. If you find any errors or have suggestions concerning these labs, contact
[email protected].

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