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Counters in Digital Logic

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21 views3 pages

Counters in Digital Logic

Uploaded by

wkchanna
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Counters in Digital Logic

A Counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
Counters are used in digital electronics for counting purpose, they can count specific event
happening in the circuit. For example, in UP counter a counter increases count for
every rising edge of clock. Not only counting, but a counter can also follow the certain
sequence based on our design like any random sequence 0,1,3,2. Most of time counters are
designed with the help of flip flops.

Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter

In asynchronous counter don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following flip flop is driven by output of previous flip
flops. We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock
pulse is encountered, Q1 is changing when rising edge of Q0 is encountered
(because Q0 is like clock pulse for second flip flop) and so on. In this way ripples are
generated through Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter and serial
counter.
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which
drives each flip flop so output changes in parallel. The one advantage of synchronous
counter over asynchronous counter is, it can operate on higher frequency than asynchronous
counter as it does not have cumulative delay because of same clock is given to each
flip flop. It is also called as parallel counter.

From circuit diagram we see that Q0 bit gives response to each falling edge of clock.
while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on
Q2,Q1 and Q0.

Number of flip-flops required to design N state number of counter.


If we are designing mod N counter and n number of flip-flops are required, then n can be
found out by this equation.
N <= 2n
Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops(n)
required is

For n= 4,10<=16, which is true.


Therefore number of Flip Flop required is 4 for Mod-10 counter.

Decade Counter

A decade counter is called as mod -10 or divide by 10 counters. It counts from 0 to


9 and again reset to 0. It counts in natural binary sequence. Here 4 Flip flops are used. It
resets after Q3 Q2 Q1 Q0 = 1001.
A decade counter is a digital circuit that counts in decimal digits, from 0 to 9, and then resets
to zero. It's also known as a BCD counter.

Here are some things to know about decade counters:


 A four-stage counter can be modified to a decade counter by adding a NAND gate.
 The IC 7490 is an integrated circuit that's often used as a decade counter. It contains
flip-flops and digital logic gates that allow it to count in different ways.

BCD 8 4
2 1
Clock pulse Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

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