Half Adder

A half adder is a fundamental digital circuit that performs the addition of two single-bit binary numbers. It is a basic
building block for more complex arithmetic circuits like full adders.

Truth Table

The truth table for a half adder shows the relationship between the inputs AA and BB and the outputs SS (Sum)
and CC (Carry):

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Gate Diagram

The half adder can be constructed using an XOR gate and an AND gate:

Boolean Expressions

The outputs of a half adder can be defined by the following Boolean expressions:
 Sum (S): S=A⊕BS=A⊕B (where ⊕⊕ denotes the XOR operation)

 Carry (C): C=A⋅BC=A⋅B (where ⋅⋅ denotes the AND operation)

Full Adder
 A full adder is a combinational logic circuit that adds three binary digits: two
significant bits, AA and BB, along with a carry-in bit Cin. It produces a sum
output SS and a carry-out output Cout

Block Diagram

 The block diagram of a full adder is as follows:

Truth Table

The truth table for a full adder is as follows:

A B C_in S (Sum) C_out (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Gate Diagram
 A full adder can be constructed using the following gates:

 2 XOR gates

 2 AND gates

 1 OR gate

The connections are as follows:

 The first XOR gate takes inputs A and B to produce an intermediate sum.

 The second XOR gate takes the intermediate sum and C_in to produce the final sum S.

 The first AND gate takes inputs A and B to produce one carry output.

 The second AND gate takes the intermediate sum and C_in to produce another carry output.

 The OR gate combines the outputs of the two AND gates to produce the final carry output C_out.

Boolean Expressions

The outputs of a full adder can be expressed with the following Boolean equations:

 Sum (S):

S=A⊕B⊕CinS=A⊕B⊕Cin

 Carry (C_out):

Cout=AB+ACin+BCinCout=AB+ACin+BCin

These expressions indicate how the outputs are derived from the inputs using logical operations.
Working of a 4-Bit Full Adder
A 4-bit full adder is a digital circuit that adds two 4-bit binary numbers along with a carry
input from a previous addition. It consists of four individual full adders connected in series,
where the carry output from each adder becomes the carry input for the next adder. This
configuration allows for the addition of multi-bit binary numbers
Feature RISC CISC

Simplified, with fewer Complex, with a larger number of

Instruction Set instructions instructions

Instruction Typically executes one Can take multiple cycles for complex
Execution instruction per cycle instructions

Addressing
Modes Fewer addressing modes More addressing modes

Instruction
Format Fixed-length instructions Variable-length instructions

Power Generally lower power

Consumption consumption Typically higher power consumption

Pipelining Highly pipelined Less pipelined

Focus Software optimization Hardware optimization

Requires more RAM due to More memory efficient due to fewer

Memory Usage more instructions instructions

Control Unit
Design Hardwired control unit Microprogrammed control unit

Detailed Explanations
BLOCK DIAGRAM
Feature Assembly Language High-Level Language

Level of Low-level language, closely High-level language, more abstract

Abstraction related to machine code and user-friendly

Less readable; uses mnemonics More readable; uses English-like

Readability and symbolic codes syntax and keywords

Machine Machine-dependent; specific to Machine-independent; can run on

Dependency a processor architecture multiple types of hardware

Translation Requires an assembler to convert Requires a compiler or interpreter for

Process to machine code conversion to machine code

Generally shorter, more compact

Code Length code Typically longer, less compact code

Faster execution due to direct Slower execution due to additional

Execution Speed hardware manipulation abstraction layers

Control Over Provides greater control over Less control over hardware; abstracts
Hardware hardware components many details

More prone to errors due to Less prone to errors; easier

Error Proneness complexity debugging and error handling

Development Longer development time due to Shorter development time; easier to

Time complexity write and maintain

Examples x86, ARM, MIPS C, C++, Java, Python, JavaScript

// Full Adder Module

module full_adder (
input wire A, // First input bit
 input wire B, // Second input bit
input wire Cin, // Carry input
output wire Sum, // Sum output
output wire Cout // Carry output
);

// Internal signals for intermediate calculations

wire AxorB; // A XOR B
wire AandB; // A AND B
wire AxorBandCin; // (A XOR B) XOR Cin

// Calculate Sum and Carry outputs

assign AxorB = A ^ B; // XOR operation between A and B
assign Sum = AxorB ^ Cin; // Final Sum output
assign AandB = A & B; // AND operation between A and B
assign Cout = AandB | (AxorB & Cin); // Final Carry output

endmodule
// Half Adder Module
module half_adder (
input wire A, // First input bit
input wire B, // Second input bit
output wire Sum, // Sum output
output wire Carry // Carry output
);

// Logic for Sum and Carry outputs

 assign Sum = A ^ B; // Sum is A XOR B
assign Carry = A & B; // Carry is A AND B

endmodule
A 4-bit adder is a digital circuit that performs the addition of two 4-bit binary numbers,
producing a 4-bit sum and a carry output. It is constructed using a combination of half
adders and full adders. Below is an explanation of its working principle along with a block
diagram.
Working Principle of a 4-Bit Adder
Components
1. Half Adder:
 Used for the least significant bit (LSB) addition. It takes two inputs and produces a sum and
a carry output.
 The logic for the half adder is:
 Sum=A0⊕B0Sum=A0⊕B0
 Carry=A0⋅B0Carry=A0⋅B0
2. Full Adders:
 Used for the remaining three bits (A1, A2, A3 and B1, B2, B3). Each full adder takes three
inputs: two bits to be added and an incoming carry bit from the previous stage.
 The logic for the full adder is:
 Sum=Ai⊕Bi⊕CinSum=Ai⊕Bi⊕Cin
 Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))
Structure
 The 4-bit adder consists of:
 1 Half Adder for the LSB.
 3 Full Adders for the remaining bits.
Carry Propagation
 The carry output from each adder is connected as the carry input to the next higher-order
adder. This cascading effect allows for the addition of multi-bit numbers.
Block diagram:
 A 4-bit adder and subtractor is a digital circuit that can perform both addition and
subtraction on two 4-bit binary numbers. This circuit utilizes a combination of full adders
and logic gates to achieve its functionality, along with an overflow detection mechanism.
Working of a 4-Bit Adder and Subtractor
Components
1. Full Adders:
 The circuit consists of four full adders, each responsible for adding corresponding bits from
the two numbers along with any carry from the previous bit.
2. Control Signal (K):
 A control signal determines whether the operation is addition or subtraction. When K = 0,
the circuit performs addition; when K = 1, it performs subtraction.
3. Two's Complement for Subtraction:
 To perform subtraction using an adder, the second number is converted to its two's
complement (which involves inverting the bits and adding one). This allows the adder to
handle subtraction as an addition operation.
Operation
 Addition:
 The two 4-bit numbers AA and BB are fed into the full adders directly when K = 0.
 Subtraction:
 For subtraction, the bits of BB are inverted using XOR gates (with the control signal K) and
then added to AA. The carry-in for the least significant bit (LSB) is set to 1 to account for the
additional one in the two's complement.
Overflow Detection
 Overflow occurs if the result of the addition or subtraction exceeds the range that can be
represented with 4 bits. For a 4-bit adder/subtractor:
 Overflow in Addition: If both inputs are positive and the result is negative.
 Overflow in Subtraction: If both inputs are negative and the result is positive.
 This can be detected by examining the carry into and out of the most significant bit (MSB).
Block Diagram of a 4-Bit Adder/Subtractor
The implementation of this 3 line to 8 line decoder can be done using two 2 lines to 4 line
decoders. We have discussed above that 2 to 4 line decoder includes two inputs and four
outputs. So, in 3 lines to 8 line decoder, it includes three inputs like A2, A1 & A0 and 8
outputs from Y7 – Y0.
The following formula is used to implementation of higher-order decoders with the help of
low order decoders
The number of lower-order decoders required is m2/m1
Where,
The number of o/ps for the lower-order decoder is ‘m1’
The number of o/ps for higher-order decoder is ‘m2’
For instance, when m1 = 4 & m2 = 8, then substitute these values in the above equation.
We can get the required no. of decoders are 2. So, for implementing a single 3 to 8 decoder,
we need two 2 lines to 4 line decoders. Here, the block diagram is shown below by using
two 2 to 4 decoders.

3 to 8 Decoder using 2 to 4 Line

The parallel inputs like A2, A1 & A0 are given to 3 lines to 8 line decoder. Here the
compliment of A3 is given to enable the pin of the decoder to obtain the outputs like Y7 to
Y0. These outputs are lower 8 minterms. In the above decoder, the A3 input is connected to
enable the pin to obtain the outputs from Y15 – Y8. So, these outputs are the higher 8
minterms.
 Working of a 4-Bit Full Adder
1. Definition: A 4-bit full adder is a digital circuit that adds two 4-bit binary numbers along
with an optional carry input, producing a 4-bit sum and a carry output.
2. Components:
 The circuit consists of four full adders connected in series.
 Each full adder is made up of:
 2 XOR gates for sum calculation.
 2 AND gates for carry generation.
 1 OR gate to combine carry outputs.
3. Inputs and Outputs:
 Inputs:
 Two 4-bit binary numbers (A = A3 A2 A1 A0 and B = B3 B2 B1 B0).
 An initial carry input (C_in).
 Outputs:
 A 4-bit sum (S = S3 S2 S1 S0).
 A final carry output (C_out).
4. Addition Process:
 The addition starts from the least significant bit (LSB) (A0, B0) and moves towards the most
significant bit (MSB) (A3, B3).
 For each bit position, the corresponding bits from both numbers and the carry from the
previous stage are fed into a full adder.
5. Full Adder Logic:
 The sum output for each full adder is calculated using the formula:
Si=Ai⊕Bi⊕CinSi=Ai⊕Bi⊕Cin
 The carry output is calculated using:
Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))
6. Cascading Full Adders:
 The carry output from each full adder becomes the carry input for the next higher-order full
adder.
 This cascading continues until all four bits are processed.
7. Example Calculation:
 For inputs A = 1100 and B = 1010, the addition would be performed as follows:
 Add A0 and B0 with C_in = 0.
 Calculate S0 and C1.
 Repeat for A1, B1 with C_in = C1, and so on until A3, B3.
8. Final Output:
 After processing all bits, the outputs will be the final sum S = S3 S2 S1 S0 and the carry out
C_out.
9. Applications:
 Used in arithmetic logic units (ALUs), calculators, and various digital systems requiring
binary addition.
1. Definition
 A 4-bit full adder is a digital circuit that adds two 4-bit binary numbers along with an
optional carry input, producing a 4-bit sum and a carry output.
 A 4-bit subtractor performs subtraction of two 4-bit binary numbers, typically using the
method of two's complement, and also detects overflow.
2. Components
 Full Adder:
 Composed of four full adders.
 Uses XOR, AND, and OR gates to compute the sum and carry.
 Subtractor:
 Can be implemented using a full adder by inverting the second number (using NOT gates)
and adding it to the first number along with a carry-in of 1.
3. Inputs and Outputs
 Inputs for Full Adder:
 Two 4-bit binary numbers (A = A3 A2 A1 A0 and B = B3 B2 B1 B0).
 An initial carry input (C_in).
 Outputs for Full Adder:
 A 4-bit sum (S = S3 S2 S1 S0).
 A final carry output (C_out).
 Inputs for Subtractor:
 Same as the adder, but B is inverted before addition.
 Outputs for Subtractor:
 A 4-bit difference (D = D3 D2 D1 D0).
 A borrow output if needed.
4. Addition Process (Full Adder)
 The addition starts from the least significant bit (LSB) (A0, B0) and moves towards the most
significant bit (MSB) (A3, B3).
 Each bit is processed through a full adder:
 Sum output:
Si=Ai⊕Bi⊕CinSi=Ai⊕Bi⊕Cin
 Carry output:
Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))Cout=(Ai⋅Bi)+(Cin⋅(Ai⊕Bi))
5. Subtraction Process
 To perform subtraction using a full adder:
 Invert the bits of B to get B‾B.
 Add B‾B to A with a carry-in of 1.
 For each bit position:
 Difference output:
Di=Ai⊕Bi‾⊕CinDi=Ai⊕Bi⊕Cin
 Borrow output:
 Borrowout=(Bi‾⋅Cin)+(Bi‾⋅Ai)Borrowout=(Bi⋅Cin)+(Bi⋅Ai)
6. Overflow Detection
 For Addition: Overflow occurs if the carry into the MSB differs from the carry out of the
MSB.
 For Subtraction: Overflow occurs if the sign of the result does not match the expected sign
based on the inputs. This can be checked by examining the signs of A, B, and D.
7. Example Calculation
 Addition Example:
 Inputs: A = 1100, B = 1010
 Process each bit using full adders to get S = 10110 with C_out indicating overflow.
 Subtraction Example:
 Inputs: A = 1100, B = 0011
 Invert B to get B‾=1100B=1100, then add with C_in = 1.
 Resulting difference D will be computed similarly.
8. Applications
 Used in arithmetic logic units (ALUs), calculators, digital signal processing, and various
digital systems requiring binary addition and subtraction.
An 8:3 encoder is a combinational circuit that converts eight input lines into three output
lines. It encodes the active input into a binary representation. Below is a detailed
explanation of its working, including the block diagram, truth table, Boolean expressions,
and logic diagram.
Block Diagram
The block diagram of an 8:3 encoder is as follows:
text
+-----------------+
| |
D7 -->| |
D6 -->| |
D5 -->| |
D4 -->| |--> Q2
D3 -->| 8:3 Encoder |--> Q1
 D2 -->| |--> Q0
D1 -->| |
D0 -->| |
+-----------------+
Truth Table
The truth table for the 8:3 encoder is shown below. It assumes that only one input is high
(logic 1) at any time; otherwise, the outputs are undefined (X).
Inputs Outputs

D7 D6

-------- ---------

0 0

0 0

0 0

0 0

0 0

X X

Boolean Expressions
From the truth table, we can derive the Boolean expressions for the outputs Q2Q2, Q1Q1,
and Q0Q0:
 Q2:
Q2=D4+D5+D6+D7Q2=D4+D5+D6+D7
 Q1:
Q1=D2+D3+D6+D7Q1=D2+D3+D6+D7
 Q0:
Q0=D1+D3+D5+D7Q0=D1+D3+D5+D7
Logic Diagram