CHAPTER1

Digital Logic Circuits

 SECTIONS TO COVER
• 1.1: Digital Computers
• 1.2: Logic Gates
• 1.3: Boolean Algebra
• 1.4: Map Simplification
• 1.5: Combinational Circuits(Half and Full Adder)
• 1.6: Flip Flops
• 1.7: Sequential Circuits (FF I/p Eqn.)
 Digital Computer
• Digital computer is a digital system that performs various computational
tasks.
• The word digital implies that the information in the computer is represented
by variables that take a limited number of discrete values.
• The decimal digits 0, 1, 2, . . . , 9, for example, provide 10 discrete values.
• Digital computers use the binary number system, which has two digits: 0 and
1.
• A binary digit is called a bit.
• Information is represented in digital computers in groups of bits.
• By using various coding techniques, groups of bits can be made to represent
not only binary numbers but also other discrete symbols, such as decimal
digits or letters of the alphabet
A computer system can be divided into two functional entities: hardware and software.
System
Software
Software
Application
Software
Computer
System CPU

Hardware Memory

ALU

• The hardware of the computer consists of all the electronic components and
electromechanical devices that comprise the physical entity of the device.
• Computer software consists of the instructions and data that the computer manipulates
to perform various data-processing tasks.
• A sequence of instructions for the computer is called a program.
• The data that are manipulated by the program constitute the data base.
 COMPUTER SOFTWARE
• System Software: The system software of a computer consists of a collection of programs
whose purpose is to make more effective use of the computer. Ex. OS.
• Application programs: Programs written by the user for the purpose of solving particular
problems. For example, a high level language program written by a user to solve particular
data-processing needs is an application program, but the compiler that translates the high-
level language program to machine language is a system program.
• Hardware: The hardware of the computer is usually divided into three major parts CPU,
Memory and Control unit.
• The central processing unit (CPU) contains an arithmetic and logic unit for manipulating
data, a number of registers for storing data, and control circuits for fetching and executing
instructions.
• The memory of a computer contains storage for instructions and data. It is called a random-
access memory (RAM) because the CPU can access any location in memory at random and
retrieve the binary information within a fixed interval of time.
• The input and output processor (IOP) contains electronic circuits for communicating and
controlling the transfer of information between the computer and the outside world. The
input and output devices connected to the computer include keyboards, printers, terminals,
magnetic disk drives, and other communication devices.
 RAM (Random Access Memory)

CPU (Central Processing Unit)

Input IOP (Input-Output Processor) Output

Devices Devices

BLOCK DIAGRAM OF DIGITAL COMPUTER

Computer Organization, Design and Architecture
• Computer organization is concerned with the way the hardware components
operate and the way they are connected together to form the computer system.
(Concerned with components placement and to verify that the computer parts
operate as intended)
• Computer design is concerned with the hardware design of the computer.
(Concerned with what hardware should be used and how the parts should be
connected).
• Computer architecture is concerned with the structure and behavior of the computer
as seen by the user.
(Concerned with specifications of the various functional modules, such as processors
and memories, and structuring them together into a computer system)
Two types of Architecture:
➢Von Neumann architecture(Desktop)
➢ Harvard architecture (Microcontroller , DSP(Digital signal Processor))
 LOGIC GATES
• Binary information is represented in digital computers by physical quantities called signals.
• Electrical signals such as voltages exist throughout the computer in either one of two recognizable
states. The two states represent a binary variable that can be equal to 1 or 0.
• The manipulation of binary information is done by logic circuits called gates.Gates are blocks of
hardware that produce signals of binary 1 or 0 when input logic requirements are satisfied.
• Truth Table- A truth table is a table that shows all possible combinations of inputs and outputs for a
logic gate
• Basic Gates: AND, OR and NOT
➢AND Gate(.) – The AND gate gives an output of 1 when if both the two inputs are 1, it gives 0
otherwise. For n-input gate if all the inputs are 1 then 1 otherwise 0.
➢OR Gate(+) – The OR gate gives an output of 1 if either of the two inputs are 1, it gives 0
otherwise. For n-input gate if all the inputs are 0 then 0 otherwise 1.
➢NOT Gate(‘) – The NOT gate gives an output of 1 if the input is 0 and vice-versa.
➢XOR Gate( ) – The XOR gate gives an output of 1 if either both inputs are different, it gives 0 if
they are same. For n-input gate if the number of input 1 are odd then it gives 1 otherwise 0.
•.
•..

Four more logic gates are obtained if the output of above-mentioned gates is
negated .
• NAND Gate( )- The NAND gate (negated AND) gives an output of 0 if both inputs are 1,
it gives 1 otherwise. For n-input gate if all inputs are 1 then it gives 0 otherwise 1.

• NOR Gate( )- The NOR gate (negated OR) gives an output of 1 only if both inputs are 0,
it gives 0 otherwise. For n-input gate if all inputs are 0 then it gives 1 otherwise 0.

• XNOR Gate( )- The XNOR gate (negated XOR) gives an output of 1 if both inputs are
same and 0 if they are different. For n-input gate if the number of input 1 are even then
it gives 1 otherwise odd.

• BUFFER Gate( )- The BUFFER gate is the opposite of the NOT gate, as its output is 1 if
its input is 1 and vice-versa.
• Every Logic gate has a graphical representation or symbol associated with it. Below is an
image which shows the graphical symbols and truth tables
Universal Logic Gates – Out of the eight logic gates discussed above, NAND and NOR are also known
as universal gates since they can be used to implement any digital circuit without using any other gate.

This means that every gate can be created by NAND or NOR gates only. Implementation of three basic gates
using NAND and NOR gates is shown below
 BOOLEAN ALGEBRA
• Boolean algebra is a switching algebra that deals with binary variables and
logic operations. The variables are designated by letters such as A, B, x, and
y. The three basic logic operations are AND, OR, and complement.
• A Boolean function can be expressed algebraically with binary variables,
the logic operation symbols, parentheses, and equal sign.
• For a given value of the variables, the Boolean function can be either 1 or
0.
• For example, Boolean function F = x + y’z.
• The function F is equal to 1➔ if x is 1 or if both y’ and z are equal to 1, F is
equal to 0 otherwise.
• But saying that y = 1 is equivalent to saying that y’= 0 since y is the
complement of y’. Therefore, we may say that F is equal to 1 if x =1 or if yz
=01.
• The relationship between a function and its binary variables can be
represented in a truth table.
 TRUTH TABLE
• To represent a function in a truth table we need a list of the 2^n
combinations of the n binary variables.
• It means if we have three variables(n=3) x, y and z ,there are eight (2^3=8)
possible distinct combinations for assigning bits to these three variables.
X
• The function F is equal to 1 for those combinations where x =1 or yz= 01;
it is equal to 0 for all other combinations. X Y Z F
0 0 0 0
0 0 1 1
X
0 1 0 0
F 0 1 1 0
Y
1 0 0 1
1 0 1
Z
1
1 1 0 1
1 1 1 1
• The purpose of Boolean algebra is to facilitate the analysis and design of digital circuits.
• It provides a convenient tool to:

1. Express in algebraic form a truth table relationship between binary variables.

2. Express in algebraic form the input—output relationship of logic diagrams.
3. Find simpler circuits for the same function.

A Boolean function specified by a truth table can be expressed algebraically in many different ways.
• Two ways of forming Boolean expressions are canonical and non-canonical forms.
• Canonical forms express all binary variables in every product (AND) [SOP] or sum (OR)[POS] term of the Boolean
function.
• To determine the canonical sum-of-products [SOP] form for a Boolean function F (A, B, C) A’B +C’ +ABC, which is in non-
canonical form(Since every term doesn’t contain all variables) the following steps are used:

F = A’B + C’ + ABC
= A’B(1) + (1)(1)C’ + ABC
Since x + x’ = 1 is a basic identity of Boolean algebra, replacing 1 with the missing terms in x + x’ form
F = A’B(C + C’) + (A + A’)(B + B’)C’ + ABC,
F = A’BC + A’BC’ + ABC’ + AB’C’ + A’BC’ + A’B’C’ + ABC
= A’BC + A’BC’ +ABC’ + AB’C + A’B’C’ + ABC
➢ Thus by manipulating a Boolean expression according to Boolean algebra rules, one may obtain a simpler expression that
will require fewer gates.
➢ To do so we need to know about the basic identities of Boolean algebra
 IDENTITIES OF BOOLEAN ALGEBRA
1 𝒙+𝟎=𝒙 2 𝒙. 𝟎=0
3 𝑥+1=1 4 𝑥 .1 = 1
5 𝑥+𝑥 =𝑥 6 𝑥. 𝑥=𝑥
7 𝑥 + 𝑥′ = 1 8 𝑥 + 𝑥′ = 0
9 𝑥+𝑦 =𝑦+𝑥 10 𝑥𝑦 = 𝑦𝑥
11 𝑥+ 𝑦+𝑧 = 𝑥+𝑦 +𝑧 12 𝑥 𝑦 𝑧 = 𝑥𝑦 𝑧
13 𝑥 𝑦 + 𝑧 = 𝑥𝑦 + 𝑦𝑧 14 𝑥 + 𝑦𝑧 = (𝑥 + 𝑦)(𝑥 + 𝑧)
′
15 𝑥+𝑦 = 𝑥 ′ 𝑦′ 16 𝑥𝑦 ′
= 𝑥 ′ + 𝑦′
17 𝑥′ ′
=𝑥

Identities are utilized to simplify the expression

Consider the expression AB’ + CD + AB’ + CD, since we know that x + x = x we can replace AB’ + AB’ by simply
AB’ and whole expression can be reduced to AB’ + CD consisting of two terms only instead of initial four.

Identities 15 and 16 are called DeMorgan’s theorems. DeMorgan’s theorem is very important in dealing with
NOR and NAND gates. It states that a NOR gate that performs the F (x + y)’ function is equivalent to the
function x’y’. Similarly, a NAND function can be expressed by either (xy)’ or (x’ + y’).
 Universal Gates: NOR and NAND
• NOR and NAND gates have two distinct graphic symbols, as shown
• Instead of representing a NOR gate with an OR graphic symbol followed by a
circle, we can represent it by an AND graphic symbol preceded by circles in all
inputs.
• This invert-AND symbol for the NOR gate follows from DeMorgan’s theorem
and from the convention that small circles denote complementation.
• Similarly, the NAND gate has two distinct symbols, as shown.
• NAND and NOR gates can be used to implement any Boolean function,
including basic logic gates such as AND, OR, and NOT.
• Hence, NAND and NOR gates are called as Universal gates

X X (xyz)’ X (xyz)’
X (x+y+z)’ x’y’z’=(x+y+z)’ Y
Y
Y Y
z z
z z
OR-INVERT INVERT-AND AND- INVERT INVERT-OR
A AND-OR ,
B
CANONICAL [SOP] NAND-NAND
C
IMPLEMENTATION

F A
B F1

F
F= ABC+ABC’+A’C
=AB(C+C’)+A’C
= AB + A’C

C F2
A
B
F = AB + A’C F1= (AB)’=A’+B’, F2= (A’C)’=A+C’

A’ F= F1’+F2’
C
= (A’+B’)’ + (A+C’)’
= AB + A’C
 COMPLEMENT OF A FUNCTION
• The complement of a function F when expressed in a truth table is obtained by
interchanging 1’s and 0’s in the values of F in the truth table.
• When the function is expressed in algebraic form, the complement of the
function can be derived by means of DeMorgan’s theorem.
• The general form of DeMorgan’s theorem can be
• (x1 + x2 + x3 + ... xn )’ = x1’ x2’ x3’ ...xn’
• (x1 x2 x3 ...xn )’ = x1’ + x2’ + x3’+ ... +xn’
• From the general DeMorgans theorem we can derive a simple procedure for
obtaining the complement of an algebraic expression.
• This is done by changing all OR operations to AND operations and all AND
operations to OR operations and then complementing each individual letter
variable.
• Example F = AB + C’D’ + B’D
• F (A + B)(C + D)(B + D’)
 MAP SIMPLIFICATION
• Two methods of simplifying Boolean algebraic expressions are the map method and
the tabular method.
• The map method is used for functions upto six variables. The map method is also
known as the Karnaugh map or K-map.
• To manipulate functions of a large number of variables, the tabular method also
known as the Quine-McCluskey method, is used.
• If a function to be minimized is not in a canonical form, it must first be converted
into canonical form before applying Quine-McCluskey method.
• Minterms: Each combination of the variables in a truth table is called a minterm.
➢ When expressed in a truth table a function of n variables will have 2^n minterms, equivalent to
the 2^n binary numbers obtained from n bits.
➢A Boolean function is equal to 1 for some minterms and to 0 for others.
➢The information contained in a truth table may be expressed in compact form by listing the
decimal equivalent of those minterms that produce a 1 for the function.
 EXAMPLE:
Consider the given truth table, which can be X Y Z F Minterms

expressed as a function: 0 0 0 0 X’Y’Z’

F (x, y, z) =Ʃ(1, 4, 5, 6, 7) 0 0 1 1 X’Y’Z
• The letters in parentheses list the binary
0 1 0 0 X’YZ’
variables in the order that they appear in the
truth table. 0 1 1 0 X’YZ

• The symbol Ʃ stands for the sum of the 1 0 0 1 XY’Z’

minterms that follow in parentheses.
1 0 1 1 XY’Z
• The minterms that produce 1 for the function
are listed in their decimal equivalent. 1 1 0 1 XYZ’

• The minterms missing from the list are the ones 1 1 1 1 XYZ
that produce 0 for the function.
 K-MAP
• The map is a diagram made up of squares, with each square representing one
minterm.
• The squares corresponding to minterms that produce 1 for the function are marked by
a 1 and the others are marked by a 0 or are left empty.
• By recognizing various patterns and combining squares marked by 1’s in the map, it is
possible to derive alternative algebraic expressions for the function, from which the
most convenient may be selected.
• The maps for functions of two, three, and four variables are shown below
• The number of squares in a map of n variables is 2^n .
• The 2^n minterms are listed by an equivalent decimal number for easy reference.
• B TRUTH TABLE
B 0 1 m A B
A
0 0 0
0 0 1 A B B’ B
1 0 1
A’ A’B’ A’B
1 2 3 2 1 0
A
A AB’ AB 3 1 1
3 VARIABLE K-MAP
4 VARIABLE K-MAP
 Solving an Expression Using K-Map
1. Select a K-map according to the total number of variables.
2. Identify maxterms or minterms as given in the problem.
3. For SOP, put the 1’s in the blocks of the K-map with respect to
the minterms (elsewhere 0’s).
4. For POS, putting 0’s in the blocks of the K-map with respect to
the maxterms (elsewhere 1’s).
5. Making rectangular groups that contain the total terms in the
power of two, such as 2,4,8 ..(except 1) and trying to cover as
many numbers of elements as we can in a single group.
6. From the groups that have been created in step 5, find the
product terms and then sum them up for the SOP form.
GROUPING OF MINTERMS
• Groups must contain 1, 2, 4, 8, or in general 2n cells.
• That is if n = 1, a group will contain two 1's since 21 = 2.
• If n = 2, a group will contain four 1's since 22 = 4.
• FOR n=2 (2 Variable K-MAP)
• There is only one Possible grouping of 4 adjacent min terms.
• The possible combinations of grouping 2 adjacent min terms are {(m0,
m1), (m2, m3), (m0, m2) and (m1, m3)}.
• The number of cells in 3 variable K-map is eight, since the number of variables is
three. The following figure shows 3 variable K-Map.
• There is only one possibility of grouping 8 adjacent min terms.
• The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2),
(m4, m5, m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0,
m6, m4)}.
• The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3),
(m3, m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7)
and (m2, m6)}.
•If x=0, then 3 variable K-map becomes 2 variable K-map.
The number of cells in 4 variable K-map is sixteen, since the number of variables is four.
The following figure shows 4 variable K-Map.
•There is only one possibility of grouping 16 adjacent min terms.
•Let R1, R2, R3 and R4 represents the min terms of first row, second row, third row and
fourth row respectively. Similarly, C1, C2, C3 and C4 represents the min terms of first
column, second column, third column and fourth column respectively. The possible
combinations of grouping 8 adjacent min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1), (C1,
C2), (C2, C3), (C3, C4), (C4, C1)}.
•If w=0, then 4 variable K-map becomes 3 variable K-map.
GROUPING ALLOWED/NOT ALLOWED
•Each group should be as large as possible.

•Each cell containing a one must be in at least one group.

 Groups may wrap around the table.
•Groups may overlap.
The leftmost cell in a row may be grouped with the
rightmost cell and the top cell in a column may be
grouped with the bottom cell.
We can consider the 'don't care condition' only when they
aid in increasing the group-size. Otherwise, 'don't care'
elements are discarded.
Summmary For Forming Groups:

1.No zeros allowed.

2.No diagonals.
3.Only power of 2 number of cells in each group.
4.Groups should be as large as possible.
5.Every one must be in at least one group.
6.Overlapping allowed.
7.Wrap around allowed.
8.Fewest number of groups possible.
SIMPLIFYING BOOLEAN FUNCTION USING 2 VAR. K-MAP
• A Boolean function F (A, B) = Ʃ(0,2,3) represented by a truth table is plotted
into the map by inserting 1’s in those squares where the function is 1.
• The squares containing 1’s, shown by blue and yellow colours are combined in
groups of adjacent squares where n=1.
• Each group of squares represents an algebraic term, and the OR of those terms
gives the simplified algebraic expression for the function.
• (A’B’+AB’+AB)=A’B’+A(B+B’)=A’B’+A
A/B B’ B not correct since grouping must
A/B B’ B
A’ 1 0
A’ 0 1 have at least 2^1 ( 2) 1’s
A 1 1
A 2 3
A/B B’ B
B’ + A
A’ 1 0
A 1 1
Example 1: Y=A'B' + A'B+AB Example 2: Y=A'B'C'+A' BC'+AB' C'+AB' C+ABC'+ABC

A B F Min terms B➔ B’C’ B’C BC BC’

0 0 1 A’B’ [0] A [00] [01] [11] [10]
0 1 1 A’B [1] A’ [0] 0 0 1 1
Y = A+B
1 0 0 AB’ [2] A [1] 1 1 1 1

1 1 1 AB [3]

A/B B’ B Z = ∑(1, 3, 6, 7)=A’C+AB

K-MAP
A’ 0 1

A 2 3

A/B B’ B
Yellow group gives A’(B+B’) = A’
A’ 1 1
Blue group gives B(A’+A) = B
Adding all terms give POS = A’+B
A 0 1
Simplify Functions using K-MAP
1. F = WX’Y’ + WY + W’YZ’ .
YZ Y’Z’ Y’Z YZ YZ’
No. of variables = 4 , K-MAP = 4 variable

WX 00 01 11 10 FOR EASE OF CONVINENCE CONVERT THE

EXPRESSION INTO CANONICAL FORM FIRST
W’X’ 00 1
WX’Y’(Z+Z’)+WY(Z+Z’)(X+X’) + W’YZ’(X+X’)
W’X 01 1
=WX’Y’Z+WX’Y’Z’+WYZX+WYZX’+WYZ’X+W
WX 11 1 1
YZ’X’+W’YZ’X+W’YZ’X’
WX’ 10 1 1 1 1

Simplifying K-MAP we get :

F = W’X’ + YZ’ + WY
2. F = ∑(0, 2, 5, 7, 8, 10, 13, 15)

SOLVING K-MAP F = QS + Q’S’

 Don’t-Care Conditions
• The 1’s and 0’s in the map represent the minterms that make the function equal to
1 or 0.
• There are occasions when it does not matter if the function produces 0 or 1 for a
given minterm.
• Since the function may be either 0 or 1, we say that we don’t care what the
function output is to be for this minterm.
• Minterms that may produce either 0 or 1 for the function are said to be don’t-care
conditions and are marked with an (X) in the map.
• These don’t-care conditions can be used to provide further simplification of the
algebraic expression.
• When choosing adjacent squares for the function in the map, the s may be
assumed to be either 0 or 1, whichever gives the simplest expression.
• In addition, an X need not be used at all if it does not contribute to the
simplification of the function.
• In each case, the choice depends only on the simplification that can be achieved.
EXAMPLE: F (A, B, C) = Ʃ (0, 2, 6)
d (A, B, C ) = Ʃ (1, 3, 5)
A/B B’C’ B’C BC BC’

A’ 1 x x 1

A 0 x 0 1

Simplified function using don’t care condition is F = A’ + BC’

Without using don’t care the function reduced to F = A’C’ + BC’
Which requires two AND gates and one OR gate for
implemented whereas we need only one AND gate and one OR
gate reducing the Hardware
1. F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
2. F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
3. F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)
4. F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)
5. F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)
6. F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 4, 5)
7. F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)
8. F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)
9. F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14)
SOLUTIONS

1. BD+C’D+B’D’
2. F(A, B, C, D) = B’C’ + D
3. F(A, B, C, D) = AD + B’D + B’C’ + A’D’
4. F(A, B, C) = AB + A’B’
5. F(A, B, C) = A + B’ + C’
6. F(A, B, C) = A + B’
7. F(A, B, C, D) = ACD’ + B’D’
8. F(A, B, C, D) = A’BC’ + A’CD + AC’D + ABC
9. F(W, X, Y, Z) = X ⊕ Z
1 C’D’ C’D CD CD’ 2 C’D’ C’D CD CD’ 3 C’D’ C’D CD CD’ 4 B’C’ B’C BC BC’

A’B’ 1 1 1 A’B’ 1 1 1 A’B’ x 1 1 x A’ 1 1 x

A’B 1 1 A’B 1 1 A’B 1 1 A x 1 1
AB 1 1 AB 1 1 AB 1 1 x
AB’ 1 1 1 AB’ 1 1 1 AB’ 1 1 1

5 B’C’ B’C BC BC’

6 B’C’ B’C BC BC’ C’D’ C’D CD CD’
7
A’ x 1 1
A’ 1 1 x A’B’ 1 1
A x 1 1 X
A x x 1 1 A’B x
AB x ’ 1
8 C’D’ C’D CD CD’ 9 C’D’ C’D CD CD’ AB’ 1 1

A’B’ 1 A’B’ 1 1
A’B 1 1 1 A’B 1 1
AB 1 1 1 AB 1 1
AB’ 1 AB’ 1 1
 POS (PRODUCT OF SUM) SIMPLIFICSTION
• The procedure for obtaining a product-of-sums expression follows from
the basic properties of Boolean algebra.
• The 1’s in the map represent the minterms that produce 1 for the
function.
• The squares not marked by 1 represent the minterms that produce 0
for the function.
• If we mark the empty squares with 0’s and combine them into groups
of adjacent squares, we obtain the complement of the function, F.
• Taking the complement of F produces an expression for F in product-
of-sums form.
EXAMPLE: F(A, B, C, D) (0, 1, 2, 5, 8, 9, 10).
POS C’D’ C’D CD CD’ SOP C’D’ C’D CD CD’

A’B’ 1 1 0 1 A’B’ 0

A’B 0 1 0 0 A’B 0 0

AB 0 0 0 0 AB 0 0 0 0

AB’ 1 1 0 1 AB’ 0

F = B’D’ + B’C’ + A’C’D F’ =AB + CD + BD’

F = F’’ = (AB+CD+BD’)’
F = (A’+B’)(C’+D’)(B’+D)
 COMBINATIONAL CIRCUITS

Digital Logic Circuits

Combinational Circuit Sequential Circuits

No Feedback Feedback Paths Exist

Path from o/p to No Memory
i/p Memory Exist
 COMBINATIONAL CIRCUIT
A combinational circuit is a circuit in which the output depends on the
present combination of inputs. Combinational circuits are made up of logic
gates. The output of each logic gate is determined by its logic function.
At any given time, the binary values of the outputs are a function of the
binary combination of the inputs. A block diagram of a combinational circuit is
shown in Fig. below. The n binary input variables come from an external source,
the m binary output variables go to an external destination, and in between
there is an interconnection of logic gates.
• Applications of Combinational Circuits
• A combinational circuit is an electronic circuit in which the output depends on the present combination
of inputs. Combinational circuits are used in digital electronics, such as computers, to perform
operations on data.
• An example of a combinational circuit is a full adder, which takes two binary digits as input and
produces a sum bit and a carry bit as output. Full adders are used in many digital devices, including
calculators and computers.
• Another example of a combinational circuit is a multiplexer. A multiplexer takes several input signals
and selects one of them to be passed to the output. Multiplexers are used in many applications,
including data communication and computer memory.
• Combinational circuits can be made using various logic gates, such as AND gates, OR gates, and NOT
gates.
Types of Combinational Circuits
• There are three main types of combinational circuits: decoders, encoders, and multiplexers.
1.Decoders are combinational circuits that convert binary code into a form that can be read by a human.
For example, a decoder might take a four-bit binary number and convert it into a seven-segment
display.
2.Encoders are combinational circuits that convert information from one form to another. For example,
an encoder might take a seven-segment display and convert it into a four-bit binary number.
3.Multiplexers are combinational circuits that select one of several input signals and send it to the
output. For example, a multiplexer might take four input signals and send only one of them to the
output.
COMBINATIONAL CIRCUIT ANALYSIS

A combinational circuit can be described by a truth table showing the binary relationship between the n input
variables and the m output variables.
The truth table lists the corresponding output binary values for each of the 2n input combinations.
A combinational circuit can also be specified with m Boolean functions, one for each output variable. Each
output function is expressed in terms of the n input variables.
The analysis of a combinational circuit starts with a given logic circuit diagram and culminates with a set of
Boolean functions or a truth table.

COMBINATIONAL CIRCUIT DESIGN

The design of combinational circuits starts from the verbal outline of the problem and ends in a logic circuit
diagram. The procedure involves the following stepsThe following are the basic steps to design a combinational
circuits
1. Define the problem.
2. Determine the number of input and output variables.
3. Fix a letter symbols to the input and the outputs. (eg. A,B,C ,w, x, Y,F, etc)
4. Get the relationship between input and output from the truth table.
5. By using K-map obtain the simplified Boolean expression for the outputs.
6. Draw the logic diagram using gates.
 HALF ADDER
• The most basic digital arithmetic circuit is the addition of two binary digits.
• A combinational circuit that performs the arithmetic addition of two bits is
called a halfadder.
• One that performs the addition of three bits (two significant bits and a
previous carry) is called a full-adder. The name of the former stems from the
fact that two half-adders are needed to implement a full-adder.
• The input variables of a half-adder are called the augend and addend bits.
• The output variables the sum and carry. It is necessary to specify two output
variables because the sum of 1 1 is binary 10, which has two digits.
• We assign symbols x and y to the two input variables, and S (for sum) and C (for
carry) to the two output variables.
• The truth table for the half-adder is shown in Fig. The C output is 0 unless both
inputs are 1. The S output represents the least significant bit of the sum. The
Boolean functions for the two outputs can be obtained directly from the truth
table:
TRUTH TABLE OF HALF ADDER
INPUTS OUTPUTS
Boolean Functions Corresponding To
Output Carry And Sum
X Y S C S = X’Y + XY’ = X ꚚY
C = XY
0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

LOGIC DIAGRAM
 FULL ADDER
• Full adder is developed to overcome the drawback of Half Adder
circuit. It can add two one-bit numbers A and B, and carry c.
• The full adder is a three input and two output combinational circuit.
• The three inputs of the full adders are augend , addend and the carry
input from the previous addition, the outputs are sum and carry.
TRUTH TABLE:
The eight rows under the input variables designate all possible combinations that the binary variables may
have.
The value of the output variables are determined from the arithmetic sum of the input bits.
When all input bits are 0, the output is 0.
The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1.
The C output has a carry of 1 if two or three inputs are equal to 1.
INPUTS SUM CARRY
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
BOOLEAN FUNCTION FOR SUM AND CARRY FROM TT
S= A’B’C + A’BC’ + AB’C’+ABC
C= A’BC+AB’C+ABC’ +ABC = (A’B+AB’)C +AB(C+C’) = (A Ꚛ B) C + AB
SIMPLIFYING USING K-MAP

SUM B’C’ B’C BC BC’ CARRY B’C’ B’C BC BC’

A’ 1
A’ 1
A 1 1
A 1 1 1

SUM{S} = A’B’C+A’BC’+AB’C’+ABC
= (A’B’ + AB)C + (A’B + AB’)C’
= (A’B+AB’)’C + (A’B+AB’)C’ [(A’B+AB’)’ = (A+B’)(A’+B)= AA’ + AB + B’A’+BB’ = AB+A’B’]
= (AꚚ B)’C + (A Ꚛ B)C’
= AꚚBꚚC

CARRY{C} = BC + AB + AC
FULL ADDER
(Design 1)
FULL ADDER (Design 2 : using Half Adder)
ASSIGNMENT DESIGN A SUBTRACTOR CIRCUIT
(Half Subtractor and Full Subtractor)

Subtractor is the logic circuit which is used to subtract two binary number (digit) and
provides Difference and Borrow as a output. There are two types of subtractor, Half
Subtractor and Full Subtractor. Half subtractor is used to subtract two digits whereas Full
Subtractor is used to subtract three digits.

RULES FOR TWO BIT SUBTRACTION

0-0=0
0 - 1 = 1 with borrow 1
1-0=1
1-1=0
STEPS TO FOLLOW
1. Construct TT
2. Define Boolean Functions FOR S and B
3. Simplify using K-MAP
4. Design CIrcuit
HALF SUBTRACTOR
FULL SUBTRACTOR
 SEQUENTIAL CIRCUITS
• Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals
present at that time are known as combinational circuits.
• On the other hand, the logic circuits whose outputs at any instant of time depend on the present inputs as
well as on the past outputs are called sequential circuits.
• In sequential circuits, the output signals are fed back to the input side. It consists of a combinational circuit
to which storage elements are connected to form a feedback path
• The storage elements are devices capable of storing binary information. The binary information stored in
these elements at any given time defines the state of the sequential circuit at that time.
• The sequential circuit receives binary information from external inputs
that, together with the present state of the storage elements,
determine the binary value of the outputs.
• These external inputs also determine the condition for changing the
state in the storage elements.
• The block diagram demonstrates that the outputs in a sequential
circuit are a function not only of the inputs, but also of the present
state of the storage elements.
• The next state of the storage elements is also a function of external
inputs and the present state.
 TYPES OF SEQUENTIAL CIRCUITS
Synchronous Sequential Circuit:
• A sequential circuit whose behavior depends upon the sequence in which the input signals change is referred
to as an asynchronous sequential circuit.
• The output will be affected whenever the input changes. The commonly used memory elements in these
circuits are time-delay devices.
• There is no need to wait for a clock pulse. Therefore, in general, asynchronous circuits are faster than
synchronous sequential circuits.
• However, in an asynchronous circuit, events are allowed to occur without any synchronization. And in such a
case, the system becomes unstable.
• Since the designs of asynchronous circuits are more tedious and difficult, their uses are rather limited. The
memory elements used in sequential circuits are flip-flops which are capable of storing binary information.

Synchronous sequential circuit:

• A sequential circuit whose behavior can be defined from the knowledge of its signal at discrete instants of
time is referred to as a synchronous sequential circuit.
• In these systems, the memory elements are affected only at discrete instants of time.
• The synchronization is achieved by a timing device known as a system clock, which generates a periodic train
of lock pulses. The outputs are affected only with the application of a clock pulse.
CLOCK SIGNAL AND TRIGGERING
Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the same.
When ON time and OFF time of the clock signal are the same, a square wave is used to
represent the clock signal. Below is a diagram which represents the clock signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at logic, either
high 5V or low 0V, to an equal amount of time. It repeats with a certain time period, which
will be equal to twice the 'ON time' or 'OFF time’.
TYPES OF TRIGGERING

LEVEL EDGE
TRIGGERING TRIGGERING

Positive Level Positive edge

Triggering Triggering

Negative Level Negative Edge

Triggering Triggering
 FLIP FLOPS
• The storage elements employed in clocked sequential circuits are called
flipflops.
• A flip-flop is a binary cell capable of storing one bit of information.
• It has two outputs, one for the normal value and one for the complement value
of the bit stored in it.
• A flip-flop maintains a binary state until directed by a clock pulse to switch
states.
• The difference among various types of flip-flops is in the number of inputs they
possess and in the manner in which the inputs affect the binary state.
• The most common types of flip-flops are SR- F/F, JK- F/F, D - F/F, T - F/F .
 SR FLIP FLOP
• The graphic symbol of the SR flip-flop is shown in Fig. below.
• It has three inputs, labeled S (for set), R (for reset), and C (for clock).
• It has an output Q and sometimes the flip-flop has a complemented output,
which is indicated with a small circle at the other output terminal.
• There is an arrowhead-shaped symbol in front of the letter C to designate a
dynamic input. The dynamic indicator symbol denotes the fact that the flip-
flop responds to a positive transition (from 0 to 1) of the input clock signal.
S R Q(t+1)
S Q
0 0 Q(t) : No Change
0 1 Clear to 0
C
1 0 Set to 1
R 1 1 Indeterminant

GRAPHICAL SYMBOL CHARACTERISTIC TABLE

 OPERATION OF SR FLIP-FLOP
• If there is no signal at the clock input C, the output of the circuit cannot
change irrespective of the values at inputs S and R.
• Only when the clock signal changes from 0 to 1 can the output be affected
according to the values in inputs S and R.
• If both S and R are 0 during the clock transition, the output does not change.
• RESET: If S = 0 and R = 1 when C changes from 0 to 1, output Q is cleared to
0.
• SET: If S = 1 and R = 0 when C changes from 0 to 1, output Q is set to 1.
• When both S and R are equal to 1, the output is unpredictable and may go to
either 0 or 1, depending on internal timing delays that occur within the
circuit.
• Q(t) is the binary state of the Q output at a given time (referred to as present
state). Q(t 1) is the binary state of the Q output after the occurrence of a
clock transition (referred to as next state). I
 D Flip-Flop
• The D (data) flip-flop is a slight modification of the SR flip-flop.
• An SR flip-flop is converted to a D flip-flop by inserting an inverter between S and R and
assigning the symbol D to the single input.
• The D input is sampled during the occurrence of a clock transition from 0 to 1.
• RESET STATE: If D = 0, the output of the flip-flop goes to the 0 state.
• SET STATE: If D = 1, the output of the flip-flop goes to the 1 state,
• The graphic symbol and characteristic table of the D flip-flop are shown in Fig.
D Q D Q(t+1)
0 0 Clear to 0
C
1 1 Set to 1

• Here Q(t +1) = D means that the Q output of the flip-flop receives its value from the D input
every time that the clock signal goes through a transition from 0 to 1
 J K FLIP-FLOP
• A JK flip-flop is a refinement of the SR flip-flop. The J input is equivalent to the S (set) input
of the SR flip-flop, and the K input is equivalent to the R (clear) input.
• Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively.
• The indeterminate condition of the SR type is defined in the JK type means when inputs J
and K are both equal to 1, a clock transition switches the outputs of the flip-flop to their
complement state.
• The graphic symbol and characteristic table of the JK flip-flop are shown in Fig.
J Q J K Q(t+1)
0 0 Q(t)
C
0 0 0
K
1 0 1

1 1 Q(t)’
 T FLIP FLOP
• Another type of flip-flop is the T (toggle) flip-flop.
• This flip-flop is obtained from a JK type when inputs J and K are connected to provide a
single input designated by T.
• The T flip-flop therefore has only two conditions.
• When T = 0 ( J = K = 0) a clock transition does not change the state of the flip-flop.
• When T = 1 ( J = K =1) a clock transition complements the state of the flip-flop.
• These conditions can be expressed by a characteristic equation Q(t+1)=Q(t)ꚚT

T Q T Q(t+1)
0 Q(t) No Change
1 Q(t+1)’ Complement
C
 MASTER SLAVE FLIP FLOPS
• Another type of flip-flop used in some systems is the master-slave flip-flop.
• This type of circuit consists of two flip-flops.
• The first is the master, which responds to the positive level of the clock, and
the second is the slave, which responds to the negative level of the clock.
• The result is that the output changes during the 1-to-0 transition of the clock
signal.
• The trend is away from the use of master-slave flip-flops and toward edge-
triggered flip-flops.
• Flip-flops available in integrated circuit packages will sometimes provide
special input terminals for setting or clearing the flip-flop asynchronously.
These inputs are usually called “preset” and “clear.”
• They affect the flip-flop on a negative level of the input signal without the
need of a clock pulse.
• These inputs are useful for bringing the flip-flops to an initial state prior to its
clocked operation.