# Performance Monitoring Events for Intel(R) Xeon(R) Processor Scalable Family

based on Skylake microarchitecture - V1.35

# 04/03/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE UMASK NAME DESCRIPTION COUNTER COUNTER_HT_OFF OVERFLOW MSR_INDEX
MSR_VALUE PRECISE_EVENT TAKEN_ALONE SAV_LOWER_LIMIT OTHER LATENCY
DEFAULT EM_TRIGGER DATA_LA L1_HIT_INDICATION WORKAROUND MATRIX_EVENT
BRANCH_EVT PRECISE_FE EVENT_STATUS
0x00 0x01 INST_RETIRED.ANY Instructions retired from execution. 32 32
2000003 0 0 0 0 5 0x53 0 1 1 0 0
0 0 0 0 0x00
0x00 0x02 CPU_CLK_UNHALTED.THREAD Core cycles when the thread is not in halt
state 33 33 2000003 0 0 0 0 5 0x53 0 1 1
0 0 0 0 0 0 0x00
0x00 0x02 CPU_CLK_UNHALTED.THREAD_ANY Core cycles when at least one thread on
the physical core is not in halt state. 33 33 2000003 0 0 0
0 5 0x73 0 0 1 0 0 0 0 0 0 0x00
0x00 0x03 CPU_CLK_UNHALTED.REF_TSC Reference cycles when the core is not in
halt state. 34 34 2000003 0 0 0 0 5 0x53 0 1
2 0 0 0 0 0 0 0x00
0x03 0x02 LD_BLOCKS.STORE_FORWARD Loads blocked due to overlapping with a
preceding store that cannot be forwarded. 0,1,2,3 0,1,2,3,4,5,6,7 100003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x03 0x08 LD_BLOCKS.NO_SR The number of times that split load operations are
temporarily blocked because all resources for handling the split accesses are in
use 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x07 0x01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS False dependencies in MOB due to
partial compare on address. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x08 0x01 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK Load misses in all DTLB levels that
cause page walks 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x08 0x02 DTLB_LOAD_MISSES.WALK_COMPLETED_4K Page walk completed due to a demand
data load to a 4K page 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x08 0x04 DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Page walk completed due to a
demand data load to a 2M/4M page 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x08 0x08 DTLB_LOAD_MISSES.WALK_COMPLETED_1G Page walk completed due to a demand
data load to a 1G page 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x08 0x0e DTLB_LOAD_MISSES.WALK_COMPLETED Load miss in all TLB levels causes
a page walk that completes. (All page sizes) 0,1,2,3 0,1,2,3,4,5,6,7 100003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x08 0x10 DTLB_LOAD_MISSES.WALK_PENDING Counts 1 per cycle for each PMH that is
busy with a page walk for a load. EPT page walk duration are excluded in Skylake.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x08 0x10 DTLB_LOAD_MISSES.WALK_ACTIVE Cycles when at least one PMH is busy with
a page walk for a load. EPT page walk duration are excluded in Skylake.
0,1,2,3 0,1,2,3,4,5,6,7 100003 0x00 0x00 0 0 5 0x153
0 0 0 0 0 0 0 0 0 0x00
0x08 0x20 DTLB_LOAD_MISSES.STLB_HIT Loads that miss the DTLB and hit the
STLB. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
 0 0 0 0 0 0 0 0 0 0x00
0x09 0x01 MEMORY_DISAMBIGUATION.HISTORY_RESET MEMORY_DISAMBIGUATION.HISTORY_RESET
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x0D 0x01 INT_MISC.RECOVERY_CYCLES Core cycles the allocator was stalled due
to recovery from earlier clear event for this thread (e.g. misprediction or memory
nuke) 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x0D 0x01 INT_MISC.RECOVERY_CYCLES_ANY Core cycles the allocator was stalled due
to recovery from earlier clear event for any thread running on the physical core
(e.g. misprediction or memory nuke). 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x73 0 0 0 0 0 0 0
0 0 0x00
0x0D 0x01 INT_MISC.CLEARS_COUNT Clears speculative count 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x157 0 0
0 0 0 0 0 0 0 0x00
0x0D 0x80 INT_MISC.CLEAR_RESTEER_CYCLES Cycles the issue-stage is waiting for
front-end to fetch from resteered path following branch misprediction or machine
clear events. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x0E 0x01 UOPS_ISSUED.ANY Uops that Resource Allocation Table (RAT) issues to
Reservation Station (RS) 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x0E 0x01 UOPS_ISSUED.STALL_CYCLES Cycles when Resource Allocation Table
(RAT) does not issue Uops to Reservation Station (RS) for the thread 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x1D3 0 0
0 0 0 0 0 0 0 0x00
0x0E 0x02 UOPS_ISSUED.VECTOR_WIDTH_MISMATCH Uops inserted at issue-stage in
order to preserve upper bits of vector registers. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0x00 0x00 0 0 5 0x53 0 0 0 0 0
0 0 0 0 0x00
0x0E 0x20 UOPS_ISSUED.SLOW_LEA Number of slow LEA uops being allocated. A uop
is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate)
regardless if as a result of LEA instruction or not. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x14 0x01 ARITH.DIVIDER_ACTIVE Cycles when divide unit is busy executing
divide or square root operations. Accounts for integer and floating-point
operations. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x153 0 0 0 0 0 0 0 0 0 0x00
0x24 0x21 L2_RQSTS.DEMAND_DATA_RD_MISS Demand Data Read miss L2, no rejects
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x24 0x22 L2_RQSTS.RFO_MISS RFO requests that miss L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x24 0x24 L2_RQSTS.CODE_RD_MISS L2 cache misses when fetching instructions
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x24 0x27 L2_RQSTS.ALL_DEMAND_MISS Demand requests that miss L2 cache
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x24 0x38 L2_RQSTS.PF_MISS Requests from the L1/L2/L3 hardware prefetchers or
Load software prefetches that miss L2 cache 0,1,2,3 0,1,2,3,4,5,6,7 200003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x24 0x3F L2_RQSTS.MISS All requests that miss L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
 0 0 0 0 0 0 0 0x00
0x24 0xc1 L2_RQSTS.DEMAND_DATA_RD_HIT Demand Data Read requests that hit L2
cache 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x24 0xc2 L2_RQSTS.RFO_HIT RFO requests that hit L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x24 0xc4 L2_RQSTS.CODE_RD_HIT L2 cache hits when fetching instructions, code
reads. 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0x24 0xd8 L2_RQSTS.PF_HIT Requests from the L1/L2/L3 hardware prefetchers or
Load software prefetches that hit L2 cache 0,1,2,3 0,1,2,3,4,5,6,7 200003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x24 0xE1 L2_RQSTS.ALL_DEMAND_DATA_RD Demand Data Read requests 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x24 0xE2 L2_RQSTS.ALL_RFO RFO requests to L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x24 0xE4 L2_RQSTS.ALL_CODE_RD L2 code requests 0,1,2,3 0,1,2,3,4,5,6,7
200003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x24 0xe7 L2_RQSTS.ALL_DEMAND_REFERENCES Demand requests to L2 cache
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x24 0xF8 L2_RQSTS.ALL_PF Requests from the L1/L2/L3 hardware prefetchers or
Load software prefetches 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x24 0xFF L2_RQSTS.REFERENCES All L2 requests 0,1,2,3 0,1,2,3,4,5,6,7
200003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x28 0x07 CORE_POWER.LVL0_TURBO_LICENSE Core cycles where the core was running in
a manner where Turbo may be clipped to the Non-AVX turbo schedule. 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x28 0x18 CORE_POWER.LVL1_TURBO_LICENSE Core cycles where the core was running in
a manner where Turbo may be clipped to the AVX2 turbo schedule. 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x28 0x20 CORE_POWER.LVL2_TURBO_LICENSE Core cycles where the core was running in
a manner where Turbo may be clipped to the AVX512 turbo schedule. 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x28 0x40 CORE_POWER.THROTTLE Core cycles the core was throttled due to a
pending power level request. 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x2E 0x41 LONGEST_LAT_CACHE.MISS Core-originated cacheable demand requests
missed L3 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0
0x53 0 0 0 0 0 SKL057 0 0 0 0x00
0x2E 0x4F LONGEST_LAT_CACHE.REFERENCE Core-originated cacheable demand requests
that refer to L3 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 SKL057 0 0 0 0x00
0x32 0x01 SW_PREFETCH_ACCESS.NTA Number of PREFETCHNTA instructions executed.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x32 0x02 SW_PREFETCH_ACCESS.T0 Number of PREFETCHT0 instructions executed.
 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x32 0x04 SW_PREFETCH_ACCESS.T1_T2 Number of PREFETCHT1 or PREFETCHT2
instructions executed. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x32 0x08 SW_PREFETCH_ACCESS.PREFETCHW Number of PREFETCHW instructions
executed. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0x32 0x0F SW_PREFETCH_ACCESS.ANY Counts the number of PREFETCHNTA, PREFETCHW,
PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x3C 0x00 CPU_CLK_UNHALTED.THREAD_P Thread cycles when thread is not in halt
state 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 5 0x53
0 0 1 0 0 0 0 0 0 0x00
0x3C 0x00 CPU_CLK_UNHALTED.THREAD_P_ANY Core cycles when at least one thread on
the physical core is not in halt state. 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 5 0x73 0 0 0 0 0 0 0
0 0 0x00
0x3C 0x00 CPU_CLK_UNHALTED.RING0_TRANS Counts when there is a transition from
ring 1, 2 or 3 to ring 0. 0,1,2,3 0,1,2,3,4,5,6,7 100007 0 0
0 0 0 0x157 0 0 0 0 0 0 0 0 0
0x00
0x3C 0x01 CPU_CLK_THREAD_UNHALTED.REF_XCLK Core crystal clock cycles when the
thread is unhalted. 0,1,2,3 0,1,2,3,4,5,6,7 25003 0 0 0 0
5 0x53 0 0 3 0 0 0 0 0 0 0x00
0x3C 0x01 CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY Core crystal clock cycles
when at least one thread on the physical core is unhalted. 0,1,2,3
0,1,2,3,4,5,6,7 25003 0 0 0 0 5 0x73 0 0 0
0 0 0 0 0 0 0x00
0x3C 0x01 CPU_CLK_UNHALTED.REF_XCLK Core crystal clock cycles when the thread
is unhalted. 0,1,2,3 0,1,2,3,4,5,6,7 25003 0 0 0 0 5
0x53 0 0 3 0 0 0 0 0 0 0x00
0x3C 0x01 CPU_CLK_UNHALTED.REF_XCLK_ANY Core crystal clock cycles when at least
one thread on the physical core is unhalted. 0,1,2,3 0,1,2,3,4,5,6,7 25003
0 0 0 0 5 0x73 0 0 0 0 0 0 0
0 0 0x00
0x3C 0x02 CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE Core crystal clock cycles
when this thread is unhalted and the other thread is halted. 0,1,2,3
0,1,2,3,4,5,6,7 25003 0 0 0 0 5 0x53 0 0 0
0 0 0 0 0 0 0x00
0x3C 0x02 CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Core crystal clock cycles when this
thread is unhalted and the other thread is halted. 0,1,2,3 0,1,2,3,4,5,6,7
25003 0x00 0x00 0 0 5 0x53 0 0 0 0 0 0
0 0 0 0x00
0x48 0x01 L1D_PEND_MISS.PENDING L1D miss outstandings duration in cycles
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x48 0x01 L1D_PEND_MISS.PENDING_CYCLES Cycles with L1D load Misses outstanding.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153
0 0 0 0 0 0 0 0 0 0x00
0x48 0x01 L1D_PEND_MISS.PENDING_CYCLES_ANY Cycles with L1D load Misses
outstanding from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0x00 0x00 0 0 5 0x173 0 0 0 0 0
0 0 0 0 0x00
0x48 0x02 L1D_PEND_MISS.FB_FULL Number of times a request needed a FB entry but
there was no entry available for it. That is the FB unavailability was dominant
reason for blocking the request. A request includes cacheable/uncacheable demands
that is load, store or SW prefetch. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
 0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x49 0x01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK Store misses in all DTLB
levels that cause page walks 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x49 0x02 DTLB_STORE_MISSES.WALK_COMPLETED_4K Page walk completed due to a demand
data store to a 4K page 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x49 0x04 DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Page walk completed due to a
demand data store to a 2M/4M page 0,1,2,3 0,1,2,3,4,5,6,7 100003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x49 0x08 DTLB_STORE_MISSES.WALK_COMPLETED_1G Page walk completed due to a demand
data store to a 1G page 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x49 0x0e DTLB_STORE_MISSES.WALK_COMPLETED Store misses in all TLB levels
causes a page walk that completes. (All page sizes) 0,1,2,3 0,1,2,3,4,5,6,7
100003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x49 0x10 DTLB_STORE_MISSES.WALK_PENDING Counts 1 per cycle for each PMH
that is busy with a page walk for a store. EPT page walk duration are excluded in
Skylake. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0x49 0x10 DTLB_STORE_MISSES.WALK_ACTIVE Cycles when at least one PMH is busy with
a page walk for a store. EPT page walk duration are excluded in Skylake.
0,1,2,3 0,1,2,3,4,5,6,7 100003 0x00 0x00 0 0 5 0x153
0 0 0 0 0 0 0 0 0 0x00
0x49 0x20 DTLB_STORE_MISSES.STLB_HIT Stores that miss the DTLB and hit the
STLB. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x4C 0x01 LOAD_HIT_PRE.SW_PF Demand load dispatches that hit L1D fill buffer
(FB) allocated for software prefetch. 0,1,2,3 0,1,2,3,4,5,6,7 100003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x4f 0x10 EPT.WALK_PENDING Counts 1 per cycle for each PMH that is busy with a
EPT (Extended Page Table) walk for any request type. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x51 0x01 L1D.REPLACEMENT L1D data line replacements 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x54 0x01 TX_MEM.ABORT_CONFLICT Number of times a transactional abort was
signaled due to a data conflict on a transactionally accessed address 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x54 0x02 TX_MEM.ABORT_CAPACITY Number of times a transactional abort was
signaled due to a data capacity limitation for transactional reads or writes.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x54 0x04 TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK Number of times a HLE
transactional region aborted due to a non XRELEASE prefixed instruction writing to
an elided lock in the elision buffer 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x54 0x08 TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY Number of times an HLE
transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x54 0x10 TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH Number of times an HLE
transactional execution aborted due to XRELEASE lock not satisfying the address and
value requirements in the elision buffer 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x54 0x20 TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT Number of times an
HLE transactional execution aborted due to an unsupported read alignment from the
elision buffer. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x54 0x40 TX_MEM.HLE_ELISION_BUFFER_FULL Number of times HLE lock could not
be elided due to ElisionBufferAvailable being zero. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x55 0x01 INST_DECODED.DECODERS Instruction decoders utilized in a cycle
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x59 0x01 PARTIAL_RAT_STALLS.SCOREBOARD Cycles where the pipeline is stalled due
to serializing operations. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x5d 0x01 TX_EXEC.MISC1 Counts the number of times a class of instructions
that may cause a transactional abort was executed. Since this is the count of
execution, it may not always cause a transactional abort. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x5d 0x02 TX_EXEC.MISC2 Counts the number of times a class of instructions
(e.g., vzeroupper) that may cause a transactional abort was executed inside a
transactional region 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x5d 0x04 TX_EXEC.MISC3 Counts the number of times an instruction execution
caused the transactional nest count supported to be exceeded 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x5d 0x08 TX_EXEC.MISC4 Counts the number of times a XBEGIN instruction was
executed inside an HLE transactional region. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x5d 0x10 TX_EXEC.MISC5 Counts the number of times an HLE XACQUIRE
instruction was executed inside an RTM transactional region0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x5E 0x01 RS_EVENTS.EMPTY_CYCLES Cycles when Reservation Station (RS) is empty
for the thread 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x5E 0x01 RS_EVENTS.EMPTY_END Counts end of periods where the Reservation
Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound
issues. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x1D7 0 0 0 0 0 0 0 0 0 0x00
0x60 0x01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD Offcore outstanding
Demand Data Read transactions in uncore queue. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x60 0x01 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Cycles when
offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ),
queue to uncore 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x153 0 0 0 0 0 0 0 0 0 0x00
0x60 0x01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 Cycles with at
least 6 offcore outstanding Demand Data Read transactions in uncore queue.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0x00 0x00 0 0 5 0x653
 0 0 0 0 0 0 0 0 0 0x00
0x60 0x02 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD Offcore outstanding Code
Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x60 0x02 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD Cycles with
offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to
uncore. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x153 0 0 0 0 0 0 0 0 0 0x00
0x60 0x04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Offcore outstanding demand
rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x60 0x04 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Cycles with
offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to
uncore. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x153 0 0 0 0 0 0 0 0 0 0x00
0x60 0x08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD Offcore outstanding cacheable
Core Data Read transactions in SuperQueue (SQ), queue to uncore 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x60 0x08 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Cycles when
offcore outstanding cacheable Core Data Read transactions are present in SuperQueue
(SQ), queue to uncore. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x153 0 0 0 0 0 0 0 0 0 0x00
0x60 0x10 OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD Counts number of
Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ
every cycle. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x60 0x10 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD Cycles
with at least 1 Demand Data Read requests who miss L3 cache in the superQ.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0x00 0x00 0 0 5 0x153
0 0 0 0 0 0 0 0 0 0x00
0x60 0x10 OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6 Cycles with
at least 6 Demand Data Read requests that miss L3 cache in the superQ. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0x00 0x00 0 0 5 0x653 0 0
0 0 0 0 0 0 0 0x00
0x79 0x04 IDQ.MITE_UOPS Uops delivered to Instruction Decode Queue (IDQ) from
MITE path 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0x79 0x04 IDQ.MITE_CYCLES Cycles when uops are being delivered to Instruction
Decode Queue (IDQ) from MITE path 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x153 0 0 0 0 0 0 0 0
0 0x00
0x79 0x08 IDQ.DSB_UOPS Uops delivered to Instruction Decode Queue (IDQ) from
the Decode Stream Buffer (DSB) path 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x79 0x08 IDQ.DSB_CYCLES Cycles when uops are being delivered to Instruction
Decode Queue (IDQ) from Decode Stream Buffer (DSB) path 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153 0 0
0 0 0 0 0 0 0 0x00
0x79 0x10 IDQ.MS_DSB_CYCLES Cycles when uops initiated by Decode Stream Buffer
(DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode
Sequencer (MS) is busy 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x153 0 0 0 0 0 0 0 0 0 0x00
0x79 0x18 IDQ.ALL_DSB_CYCLES_4_UOPS Cycles Decode Stream Buffer (DSB) is
delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x453 0 0
 0 0 0 0 0 0 0 0x00
0x79 0x18 IDQ.ALL_DSB_CYCLES_ANY_UOPS Cycles Decode Stream Buffer (DSB) is
delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153 0 0
0 0 0 0 0 0 0 0x00
0x79 0x18 IDQ.DSB_CYCLES_OK Cycles Decode Stream Buffer (DSB) is delivering 4 or
more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x453 0 0
0 0 0 0 0 0 0 0x00
0x79 0x18 IDQ.DSB_CYCLES_ANY Cycles Decode Stream Buffer (DSB) is delivering
any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153 0 0
0 0 0 0 0 0 0 0x00
0x79 0x20 IDQ.MS_MITE_UOPS Uops initiated by MITE and delivered to Instruction
Decode Queue (IDQ) while Microcode Sequencer (MS) is busy 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x79 0x24 IDQ.ALL_MITE_CYCLES_4_UOPS Cycles MITE is delivering 4 Uops
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x453
0 0 0 0 0 0 0 0 0 0x00
0x79 0x24 IDQ.ALL_MITE_CYCLES_ANY_UOPS Cycles MITE is delivering any Uop
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153
0 0 0 0 0 0 0 0 0 0x00
0x79 0x30 IDQ.MS_CYCLES Cycles when uops are being delivered to Instruction
Decode Queue (IDQ) while Microcode Sequencer (MS) is busy 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x153 0 0
0 0 0 0 0 0 0 0x00
0x79 0x30 IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or
MITE (legacy decode pipeline) to the Microcode Sequencer 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x157 0 0
0 0 0 0 0 0 0 0x00
0x79 0x30 IDQ.MS_UOPS Uops delivered to Instruction Decode Queue (IDQ) while
Microcode Sequencer (MS) is busy 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x80 0x04 ICACHE_16B.IFDATA_STALL Cycles where a code fetch is stalled due to L1
instruction cache miss. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x83 0x01 ICACHE_64B.IFTAG_HIT Instruction fetch tag lookups that hit in the
instruction cache (L1I). Counts at 64-byte cache-line granularity. 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x83 0x02 ICACHE_64B.IFTAG_MISS Instruction fetch tag lookups that miss in the
instruction cache (L1I). Counts at 64-byte cache-line granularity. 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x83 0x04 ICACHE_64B.IFTAG_STALL Cycles where a code fetch is stalled due to L1
instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x83 0x04 ICACHE_TAG.STALLS Cycles where a code fetch is stalled due to L1
instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0x85 0x01 ITLB_MISSES.MISS_CAUSES_A_WALK Misses at all ITLB levels that
cause page walks 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x85 0x02 ITLB_MISSES.WALK_COMPLETED_4K Code miss in all TLB levels causes a page
walk that completes. (4K) 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0
 0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x85 0x04 ITLB_MISSES.WALK_COMPLETED_2M_4M Code miss in all TLB levels causes
a page walk that completes. (2M/4M) 0,1,2,3 0,1,2,3,4,5,6,7 100003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0x85 0x08 ITLB_MISSES.WALK_COMPLETED_1G Code miss in all TLB levels causes a page
walk that completes. (1G) 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0x85 0x0e ITLB_MISSES.WALK_COMPLETED Code miss in all TLB levels causes a page
walk that completes. (All page sizes) 0,1,2,3 0,1,2,3,4,5,6,7 100003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x85 0x10 ITLB_MISSES.WALK_PENDING Counts 1 per cycle for each PMH that is
busy with a page walk for an instruction fetch request. EPT page walk duration are
excluded in Skylake. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x85 0x10 ITLB_MISSES.WALK_ACTIVE Cycles when at least one PMH is busy with a
page walk for code (instruction fetch) request. EPT page walk duration are excluded
in Skylake. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0x00 0 0 5
0x153 0 0 0 0 0 0 0 0 0 0x00
0x85 0x20 ITLB_MISSES.STLB_HIT Instruction fetch requests that miss the ITLB
and hit the STLB. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0x87 0x01 ILD_STALL.LCP Stalls caused by changing prefix length of the
instruction. [This event is alias to DECODE.LCP] 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0x87 0x01 DECODE.LCP Stalls caused by changing prefix length of the instruction.
[This event is alias to ILD_STALL.LCP] 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0x89 0xe4 BR_MISP_EXEC.INDIRECT Speculative mispredicted indirect branches
0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 1 0 0x00
0x89 0xFF BR_MISP_EXEC.ALL_BRANCHES Speculative and retired mispredicted
macro conditional branches 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 1 0
0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CORE Uops not delivered to Resource Allocation
Table (RAT) per thread when backend of the machine is not stalled 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Cycles per thread when 4
or more uops are not delivered to Resource Allocation Table (RAT) when backend of
the machine is not stalled 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x453 0 0 0 0 0 0 0 0 0
0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE Cycles per thread
when 3 or more uops are not delivered to Resource Allocation Table (RAT) when
backend of the machine is not stalled 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x353 0 0 0 0 0 0 0
0 0 0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE Cycles with less
than 2 uops delivered by the front end. 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x253 0 0 0 0 0 0 0
0 0 0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE Cycles with less
than 3 uops delivered by the front end. 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x153 0 0 0 0 0 0 0
0 0 0x00
0x9C 0x01 IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts cycles FE delivered 4
uops or Resource Allocation Table (RAT) was stalling FE. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x1D3 0 0
0 0 0 0 0 0 0 0x00
0xA1 0x01 UOPS_DISPATCHED_PORT.PORT_0 Cycles per thread when uops are executed
in port 0 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x02 UOPS_DISPATCHED_PORT.PORT_1 Cycles per thread when uops are executed
in port 1 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x04 UOPS_DISPATCHED_PORT.PORT_2 Cycles per thread when uops are executed
in port 2 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x08 UOPS_DISPATCHED_PORT.PORT_3 Cycles per thread when uops are executed
in port 3 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x10 UOPS_DISPATCHED_PORT.PORT_4 Cycles per thread when uops are executed
in port 4 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x20 UOPS_DISPATCHED_PORT.PORT_5 Cycles per thread when uops are executed
in port 5 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x40 UOPS_DISPATCHED_PORT.PORT_6 Cycles per thread when uops are executed
in port 6 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xA1 0x80 UOPS_DISPATCHED_PORT.PORT_7 Cycles per thread when uops are executed
in port 7 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xa2 0x01 RESOURCE_STALLS.ANY Resource-related stall cycles 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xA2 0x08 RESOURCE_STALLS.SB Cycles stalled due to no store buffers
available. (not including draining form sync). 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xA3 0x01 CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss demand load is
outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x153 0 0 0 0 0 0 0 0 0 0x00
0xA3 0x02 CYCLE_ACTIVITY.CYCLES_L3_MISS Cycles while L3 cache miss demand load is
outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0x00 0x00 0 0
5 0x253 0 0 0 0 0 0 0 0 0 0x00
0xA3 0x04 CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x453 0 0
0 0 0 0 0 0 0 0x00
0xA3 0x05 CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss
demand load is outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x553 0 0 0 0 0 0 0 0 0
0x00
0xA3 0x06 CYCLE_ACTIVITY.STALLS_L3_MISS Execution stalls while L3 cache miss
demand load is outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0x00 0x00
0 0 5 0x653 0 0 0 0 0 0 0 0 0
0x00
0xA3 0x08 CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand
load is outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x853 0 0 0 0 0 0 0 0 0 0x00
0xA3 0x0C CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache
miss demand load is outstanding. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0xC53 0 0 0 0 0 0 0 0
0 0x00
0xA3 0x10 CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an
outstanding load. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x1053 0 0 0 0 0 0 0 0 0 0x00
0xA3 0x14 CYCLE_ACTIVITY.STALLS_MEM_ANY Execution stalls while memory subsystem
has an outstanding load. 0,1,2,3 0,1,2,3 2000003 0 0 0
0 0 0x1453 0 0 0 0 0 0 0 0 0
0x00
0xA6 0x01 EXE_ACTIVITY.EXE_BOUND_0_PORTS Cycles where no uops were executed,
the Reservation Station was not empty, the Store Buffer was full and there was no
outstanding load. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xA6 0x02 EXE_ACTIVITY.1_PORTS_UTIL Cycles total of 1 uop is executed on all
ports and Reservation Station was not empty. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xA6 0x04 EXE_ACTIVITY.2_PORTS_UTIL Cycles total of 2 uops are executed on
all ports and Reservation Station was not empty. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xA6 0x08 EXE_ACTIVITY.3_PORTS_UTIL Cycles total of 3 uops are executed on
all ports and Reservation Station was not empty. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xA6 0x10 EXE_ACTIVITY.4_PORTS_UTIL Cycles total of 4 uops are executed on
all ports and Reservation Station was not empty. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xA6 0x40 EXE_ACTIVITY.BOUND_ON_STORES Cycles where the Store Buffer was full
and no outstanding load. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xA8 0x01 LSD.UOPS Number of Uops delivered by the LSD. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xA8 0x01 LSD.CYCLES_ACTIVE Cycles Uops delivered by the LSD, but didn't come
from the decoder. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
5 0x153 0 0 0 0 0 0 0 0 0 0x00
0xA8 0x01 LSD.CYCLES_4_UOPS Cycles 4 Uops delivered by the LSD, but didn't come
from the decoder. [This event is alias to LSD.CYCLES_OK] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0x00 0 0 0 0x453 0 0
0 0 0 0 0 0 0 0x00
0xA8 0x01 LSD.CYCLES_OK Cycles 4 Uops delivered by the LSD, but didn't come
from the decoder. [This event is alias to LSD.CYCLES_4_UOPS] 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0x00 0 0 0 0x453 0 0
0 0 0 0 0 0 0 0x00
0xAB 0x01 DSB2MITE_SWITCHES.COUNT Decode Stream Buffer (DSB)-to-MITE switches
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xAB 0x02 DSB2MITE_SWITCHES.PENALTY_CYCLES Decode Stream Buffer (DSB)-to-MITE
switch true penalty cycles. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xAE 0x01 ITLB.ITLB_FLUSH Flushing of the Instruction TLB (ITLB) pages,
includes 4k/2M/4M pages. 0,1,2,3 0,1,2,3,4,5,6,7 100007 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xB0 0x01 OFFCORE_REQUESTS.DEMAND_DATA_RD Demand Data Read requests sent to
uncore 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xB0 0x02 OFFCORE_REQUESTS.DEMAND_CODE_RD Cacheable and non-cacheable code
read requests 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xB0 0x04 OFFCORE_REQUESTS.DEMAND_RFO Demand RFO requests including regular
RFOs, locks, ItoM 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xB0 0x08 OFFCORE_REQUESTS.ALL_DATA_RD Demand and prefetch data reads
0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xB0 0x10 OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Demand Data Read requests who
miss L3 cache 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xB0 0x80 OFFCORE_REQUESTS.ALL_REQUESTS Any memory transaction that reached the
SQ. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xB1 0x01 UOPS_EXECUTED.THREAD Counts the number of uops to be executed per-
thread each cycle. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xB1 0x01 UOPS_EXECUTED.STALL_CYCLES Counts number of cycles no uops were
dispatched to be executed on this thread. 0,1,2,3 0,1,2,3,4,5,6,7 2000003
0 0 0 0 0 0x1D3 0 0 0 0 0 0 0
0 0 0x00
0xB1 0x01 UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC Cycles where at least 1 uop was
executed per-thread 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x153 0 0 0 0 0 0 0 0 0 0x00
0xB1 0x01 UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC Cycles where at least 2 uops were
executed per-thread 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x253 0 0 0 0 0 0 0 0 0 0x00
0xB1 0x01 UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC Cycles where at least 3 uops were
executed per-thread 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x353 0 0 0 0 0 0 0 0 0 0x00
0xB1 0x01 UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC Cycles where at least 4 uops were
executed per-thread 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x453 0 0 0 0 0 0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE Number of uops executed on the core.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE_CYCLES_GE_1 Cycles at least 1 micro-op is
executed from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x153 0 0 0 0 0
0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE_CYCLES_GE_2 Cycles at least 2 micro-op is
executed from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x253 0 0 0 0 0
0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE_CYCLES_GE_3 Cycles at least 3 micro-op is
executed from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x353 0 0 0 0 0
0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE_CYCLES_GE_4 Cycles at least 4 micro-op is
executed from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x453 0 0 0 0 0
0 0 0 0 0x00
0xB1 0x02 UOPS_EXECUTED.CORE_CYCLES_NONE Cycles with no micro-ops executed
from any thread on physical core. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x1D3 0 0 0 0 0 0 0 0
 0 0x00
0xB1 0x10 UOPS_EXECUTED.X87 Counts the number of x87 uops dispatched. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xB2 0x01 OFFCORE_REQUESTS_BUFFER.SQ_FULL Offcore requests buffer cannot take
more entries for this thread core. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xB7, 0xBB 0x01 OFFCORE_RESPONSE Offcore response can be programmed only with a
specific pair of event select and counter MSR, and with specific event codes and
predefine mask bit value in a dedicated MSR to specify attributes of the offcore
transaction 0,1,2,3 0,1,2,3 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 1 0 0 0x00
0xBD 0x01 TLB_FLUSH.DTLB_THREAD DTLB flush attempts of the thread-specific
entries 0,1,2,3 0,1,2,3,4,5,6,7 100007 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xBD 0x20 TLB_FLUSH.STLB_ANY STLB flush attempts 0,1,2,3
0,1,2,3,4,5,6,7 100007 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC0 0x00 INST_RETIRED.ANY_P Number of instructions retired. General Counter
- architectural event 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 5 0x53 0 0 1 0 0 SKL091, SKL044 0 0
0 0x00
0xC0 0x01 INST_RETIRED.PREC_DIST Precise instruction retired event with HW to
reduce effect of PEBS shadow in IP distribution 1 1 2000003 0 0
1 0 5 0x53 0 0 0 0 0 SKL091, SKL044 0
0 0 0x00
0xC0 0x01 INST_RETIRED.TOTAL_CYCLES_PS Number of cycles using always true
condition applied to PEBS instructions retired event. 0,2,3 0,2,3 2000003
0 0 1 0 5 0xAD3 0 0 0 0 0 SKL091,
SKL044 0 0 0 0x00
0xC0 0x02 INST_RETIRED.NOP Number of all retired NOP instructions. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 SKL091, SKL044 0 0 0 0x00
0xc0 0x02 INST_RETIRED.NOP_PS Number of all retired NOP instructions.
0,1,2,3 0,1,2,3 2000003 0 0 1 0 0 0x53 0
0 0 0 0 SKL091, SKL044 0 0 0 0x00
0xC1 0x3F OTHER_ASSISTS.ANY Number of times a microcode assist is invoked by HW
other than FP-assist. Examples include AD (page Access Dirty) and AVX* related
assists. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0x00 0x00 0 0 5
0x53 0 0 0 0 0 0 0 0 0 0x00
0xC2 0x02 UOPS_RETIRED.RETIRE_SLOTS Retirement slots used. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC2 0x02 UOPS_RETIRED.STALL_CYCLES Cycles without actually retired uops.
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x1D3
0 0 0 0 0 0 0 0 0 0x00
0xC2 0x02 UOPS_RETIRED.TOTAL_CYCLES Cycles with less than 10 actually retired
uops. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x10D3
0 0 0 0 0 0 0 0 0 0x00
0xc2 0x04 UOPS_RETIRED.MACRO_FUSED Number of macro-fused uops retired. (non
precise) 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xC3 0x01 MACHINE_CLEARS.COUNT Number of machine clears (nukes) of any type.
0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x157
0 0 0 0 0 0 0 0 0 0x00
0xC3 0x02 MACHINE_CLEARS.MEMORY_ORDERING Counts the number of machine clears
due to memory order conflicts. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0
0 0 0 0 0x53 0 0 0 0 0 SKL089 0
 0 0 0x00
0xC3 0x04 MACHINE_CLEARS.SMC Self-modifying code (SMC) detected. 0,1,2,3
0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC4 0x00 BR_INST_RETIRED.ALL_BRANCHES All (macro) branch instructions retired.
0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x01 BR_INST_RETIRED.CONDITIONAL Conditional branch instructions retired.
[This event is alias to BR_INST_RETIRED.COND] 0,1,2,3 0,1,2,3,4,5,6,7 400009
0 0 0 0 0 0x53 0 0 0 0 0 SKL091
0 1 0 0x00
0xC4 0x01 BR_INST_RETIRED.CONDITIONAL_PS Conditional branch instructions
retired. [This event is alias to BR_INST_RETIRED.COND_PS] 0,1,2,3 0,1,2,3
400009 0 0 1 0 0 0x53 0 0 0 0 0
SKL091 0 1 0 0x00
0xC4 0x01 BR_INST_RETIRED.COND Conditional branch instructions retired. [This
event is alias to BR_INST_RETIRED.CONDITIONAL] 0,1,2,3 0,1,2,3,4,5,6,7 400009
0 0 0 0 0 0x53 0 0 0 0 0 SKL091
0 1 0 0x00
0xC4 0x01 BR_INST_RETIRED.COND_PS Conditional branch instructions retired. [This
event is alias to BR_INST_RETIRED.CONDITIONAL_PS] 0,1,2,3 0,1,2,3 400009
0 0 1 0 0 0x53 0 0 0 0 0 SKL091
0 1 0 0x00
0xC4 0x02 BR_INST_RETIRED.NEAR_CALL Direct and indirect near call
instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7 100007 0 0 0
0 0 0x53 0 0 0 0 0 SKL091 0 1 0
0x00
0xC4 0x02 BR_INST_RETIRED.NEAR_CALL_PS Direct and indirect near call
instructions retired. 0,1,2,3 0,1,2,3 100007 0 0 1 0
0 0x53 0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x04 BR_INST_RETIRED.ALL_BRANCHES_PS All (macro) branch instructions
retired. 0,1,2,3 0,1,2,3 400009 0 0 1 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x08 BR_INST_RETIRED.NEAR_RETURN Return instructions retired. 0,1,2,3
0,1,2,3,4,5,6,7 100007 0 0 0 0 0 0x53 0 0
0 0 0 SKL091 0 1 0 0x00
0xC4 0x08 BR_INST_RETIRED.NEAR_RETURN_PS Return instructions retired.
0,1,2,3 0,1,2,3 100007 0 0 1 0 0 0x53 0
0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x10 BR_INST_RETIRED.NOT_TAKEN Not taken branch instructions retired.
0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xc4 0x10 BR_INST_RETIRED.COND_NTAKEN Not taken branch instructions retired.
0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x20 BR_INST_RETIRED.NEAR_TAKEN Taken branch instructions retired.
0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x20 BR_INST_RETIRED.NEAR_TAKEN_PS Taken branch instructions retired.
0,1,2,3 0,1,2,3 400009 0 0 1 0 0 0x53 0
0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x40 BR_INST_RETIRED.FAR_BRANCH Far branch instructions retired.
0,1,2,3 0,1,2,3,4,5,6,7 100007 0 0 0 0 0 0x53
0 0 0 0 0 SKL091 0 1 0 0x00
0xC4 0x40 BR_INST_RETIRED.FAR_BRANCH_PS Counts the number of far branch
instructions retired. 0,1,2,3 0,1,2,3 100007 0 0 1 0
0 0x53 0 0 0 0 0 SKL091 0 1 0 0x00
0xC5 0x00 BR_MISP_RETIRED.ALL_BRANCHES All mispredicted macro branch
instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0
 0 0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x01 BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional branch
instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0 0
0 0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x01 BR_MISP_RETIRED.CONDITIONAL_PS Mispredicted conditional branch
instructions retired. 0,1,2,3 0,1,2,3 400009 0 0 1 0
0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x02 BR_MISP_RETIRED.NEAR_CALL Mispredicted direct and indirect near
call instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7 400009 0 0
0 0 0 0x53 0 0 0 0 0 0 0 1 0
0x00
0xC5 0x02 BR_MISP_RETIRED.NEAR_CALL_PS Mispredicted direct and indirect near
call instructions retired. 0,1,2,3 0,1,2,3 100007 0 0 1
0 0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x04 BR_MISP_RETIRED.ALL_BRANCHES_PS Mispredicted macro branch
instructions retired. 0,1,2,3 0,1,2,3 400009 0 0 1 0
0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x08 BR_MISP_RETIRED.RET This event counts the number of mispredicted
ret instructions retired. Non PEBS 0,1,2,3 0,1,2,3,4,5,6,7 100007 0
0 0 0 0 0x53 0 0 0 0 0 0 0 1
0 0x00
0xC5 0x08 BR_MISP_RETIRED.RET_PS This event counts the number of mispredicted
ret instructions retired. 0,1,2,3 0,1,2,3 100007 0 0 1
0 0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xC5 0x20 BR_MISP_RETIRED.NEAR_TAKEN Number of near branch instructions
retired that were mispredicted and taken. 0,1,2,3 0,1,2,3,4,5,6,7 400009
0 0 0 0 0 0x53 0 0 0 0 0 0 0
1 0 0x00
0xC5 0x20 BR_MISP_RETIRED.NEAR_TAKEN_PS Number of near branch instructions
retired that were mispredicted and taken. 0,1,2,3 0,1,2,3 100007 0
0 1 0 0 0x53 0 0 0 0 0 0 0 1
0 0x00
0xC6 0x01 FRONTEND_RETIRED.DSB_MISS Retired Instructions who experienced a
critical DSB miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x11 0 1
0 0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.L1I_MISS Retired Instructions who experienced
Instruction L1 Cache true miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x12
0 1 0 0x53 0 0 0 0 0 0 0 0 1
0x00
0xC6 0x01 FRONTEND_RETIRED.L2_MISS Retired Instructions who experienced
Instruction L2 Cache true miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x13
0 1 0 0x53 0 0 0 0 0 0 0 0 1
0x00
0xC6 0x01 FRONTEND_RETIRED.ITLB_MISS Retired Instructions who experienced iTLB
true miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x14 0 1 0 0x53
0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.STLB_MISS Retired Instructions who experienced STLB
(2nd level TLB) true miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x15 0
1 0 0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2 Retired instructions that are fetched
after an interval where the front-end delivered no uops for a period of 2 cycles
which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x400206 0 1 0 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2 Retired instructions
that are fetched after an interval where the front-end had at least 2 bubble-slots
for a period of 2 cycles which was not interrupted by a back-end stall.
0,1,2,3 0,1,2,3 100007 0x3F7 0x200206 0 1 0 0x53
0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_4 Retired instructions that are fetched
after an interval where the front-end delivered no uops for a period of 4 cycles
which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x400406 0 1 0 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.DSB_MISS_PS Retired Instructions who experienced a
critical DSB miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x11 1 1
0 0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.L1I_MISS_PS Retired Instructions who experienced
Instruction L1 Cache true miss. Precise Event. 0,1,2,3 0,1,2,3 100007
0x3F7 0x12 1 1 0 0x53 0 0 0 0 0 0 0
0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.L2_MISS_PS Retired Instructions who experienced
Instruction L2 Cache true miss. Precise Event. 0,1,2,3 0,1,2,3 100007
0x3F7 0x13 1 1 0 0x53 0 0 0 0 0 0 0
0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.ITLB_MISS_PS Retired Instructions who experienced iTLB
true miss. Precise Event. 0,1,2,3 0,1,2,3 100007 0x3F7 0x14 1
1 0 0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.STLB_MISS_PS Retired Instructions who experienced STLB
(2nd level TLB) true miss. Precise Event. 0,1,2,3 0,1,2,3 100007 0x3F7
0x15 1 1 0 0x53 0 0 0 0 0 0 0 0
1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 2
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x400206 1 1 0 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2_PS Retired instructions
that are fetched after an interval where the front-end had at least 2 bubble-slots
for a period of 2 cycles which was not interrupted by a back-end stall. Precise
Event. 0,1,2,3 0,1,2,3 100007 0x3F7 0x200206 1 1 0
0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_4_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 4
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x400406 1 1 0 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_8 Retired instructions that are fetched
after an interval where the front-end delivered no uops for a period of 8 cycles
which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x400806 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_16 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 16
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x401006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_32 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 32
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x402006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_64 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 64
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x404006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_128 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 128
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x408006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_256 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 256
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x410006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_512 Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 512
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x420006 0 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 Retired instructions
that are fetched after an interval where the front-end had at least 1 bubble-slot
for a period of 2 cycles which was not interrupted by a back-end stall.
0,1,2,3 0,1,2,3 100007 0x3F7 0x100206 0 1 5 0x53
0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS Retired instructions
that are fetched after an interval where the front-end had at least 1 bubble-slot
for a period of 2 cycles which was not interrupted by a back-end stall. Precise
Event. 0,1,2,3 0,1,2,3 100007 0x3F7 0x100206 1 1 5
0x53 0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3 Retired instructions
that are fetched after an interval where the front-end had at least 3 bubble-slots
for a period of 2 cycles which was not interrupted by a back-end stall.
0,1,2,3 0,1,2,3 100007 0x3F7 0x300206 0 1 5 0x53
0 0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_8_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 8
cycles which was not interrupted by a back-end stall. 0,1,2,3 0,1,2,3 100007
0x3F7 0x400806 1 1 5 0x53 0 0 0 0 0 0
0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_16_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 16
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x401006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_32_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 32
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x402006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_64_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 64
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x404006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_128_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 128
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x408006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_256_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 256
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x410006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_512_PS Retired instructions that are
fetched after an interval where the front-end delivered no uops for a period of 512
cycles which was not interrupted by a back-end stall. Precise Event. 0,1,2,3
0,1,2,3 100007 0x3F7 0x420006 1 1 5 0x53 0 0
0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3_PS Retired instructions
that are fetched after an interval where the front-end had at least 3 bubble-slots
for a period of 2 cycles which was not interrupted by a back-end stall. Precise
Event. 0,1,2,3 0,1,2,3 100007 0x3F7 0x300206 1 1 5
0x53 0 0 0 0 0 0 0 0 1 0x00
0xc6 0x01 FRONTEND_RETIRED.LATENCY_GE_1 Retired instructions after front-end
starvation of at least 1 cycle 0,1,2,3 0,1,2,3 100007 0x3F7
0x400106 1 1 0 0x53 0 0 0 0 0 0 0
0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.ANY_DSB_MISS Retired Instructions who experienced DSB
miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x1 0 1 0 0x53 0
0 0 0 0 0 0 0 1 0x00
0xC6 0x01 FRONTEND_RETIRED.ANY_DSB_MISS_PS Retired Instructions who
experienced DSB miss. 0,1,2,3 0,1,2,3 100007 0x3F7 0x1 1 1
0 0x53 0 0 0 0 0 0 0 0 1 0x00
0xC7 0x01 FP_ARITH_INST_RETIRED.SCALAR_DOUBLE Counts once for most SIMD scalar
computational double precision floating-point instructions retired. Counts twice
for DPP and FM(N)ADD/SUB instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC7 0x02 FP_ARITH_INST_RETIRED.SCALAR_SINGLE Counts once for most SIMD scalar
computational single precision floating-point instructions retired. Counts twice
for DPP and FM(N)ADD/SUB instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC7 0x03 FP_ARITH_INST_RETIRED.SCALAR Counts once for most SIMD scalar
computational floating-point instructions retired. Counts twice for DPP and
FM(N)ADD/SUB instructions retired. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xC7 0x04 FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE Counts once for most SIMD
128-bit packed computational double precision floating-point instructions retired.
Counts twice for DPP and FM(N)ADD/SUB instructions retired.0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC7 0x08 FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE Counts once for most SIMD
128-bit packed computational single precision floating-point instruction retired.
Counts twice for DPP and FM(N)ADD/SUB instructions retired.0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC7 0x10 FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE Counts once for most SIMD
256-bit packed double computational precision floating-point instructions retired.
Counts twice for DPP and FM(N)ADD/SUB instructions retired.0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC7 0x18 FP_ARITH_INST_RETIRED.4_FLOPS Number of SSE/AVX computational 128-bit
packed single and 256-bit packed double precision FP instructions retired; some
instructions will count twice as noted below. Each count represents 2 or/and 4
computation operations, 1 for each element. Applies to SSE* and AVX* packed single
precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL
DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice
as they perform 2 calculations per element. 0,1,2,3 0,1,2,3,4,5,6,7
1000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC7 0x18 FP_ARITH_INST_RETIRED.8_FLOPS Number of SSE/AVX computational 256-bit
packed single precision and 512-bit packed double precision FP instructions
retired; some instructions will count twice as noted below. Each count represents
8 computation operations, 1 for each element. Applies to SSE* and AVX* packed
single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL
DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB
count twice as they perform 2 calculations per element. 0,1,2,3
0,1,2,3,4,5,6,7 1000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC7 0x20 FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE Counts once for most SIMD
256-bit packed single computational precision floating-point instructions retired.
Counts twice for DPP and FM(N)ADD/SUB instructions retired.0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC7 0x40 FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE Counts number of SSE/AVX
computational 512-bit packed double precision floating-point instructions retired;
some instructions will count twice as noted below. Each count represents 8
computation operations, one for each element. Applies to SSE* and AVX* packed
double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14
RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2
calculations per element. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xC7 0x80 FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE Counts number of SSE/AVX
computational 512-bit packed single precision floating-point instructions retired;
some instructions will count twice as noted below. Each count represents 16
computation operations, one for each element. Applies to SSE* and AVX* packed
single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14
RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2
calculations per element. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xC7 0xFC FP_ARITH_INST_RETIRED.VECTOR Number of any Vector retired FP
arithmetic instructions 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xC8 0x01 HLE_RETIRED.START Number of times an HLE execution started. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC8 0x02 HLE_RETIRED.COMMIT Number of times an HLE execution successfully
committed 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xC8 0x04 HLE_RETIRED.ABORTED Number of times an HLE execution aborted due to
any reasons (multiple categories may count as one). 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC8 0x04 HLE_RETIRED.ABORTED_PS Number of times an HLE execution aborted due to
any reasons (multiple categories may count as one). 0,1,2,3 0,1,2,3
2000003 0 0 1 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC8 0x08 HLE_RETIRED.ABORTED_MEM Number of times an HLE execution aborted due to
various memory events (e.g., read/write capacity and conflicts). 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC8 0x10 HLE_RETIRED.ABORTED_TIMER Number of times an HLE execution aborted
due to hardware timer expiration. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xC8 0x20 HLE_RETIRED.ABORTED_UNFRIENDLY Number of times an HLE execution
aborted due to HLE-unfriendly instructions and certain unfriendly events (such as
AD assists etc.). 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xC8 0x40 HLE_RETIRED.ABORTED_MEMTYPE Number of times an HLE execution aborted
due to incompatible memory type 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xC8 0x80 HLE_RETIRED.ABORTED_EVENTS Number of times an HLE execution aborted
due to unfriendly events (such as interrupts). 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC9 0x01 RTM_RETIRED.START Number of times an RTM execution started. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC9 0x02 RTM_RETIRED.COMMIT Number of times an RTM execution successfully
committed 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xC9 0x04 RTM_RETIRED.ABORTED Number of times an RTM execution aborted due to
any reasons (multiple categories may count as one). 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 1 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC9 0x04 RTM_RETIRED.ABORTED_PS Number of times an RTM execution aborted due to
any reasons (multiple categories may count as one). 0,1,2,3 0,1,2,3
2000003 0 0 1 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC9 0x08 RTM_RETIRED.ABORTED_MEM Number of times an RTM execution aborted due to
various memory events (e.g. read/write capacity and conflicts) 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xC9 0x10 RTM_RETIRED.ABORTED_TIMER Number of times an RTM execution aborted
due to uncommon conditions. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0
0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xC9 0x20 RTM_RETIRED.ABORTED_UNFRIENDLY Number of times an RTM execution
aborted due to HLE-unfriendly instructions 0,1,2,3 0,1,2,3,4,5,6,7
2000003 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xC9 0x40 RTM_RETIRED.ABORTED_MEMTYPE Number of times an RTM execution aborted
due to incompatible memory type 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xC9 0x80 RTM_RETIRED.ABORTED_EVENTS Number of times an RTM execution aborted
due to none of the previous 4 categories (e.g. interrupt) 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xCA 0x1E FP_ASSIST.ANY Cycles with any input/output SSE or FP assist
0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x153
0 0 0 0 0 0 0 0 0 0x00
0xCB 0x01 HW_INTERRUPTS.RECEIVED Number of hardware interrupts received by the
processor. 0,1,2,3 0,1,2,3,4,5,6,7 203 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xCC 0x20 ROB_MISC_EVENTS.LBR_INSERTS Increments whenever there is an update to
the LBR array. 0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 1 0 0x00
0xCC 0x40 ROB_MISC_EVENTS.PAUSE_INST Number of retired PAUSE instructions
(that do not end up with a VMExit to the VMM; TSX aborted Instructions may be
counted). This event is not supported on first SKL and KBL products. 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Counts randomly selected loads when
the latency from first dispatch to completion is greater than 4 cycles.
0,1,2,3 0,1,2,3 100003 0x3F6 0x4 1 1 0 0x53 1
0 0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Counts randomly selected loads when
the latency from first dispatch to completion is greater than 8 cycles.
0,1,2,3 0,1,2,3 50021 0x3F6 0x8 1 1 0 0x53 1 0
0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 16 cycles.
0,1,2,3 0,1,2,3 20011 0x3F6 0x10 1 1 0 0x53 1 0
0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 32 cycles.
0,1,2,3 0,1,2,3 100007 0x3F6 0x20 1 1 0 0x53 1
0 0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 64 cycles.
0,1,2,3 0,1,2,3 2003 0x3F6 0x40 1 1 0 0x53 1 0
0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 128
cycles. 0,1,2,3 0,1,2,3 1009 0x3F6 0x80 1 1 0 0x53 1
0 0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 256
cycles. 0,1,2,3 0,1,2,3 503 0x3F6 0x100 1 1 0 0x53 1
0 0 1 0 0 0 0 0 0x00
0xcd 0x01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Counts randomly selected
loads when the latency from first dispatch to completion is greater than 512
cycles. 0,1,2,3 0,1,2,3 101 0x3F6 0x200 1 1 0 0x53 1
0 0 1 0 0 0 0 0 0x00
0xD0 0x11 MEM_INST_RETIRED.STLB_MISS_LOADS Retired load instructions that miss
the STLB. 0,1,2,3 0,1,2,3 100003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xD0 0x11 MEM_INST_RETIRED.STLB_MISS_LOADS_PS Retired load instructions that miss
the STLB. (Precise Event) 0,1,2,3 0,1,2,3 100003 0 0 1
0 0 0x53 0 0 0 1 0 0 0 0 0 0x00
0xD0 0x12 MEM_INST_RETIRED.STLB_MISS_STORES Retired store instructions that
miss the STLB. 0,1,2,3 0,1,2,3 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD0 0x12 MEM_INST_RETIRED.STLB_MISS_STORES_PS Retired store instructions
that miss the STLB. (Precise Event) 0,1,2,3 0,1,2,3 100003 0 0
1 0 0 0x53 0 0 0 1 1 0 0 0 0
0x00
0xD0 0x21 MEM_INST_RETIRED.LOCK_LOADS Retired load instructions with locked
access. 0,1,2,3 0,1,2,3 100007 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xD0 0x21 MEM_INST_RETIRED.LOCK_LOADS_PS Retired load instructions with
locked access. (Precise Event) 0,1,2,3 0,1,2,3 100007 0 0
1 0 0 0x53 0 0 0 1 0 0 0 0 0
0x00
0xD0 0x41 MEM_INST_RETIRED.SPLIT_LOADS Retired load instructions that split
across a cacheline boundary. 0,1,2,3 0,1,2,3 100003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xD0 0x41 MEM_INST_RETIRED.SPLIT_LOADS_PS Retired load instructions that
split across a cacheline boundary. (Precise Event) 0,1,2,3 0,1,2,3 100003
0 0 1 0 0 0x53 0 0 0 1 0 0 0
0 0 0x00
0xD0 0x42 MEM_INST_RETIRED.SPLIT_STORES Retired store instructions that split
across a cacheline boundary. 0,1,2,3 0,1,2,3 100003 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xD0 0x42 MEM_INST_RETIRED.SPLIT_STORES_PS Retired store instructions that
split across a cacheline boundary. (Precise Event) 0,1,2,3 0,1,2,3 100003
0 0 1 0 0 0x53 0 0 0 1 1 0 0
0 0 0x00
0xD0 0x81 MEM_INST_RETIRED.ALL_LOADS Retired load instructions. 0,1,2,3
0,1,2,3 2000003 0 0 0 0 0 0x53 0 0 0
0 0 0 0 0 0 0x00
0xD0 0x81 MEM_INST_RETIRED.ALL_LOADS_PS Retired load instructions. (Precise
Event) 0,1,2,3 0,1,2,3 2000003 0 0 1 0 0 0x53
0 0 0 1 0 0 0 0 0 0x00
0xD0 0x82 MEM_INST_RETIRED.ALL_STORES Retired store instructions. 0,1,2,3
0,1,2,3 2000003 0 0 0 0 0 0x53 0 0 0
0 0 0 0 0 0 0x00
0xD0 0x82 MEM_INST_RETIRED.ALL_STORES_PS Retired store instructions.
(Precise Event) 0,1,2,3 0,1,2,3 2000003 0 0 1 0 0
0x53 0 0 0 1 1 0 0 0 0 0x00
0xD0 0x83 MEM_INST_RETIRED.ANY All retired memory instructions. 0,1,2,3
0,1,2,3 2000003 0 0 0 0 0 0x53 0 0 0
0 0 0 0 0 0 0x00
0xD0 0x83 MEM_INST_RETIRED.ANY_PS All retired memory instructions. 0,1,2,3
0,1,2,3 2000003 0 0 1 0 0 0x53 0 0 0
1 1 0 0 0 0 0x00
0xD1 0x01 MEM_LOAD_RETIRED.L1_HIT Retired load instructions with L1 cache hits as
data sources 0,1,2,3 0,1,2,3 2000003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD1 0x01 MEM_LOAD_RETIRED.L1_HIT_PS Retired load instructions with L1 cache
hits as data sources 0,1,2,3 0,1,2,3 2000003 0 0 1 0
0 0x53 0 0 0 1 0 0 0 0 0 0x00
0xD1 0x02 MEM_LOAD_RETIRED.L2_HIT Retired load instructions with L2 cache hits as
data sources 0,1,2,3 0,1,2,3 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD1 0x02 MEM_LOAD_RETIRED.L2_HIT_PS Retired load instructions with L2 cache
hits as data sources 0,1,2,3 0,1,2,3 100003 0 0 1 0
0 0x53 0 0 0 1 0 0 0 0 0 0x00
0xD1 0x04 MEM_LOAD_RETIRED.L3_HIT Retired load instructions with L3 cache hits as
data sources 0,1,2,3 0,1,2,3 50021 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xD1 0x04 MEM_LOAD_RETIRED.L3_HIT_PS Retired load instructions with L3 cache
hits as data sources 0,1,2,3 0,1,2,3 50021 0 0 1 0 0
0x53 0 0 0 1 0 0 0 0 0 0x00
0xD1 0x08 MEM_LOAD_RETIRED.L1_MISS Retired load instructions missed L1 cache
as data sources 0,1,2,3 0,1,2,3 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD1 0x08 MEM_LOAD_RETIRED.L1_MISS_PS Retired load instructions missed L1 cache
as data sources 0,1,2,3 0,1,2,3 100003 0 0 1 0 0
0x53 0 0 0 1 0 0 0 0 0 0x00
0xD1 0x10 MEM_LOAD_RETIRED.L2_MISS Retired load instructions missed L2 cache
as data sources 0,1,2,3 0,1,2,3 50021 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xD1 0x10 MEM_LOAD_RETIRED.L2_MISS_PS Retired load instructions missed L2 cache
as data sources 0,1,2,3 0,1,2,3 50021 0 0 1 0 0 0x53
0 0 0 1 0 0 0 0 0 0x00
0xD1 0x20 MEM_LOAD_RETIRED.L3_MISS Retired load instructions missed L3 cache
as data sources 0,1,2,3 0,1,2,3 100007 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD1 0x20 MEM_LOAD_RETIRED.L3_MISS_PS Retired load instructions missed L3 cache
as data sources 0,1,2,3 0,1,2,3 100007 0 0 1 0 0
 0x53 0 0 0 1 0 0 0 0 0 0x00
0xD1 0x40 MEM_LOAD_RETIRED.FB_HIT Retired load instructions which data sources
were load missed L1 but hit FB due to preceding miss to the same cache line with
data not ready 0,1,2,3 0,1,2,3 100007 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xD1 0x40 MEM_LOAD_RETIRED.FB_HIT_PS Retired load instructions which data
sources were load missed L1 but hit FB due to preceding miss to the same cache line
with data not ready 0,1,2,3 0,1,2,3 100003 0 0 1 0
0 0x53 0 0 0 1 0 0 0 0 0 0x00
0xD2 0x01 MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS Retired load instructions which
data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
0,1,2,3 0,1,2,3 20011 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xD2 0x01 MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS Retired load instructions
which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
0,1,2,3 0,1,2,3 20011 0 0 1 0 0 0x53 0 0
0 1 0 0 0 0 0 0x00
0xD2 0x02 MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT Retired load instructions which
data sources were L3 and cross-core snoop hits in on-pkg core cache 0,1,2,3
0,1,2,3 20011 0 0 0 0 0 0x53 0 0 0 0
0 0 0 0 0 0x00
0xD2 0x02 MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS Retired load instructions which
data sources were L3 and cross-core snoop hits in on-pkg core cache 0,1,2,3
0,1,2,3 20011 0 0 1 0 0 0x53 0 0 0 1
0 0 0 0 0 0x00
0xD2 0x04 MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM Retired load instructions which
data sources were HitM responses from shared L3 0,1,2,3 0,1,2,3 20011 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x00
0xD2 0x04 MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS Retired load instructions
which data sources were HitM responses from shared L3 0,1,2,3 0,1,2,3 20011
0 0 1 0 0 0x53 0 0 0 1 0 0 0
0 0 0x00
0xD2 0x08 MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE Retired load instructions which
data sources were hits in L3 without snoops required 0,1,2,3 0,1,2,3 100003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0xD2 0x08 MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE_PS Retired load instructions
which data sources were hits in L3 without snoops required 0,1,2,3 0,1,2,3
100003 0 0 1 0 0 0x53 0 0 0 1 0
0 0 0 0 0x00
0xD3 0x01 MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM Retired load instructions which
data sources missed L3 but serviced from local dram 0,1,2,3 0,1,2,3 100007
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0xD3 0x01 MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS Retired load instructions
which data sources missed L3 but serviced from local dram 0,1,2,3 0,1,2,3
100007 0 0 1 0 0 0x53 0 0 0 1 0
0 0 0 0 0x00
0xD3 0x02 MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Retired load instructions
which data sources missed L3 but serviced from remote dram 0,1,2,3 0,1,2,3
100007 0 0 0 0 0 0x53 0 0 0 0 0
0 0 0 0 0x00
0xD3 0x02 MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS Retired load instructions
which data sources missed L3 but serviced from remote dram 0,1,2,3 0,1,2,3
100007 0 0 1 0 0 0x53 0 0 0 1 0
0 0 0 0 0x00
0xD3 0x04 MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Retired load instructions
whose data sources was remote HITM 0,1,2,3 0,1,2,3 100007 0 0
 0 0 0 0x53 0 0 0 0 0 0 0 0 0
0x00
0xD3 0x04 MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS Retired load instructions
whose data sources was remote HITM 0,1,2,3 0,1,2,3 100007 0 0
1 0 0 0x53 0 0 0 1 0 0 0 0 0
0x00
0xD3 0x08 MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD Retired load instructions whose
data sources was forwarded from a remote cache 0,1,2,3 0,1,2,3 100007
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0xD3 0x08 MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS Retired load instructions
whose data sources was forwarded from a remote cache 0,1,2,3 0,1,2,3 100007
0 0 1 0 0 0x53 0 0 0 1 0 0 0
0 0 0x00
0xD4 0x04 MEM_LOAD_MISC_RETIRED.UC Retired instructions with at least 1
uncacheable load or lock. 0,1,2,3 0,1,2,3 100007 0 0 0
0 0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xD4 0x04 MEM_LOAD_MISC_RETIRED.UC_PS Retired instructions with at least 1
uncacheable load or lock. 0,1,2,3 0,1,2,3 100007 0 0 1
0 0 0x53 0 0 0 1 0 0 0 0 0 0x00
0xE6 0x01 BACLEARS.ANY Counts the total number when the front end is
resteered, mainly when the BPU cannot provide a correct prediction and this is
corrected by other branch handling mechanisms at the front end. 0,1,2,3
0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xEF 0x01 CORE_SNOOP_RESPONSE.RSP_IHITI CORE_SNOOP_RESPONSE.RSP_IHITI 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xEF 0x02 CORE_SNOOP_RESPONSE.RSP_IHITFSE CORE_SNOOP_RESPONSE.RSP_IHITFSE
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xEF 0x04 CORE_SNOOP_RESPONSE.RSP_SHITFSE CORE_SNOOP_RESPONSE.RSP_SHITFSE
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xEF 0x08 CORE_SNOOP_RESPONSE.RSP_SFWDM CORE_SNOOP_RESPONSE.RSP_SFWDM 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xEF 0x10 CORE_SNOOP_RESPONSE.RSP_IFWDM CORE_SNOOP_RESPONSE.RSP_IFWDM 0,1,2,3
0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xEF 0x20 CORE_SNOOP_RESPONSE.RSP_IFWDFE CORE_SNOOP_RESPONSE.RSP_IFWDFE
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xEF 0x40 CORE_SNOOP_RESPONSE.RSP_SFWDFE CORE_SNOOP_RESPONSE.RSP_SFWDFE
0,1,2,3 0,1,2,3,4,5,6,7 2000003 0 0 0 0 0 0x53
0 0 0 0 0 0 0 0 0 0x00
0xF0 0x40 L2_TRANS.L2_WB L2 writebacks that access L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xF1 0x1F L2_LINES_IN.ALL L2 cache lines filling L2 0,1,2,3
0,1,2,3,4,5,6,7 100003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xF2 0x01 L2_LINES_OUT.SILENT Counts the number of lines that are silently
dropped by L2 cache when triggered by an L2 cache fill. These lines are typically
in Shared state. A non-threaded event. 0,1,2,3 0,1,2,3,4,5,6,7 200003
0 0 0 0 0 0x53 0 0 0 0 0 0 0
0 0 0x00
0xF2 0x02 L2_LINES_OUT.NON_SILENT Counts the number of lines that are evicted by
L2 cache when triggered by an L2 cache fill. Those lines can be either in modified
state or clean state. Modified lines may either be written back to L3 or directly
written to memory and not allocated in L3. Clean lines may either be allocated in
L3 or dropped 0,1,2,3 0,1,2,3,4,5,6,7 200003 0 0 0 0
0 0x53 0 0 0 0 0 0 0 0 0 0x00
0xF2 0x04 L2_LINES_OUT.USELESS_PREF This event is deprecated. Refer to new
event L2_LINES_OUT.USELESS_HWPF 0,1,2,3 0,1,2,3,4,5,6,7 200003 0
0 0 0 0 0x53 0 0 0 0 0 0 0 0
0 0x01
0xF2 0x04 L2_LINES_OUT.USELESS_HWPF Counts the number of lines that have been
hardware prefetched but not used and now evicted by L2 cache 0,1,2,3
0,1,2,3,4,5,6,7 200003 0 0 0 0 0 0x53 0 0
0 0 0 0 0 0 0 0x00
0xF4 0x10 SQ_MISC.SPLIT_LOCK Number of cache line split locks sent to
uncore. 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xFE 0x02 IDI_MISC.WB_UPGRADE Counts number of cache lines that are allocated
and written back to L3 with the intention that they are more likely to be reused
shortly 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00
0xFE 0x04 IDI_MISC.WB_DOWNGRADE Counts number of cache lines that are dropped
and not written back to L3 as they are deemed to be less likely to be reused
shortly 0,1,2,3 0,1,2,3,4,5,6,7 100003 0 0 0 0 0
0x53 0 0 0 0 0 0 0 0 0 0x00