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uart_design_verilog

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Sneha Sneha
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7 views

uart_design_verilog

Uploaded by

Sneha Sneha
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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//uart transmitter

module uart_tx #(parameter clks_per_bit=217)


(input i_clock,
input i_TX_DV,
input [7:0] i_TX_byte,
output o_TX_active,
output reg o_TX_serial,
output o_TX_done );

parameter IDLE = 3'b000;


parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [2:0] main = 0;


reg [7:0] r_clock_count = 0;
reg [2:0] r_bit_index = 0;
reg [7:0] r_TX_data = 0;
reg r_TX_done = 0;
reg r_TX_active = 0;

always@(posedge i_clock)
begin
case(main)
IDLE:
begin
o_TX_serial <= 1'b1;
r_TX_done <= 1'b0;
r_clock_count <= 0;
r_bit_index <= 0;

if(i_TX_DV == 1'b1)
begin
r_TX_active <= 1'b1;
r_TX_data <= i_TX_byte;
main <= TX_START_BIT;
end
else
main <= IDLE;
end

TX_START_BIT:
begin
o_TX_serial <= 1'b0;

if (r_clock_count < clks_per_bit-1)


begin
r_clock_count <= r_clock_count+1;
main <= TX_START_BIT;
end
else
begin
r_clock_count <= 0;
main <= TX_DATA_BITS;
end
end

TX_DATA_BITS :
begin
o_TX_serial <= r_TX_data[r_bit_index];

if (r_clock_count < clks_per_bit-1)


begin
r_clock_count <= r_clock_count+1;
main <= TX_DATA_BITS;
end
else
begin
r_clock_count <= 0;

if (r_bit_index < 7)
begin
r_bit_index <= r_bit_index+1;
main <= TX_DATA_BITS;
end
else
begin
r_bit_index <= 0;
main <= TX_STOP_BIT;
end
end
end

TX_STOP_BIT :
begin
o_TX_serial <= 1'b1;

if (r_clock_count < clks_per_bit-1)


begin
r_clock_count <= r_clock_count+1;
main <= TX_STOP_BIT;
end
else
begin
r_TX_done <= 1'b1;
r_clock_count <= 0;
main <= CLEANUP;
r_TX_active <= 1'b0;
end
end

CLEANUP :
begin
r_TX_done <= 1'b1;
main <= IDLE;
end

default :
main <= IDLE;

endcase
end

assign o_TX_active = r_TX_active;


assign o_TX_done = r_TX_done;

endmodule
//uart receiver
module uart_rx #(parameter clks_per_bit=217)
(input i_clock,
input i_RX_serial,
output o_RX_DV,
output [7:0] o_RX_byte);

parameter IDLE = 3'b000;


parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [7:0] r_clock_count = 0;


reg [2:0] r_bit_index = 0;
reg [7:0] r_RX_byte = 0;
reg r_RX_DV = 0;
reg [2:0] main = 0;

always@(posedge i_clock)
begin

case(main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_clock_count <= 0;
r_bit_index <= 0;

if(i_RX_serial == 1'b0) //start bit detection


main <= RX_START_BIT;
else
main <= IDLE;
end

RX_START_BIT :
begin
if(r_clock_count == (clks_per_bit-1)/2) //to check middile of start
bit
begin
if(i_RX_serial == 1'b0)
begin
r_clock_count <= 0; // reset counter, found the middle
main <= RX_DATA_BITS;
end
else
main <= IDLE;
end
else
begin
r_clock_count <=r_clock_count+1;
main <= RX_START_BIT;
end
end

RX_DATA_BITS :
begin
if (r_clock_count < clks_per_bit-1)
begin
r_clock_count <= r_clock_count+1;
main <= RX_DATA_BITS;
end
else
begin
r_clock_count <= 0;
r_RX_byte[r_bit_index] <=i_RX_serial;

if (r_bit_index < 7) //to check if we have received all 8bits


begin
r_bit_index <= r_bit_index+1;
main <= RX_DATA_BITS;
end
else
begin
r_bit_index <= 0;
main <= RX_STOP_BIT;
end
end
end

RX_STOP_BIT :
begin
if(r_clock_count < clks_per_bit-1) // wait clks_per_bit-1 clock
cycles for Stop bit to finish
begin
r_clock_count <= r_clock_count+1;
main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_clock_count <= 0;
main <=CLEANUP;
end
end

CLEANUP :
begin
main <= IDLE;
r_RX_DV <=1'b0;
end

default:main <= IDLE;


endcase
end

assign o_RX_DV=r_RX_DV;
assign o_RX_byte=r_RX_byte;

endmodule

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