Lg 42ly330c-Za Chassis Ld4ca 1403-Rev00
Lg 42ly330c-Za Chassis Ld4ca 1403-Rev00
Lg 42ly330c-Za Chassis Ld4ca 1403-Rev00
LED TV
SERVICE MANUAL
CHASSIS : LD4CA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CONTENTS . ............................................................................................. 2
SPECIFICATION ....................................................................................... 6
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. Carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
Analogue TV
1) PAL-BG Analogue TV : (RF) VHF: E2 to E12, UHF : E21 to E69
2) PAL-DK (CATV) S1 to S20, HYPER: S21 to S47
3) PAL-I/I’
4) SECAM-BG Digital TV : VHF, UHF
5) SECAM-DK
2 Broadcasting system 6) SECAM L/L’ Satellite TV : VHF, UHF,
C-Band, Ku-Band
Digital TV
1) DVB-T/C * DVB-T2 (T2 model only support )
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
: 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
3 Receiving system Digital : COFDM, QAM 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
► DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
4 Scart Jack (1EA) PAL, SECAM Scart 1 Jack is Full scart and support RF-OUT(analog).
Component Phone
5 Component Input(Y/Cb/Cr, Y/Pb/Pr)
Jack (1EA)
7 HDMI Input (2 EA) HDMI1/2-DTV Support HDCP
8 Audio Input (1EA) Component & AV Component & AV’s audio input is used by common port.
9 SDPIF out (1EA) SPDIF out
Antenna, AV1, Component, HDMI1, 32/37/42/47/55/60inch: Rear
10 Earphone out (1EA)
HDMI2 22/28inch: Side
11 USB (1EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD
CI : U
K, Finland, Denmark, Norway, Sweden, Russia, Spain,
DVB-T Ireland, Luxemburg, Belgium, Netherland
CI+ : France(Canal+), Italy(DGTVi)
12 DVB CI : Switzerland, Austria, Slovenia, Hungary, Bulgaria
DVB-C CI+ : S
witzerland(UPC,Cablecom), Netherland(Ziggo),
Germany(KDG,CWB), Finland(labwise)
DVB-S CI + : Germany(Astra HD+ )
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. Video resolutions (2D)
5.1. Component Input (Y, CB/PB, CR/PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1 720*576 15.625 50.00 13.5 SDTV ,DVD 576I
2 720*480 15.73 60.00 13.5135 SDTV ,DVD 480I
3 720*480 15.73 59.94 13.50 SDTV ,DVD 480I
4 720*576 31.25 50.00 27.00 SDTV 576P
5 720*480 31.50 60.00 27.027 SDTV 480P
6 720*480 31.47 59.94 27.00 SDTV 480P
7 1280*720 37.50 50.00 74.25 HDTV 720P
8 1280*720 45.00 60.00 74.25 HDTV 720P
9 1280*720 44.96 59.94 74.176 HDTV 720P
10 1920*1080 28.125 50.00 74.25 HDTV 1080I
11 1920*1080 33.75 60.00 74.25 HDTV 1080I
12 1920*1080 33.72 59.94 74.176 HDTV 1080I
13 1920*1080 56.25 50.00 148.50 HDTV 1080P
14 1920*1080 67.50 60.00 148.50 HDTV 1080P
15 1920*1080 67.432 59.94 148.352 HDTV 1080P
16 1920*1080 27.00 24.00 74.25 HDTV 1080P
17 1920*1080 26.97 23.94 74.176 HDTV 1080P
18 1920*1080 33.75 30.00 74.25 HDTV 1080P
19 1920*1080 33.71 29.97 74.176 HDTV 1080P
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range (4) Click "Connect" tab. If "Can't" is displayed, check connection
between computer, jig, and set.
This specification sheet is applied to all of the LED TV with
LD4CA chassis.
(2) (3)
2. Designation
(1) The adjustment is according to the order which is designated
and which must be followed, according to the plan which
can be changed only on agreeing.
(2) Power adjustment : Free Voltage.
(3) Magnetic Field Condition: Nil.
(4) Input signal Unit: Product Specification Standard.
(5) Reserve after operation : Above 5 Minutes (Heat Run) Please Check the Speed :
Temperature : at 25 °C ± 5 °C To use speed between
Relative humidity : 65 ± 10 % from 200KHz to 400KHz
Input voltage : 220 V, 60 Hz
(6) Adjustment equipments: Color Analyzer(CA-210 or CA-110), (5) Click "Auto" tab and set as below.
DDC Adjustment Jig, Service remote control. (6) Click "Run".
(7) Push the "IN STOP" key - For memory initialization. (7) After downloading, check "OK" message.
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
* After downloading, have to adjust Tool Option again. 3.3. EDID data
(1) Push "IN-START" key in service remote control. (1) RGB
(2) Select "Tool Option 1" and push "OK" key. 1) HD RGB EDID DATA
(3) Punch in the number. (Each model has their number) 0 1 2 3 4 5 6 7 8 9 A B C D E F
(4) Completed selecting Tool option. 00 00 ff ff ff ff ff ff 00 1e 6d a b
10 c 01 03 68 a0 5a 78 0a ee 91 a3 54 4c 99 26
20 0f 50 54 a1 08 00 71 40 61 40 45 40 31 40 01 01
3.1. ADC Process(Optional) 30 01 01 01 01 01 01 1b 21 50 a0 51 00 1e 30 48 88
* If ADC processes as OTP, There is no need to proceed 40 35 00 40 84 00 00 00 1c 01 1d 00 72 51 d0 1e 20
internal ADC. 50 6e 28 55 00 a0 5a 00 00 00 1e 00 00 00 fd 00 3a
- Enter Service Mode by pushing "ADJ" key, 60 3e 1e 53 10 00 0a 20 20 20 20 20 20 d
- Enter Internal ADC mode by pushing "►" key at "9. ADC 70 d 00 e
Calibration". 2) FHD RGB EDID DATA
EZ ADJUST ADC Calibration 0 1 2 3 4 5 6 7 8 9 A B C D E F
0. Tool Option1 ADC Comp 480i NG 00 00 ff ff ff ff ff ff 00 1e 6d a b
1. Tool Option2
ADC Comp 1080p NG
2. Tool Option3
ADC RGB
10 c 01 03 68 10 09 78 0a ee 91 a3 54 4c 99 26
NG
3. Tool Option4
4. Tool Option5 ADC Type OTP 20 0f 50 54 a1 08 00 81 80 61 40 45 40 31 40 01 01
5. Tool Option6
Start Reset 30 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
6. Tool Option Commercial
7. Country Group 40 45 00 a0 5a 00 00 00 1e 01 1d 00 72 51 d0 1e 20
8. Area Option
9.ADC Calibration ►
50 6e 28 55 00 a0 5a 00 00 00 1e 00 00 00 fd 00 3a
10. White Balance 60 3e 1e 53 10 00 0a 20 20 20 20 20 20 d
11. 20 Point WB
12. Test Pattern
70 d 00 e
13 EDID D/L
14. Sub B/C
15. V-Com
16. Ext. Input Adjust
(2) HDMI
17. SPK Lipsync Adjust
18. SPDIF Lipsync Adjust
1) HD HDMI EDID data (2D Model)
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D a B
<Caution> U sing "P-ONLY" key of the Adjustment remote 10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
control, power on TV. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 01 01
30 01 01 01 01 01 01 66 21 50 B0 51 00 1B 30 40 70
* ADC Calibration Protocol (RS232) 40 36 00 40 84 63 00 00 1E 64 19 00 40 41 00 26 30
NO Item CMD 1 CMD 2 Data 0 50 18 88 36 00 40 84 63 00 00 18 00 00 00 FD 00 3A
Enter Adjust Adjust When transfer the ‘Mode In’, 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 D
A A 0 0
MODE ‘Mode In’ Carry the command. 70 d 01 e
ADC Automatically adjustment 80 02 03 22 F1 4E 10 1F 04 93 05 14 03 02 12 20 21
ADC adjust A D 1 0
Adjust (The use of a internal pattern)
90 22 15 01 26 15 07 50 09 57 07 F
A0 80 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A
Adjust Sequence B0 00 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
C0 20 C2 31 00 00 1E 8C 0A D0 8A 20 E0 2D 10 10 3E
▪ aa 00 00 [Enter Adjust Mode]
D0 96 00 A0 5A 00 00 00 18 02 3A 80 18 71 38 2D 40
▪ xb 00 40 [Component Input]
E0 58 2C 45 00 A0 5A 00 00 00 1E 00 00 00 00 00 00
▪ ad 00 10 [Adjust 480i & 1080p Comp]
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e
▪ aa 00 90 End Adjust mode
* Required equipment : Adjustment remote control. 2) FHD HDMI EDID data (2D Model)
0 1 2 3 4 5 6 7 8 9 A B C D E F
3.2. EDID Download 00 00 FF FF FF FF FF FF 00 1E 6D a B
▪ After enter Service Mode by pushing "ADJ" key. 10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
▪ Enter EDID D/L menu. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
▪ Enter "START" by pushing "OK" key. 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
EZ ADJUST EDID D/L 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
0. Tool Option1
HDMI1 NG 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
HDMI2 NG
1. Tool Option2 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 D
2. Tool Option3 Start Reset
3. Tool Option4 70 d 01 e
4. Tool Option5
5. Tool Option6
80 02 03 22 F1 4E 10 9F 04 13 05 14 03 02 12 20 21
6. Tool Option Commercial 90 22 15 01 26 15 07 50 09 57 07 F
7. Country Group
8. Area Option A0 f 01 1D 80 18 71 1C 16 20 58 2C 25 00 20 C2
9.ADC Calibration B0 31 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
10. White Balance
11. 20 Point WB C0 20 C2 31 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C
12. Test Pattern
13.EDID D/L ►
D0 45 00 A0 5A 00 00 00 1E 01 1D 00 BC 52 D0 1E 20
14. Sub B/C E0 B8 28 55 40 C4 8E 21 00 00 1E 00 00 00 00 00 00
15. V-Com
16. Ext. Input Adjust F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e
17. SPK Lipsync Adjust
18. SPDIF Lipsync Adjust
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
0
3) FHD HDMI EDID data (3D model)
1 2 3 4 5 6 7 8 9 A B C D E F
4. Total Assembly line process
00 00 FF FF FF FF FF FF 00 1E 6D a b 4.1. White Balance adjustment
10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 ▪ W/B Equipment condition
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 CA210 : LED -> CH14, Test signal: Inner pattern(80IRE)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C ▪ Above 5 minutes H/run in the inner pattern. (“power on” key
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 of adjust remote control)
50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A ▪ If it is executed W/B adjustment in 2~3 minutes H/run, it is
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d adjusted by Target data.
70 d 01 e * Note : x,y coordinates are drifted about 0.005 after 30 mins
80 02 03 33 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 heat-run. So checking color coordinate within 5-min at total
90 22 15 01 26 15 07 50 09 57 07 f assembly line, consider x,y coordinates might be up to 0.005
A0 80 1E 20 C0 0E 01 40 0A 0F 08 10 18 10 98 10 58
than x,y target of each color temperature
B0 10 38 10 01 1D 80 18 71 1C 16 20 58 2C 25 00 20
C0 C2 31 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55
Mode Temp Coordinate spec
D0 00 20 C2 31 00 00 1E 02 3A 80 18 71 38 2D 40 58 X=0.271 (±0.002)
Cool 13,000 K
E0 2C 45 00 A0 5A 00 00 00 1E 01 1D 00 BC 52 D0 1E Y=0.270 (±0.002)
F0 20 B8 28 55 40 C4 8E 21 00 00 1E 00 00 00 00 e X=0.286 (±0.002)
Medium 9,300 K
Y=0.289 (±0.002)
- Detail EDID Options are below X=0.313 (±0.002)
a. Product ID Warm 6,500 K
Y=0.329 (±0.002)
MODEL NAME HEX EDID Table DDC Function
▪ Normal line(LGD, March ~ December for Gumi, Global)
HD/FHD Model 0001 01 00 Analog/Digital Cool Medium Warm
Aging time
b. Serial No: Controlled on production line. NC5.0 x y x y x y
(Min)
c. Month, Year: 271 270 286 289 313 329
ex) Week : '01' -> '01', Year : '2014' -> '18' fix 1 0-2 282 289 297 308 324 348
d. Model Name(Hex): 2 3-5 281 287 296 306 323 346
cf) TV set’s model name in EDID data is below.
3 6-9 279 284 294 303 321 343
Model name MODEL NAME(HEX)
4 10-19 277 280 292 299 319 339
LG TV 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 (LG TV)
5 20-35 275 277 290 296 317 336
e. Checksum: Changeable by total EDID data. 6 36-49 274 274 289 293 316 333
HD FHD(2D) 7 50-79 273 272 288 291 315 331
EDID C/S data 8 80-119 272 271 287 290 314 330
HDMI RGB HDMI RGB
9 Over 120 271 270 286 289 313 329
Block 0 75 A3 41 5A
Check sum
5B (HDMI1) 25 (HDMI1) ▪ Normal line(LGD, January ~ February for Gumi, Apply not
(Hex) Block 1 - -
4B (HDMI2) 15 (HDMI2) Cinema Screen)
Cool Medium Warm
Aging time
f. Vendor Specific(HDMI) NC5.0 x y x y x y
(Min)
INPUT Model name(HEX)_2D Model name(HEX)_3D 271 270 286 289 313 329
1 0-2 286 295 301 314 328 354
HDMI1 67030C001000801E 78030C001000801E
2 3-5 284 290 299 309 326 349
HDMI2 67030C002000801E 78030C002000801E 3 6-9 282 287 297 306 324 346
4 10-19 279 283 294 302 321 342
5 20-35 276 278 291 297 318 337
6 36-49 274 275 289 294 316 334
3.4. Function Check 7 50-79 273 272 288 291 315 331
- Check display and sound
■ Check Input and Signal items. 8 80-119 272 271 287 290 314 330
1) TV 9 Over 120 271 270 286 289 313 329
2) AV (SCART / CVBS) ▪ Use only AUO/INX/Sharp/CSOT/BOE (Cool temp Spec is
3) COMPONENT (480i) 13000K)
4) HDMI
Aging time Cool Medium Warm
* Display and Sound check is executed by Remote control.
(Min) x y x y x y
<Caution> spec 271 270 286 289 313 329
Not to push the INSTOP key after completion if the function target 278 280 293 299 320 339
inspection.
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
* Connecting picture of the measuring instrument * Manual W/B process using adjust Remote control.
(On Automatic control) ▪ After enter Service Mode by pushing "ADJ" key,
Inside PATTERN is used when W/B is controlled. Connect to ▪ E nter White Balance by pushing " ► " key at "9. White
auto controller or push Adjustment R/C P-ONLY → Enter the Balance".
mode of White-Balance, the pattern will come out. EZ ADJUST
0. Tool Option1
1. Tool Option2
Whit Balance
2. Tool Option3 Color Temp. ◄ Cool ►
3. Tool Option4
R-Gain 172
Full White Pattern CA-210 4. Tool Option5
G-Gain 172
5. Tool Option6
B-Gain 192
6. Tool Option Commercial
COLOR 7. Country Group R-Cut 64
ANALYZER 8. Area Option 64
G-Cut
TYPE : CA-210 9. ADC Calibration B-Cut 64
10. White Balance
Test-Pattern ON
11. 20 Point WB
Backlight 100
12. Test Pattern
13 EDID D/L Reset To Set
RS-232C Communication 14. Sub B/C
15. V-Com
16. Ext. Input Adjust
17. SPK Lipsync Adjust
(1) Adjust in the place where the influx of light like floodlight * CASE Cool Mode
around is blocked. (illumination is less than 10 lux). First adjust the coordinate far away from the target
(2) Adhere closely the Color analyzer(CA210) to the module value(x, y).B.
less than 10 cm distance, keep it with the surface of the 1) x, y > target
Module and Color analyzer's prove vertically.(80° ~ 100°). 2) x, y < target
(3) Aging time 3) x >target, y < target
- After aging start, keep the power on (no suspension of 4) x < target, y > target
power supply) and heat-run over 5 minutes. -E very 4 case have to fit y value by adjusting B Gain
- Using 'no signal' or 'POWER ONLY' or the others, check and then fit x value by adjusting R-Gain.
the back light on. - In this case, increasing/decreasing of B Gain and R
Gain can be adjusted.
▪ Auto adjustment Map(using RS-232C to USB cable)
RS-232C COMMAND How to adjust
[CMD ID DATA] 1) In case G gain more than 172
Wb 00 00 White Balance Start Adjust R Gain and B Gain less than 192
Wb 00 ff White Balance End 2) If the G gain value be adjusted down to 172
RS-232C COMMAND CENTER One of the R/B Gain is 254
[CMD ID DATA] (DEFAULT) 3) If G Gain is 172 , More than one of R/B Gain is to be
MIN MAX
between 192~254
Cool Mid Warm Cool Mid Warm
R Gain jg Ja jd 00 172 192 192 254 * CASE Medium / Warm
G Gain jh Jb je 00 172 192 192 192 First adjust the coordinate far away from the target
B Gain ji Jc jf 00 192 192 172 254 value(x, y).
1) x, y > target
R Cut 64 64 64 128
i) Decrease the R, G.
G Cut 64 64 64 128 2) x, y < target
B Cut 64 64 64 128 i) First decrease the B gain,
ii) Decrease the one of the others.
<Caution> 3) x > target, y < target
Color Temperature : COOL, Medium, Warm. i) First decrease B, so make y a little more than the target.
One of R Gain/G Gain/ B Gain should be kept on 0xC0, and ii) Adjust x value by decreasing the R
adjust other two lower than C0.(When R/G/B Gain are all 4) x < target, y > target
C0, it is the FULL Dynamic Range of Module) i) First decrease B, so make x a little more than the target.
ii) Adjust x value by decreasing the G
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
4.2. 3D function test 4.4. MHL Test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) (1) Turn on TV
* HDMI mode NO. 872 , pattern No.83 (2) Select HDMI2 mode using input Menu.
(1) Please input 3D test pattern like below. (3) Set MHL Zig(M1S0D3617) using MHL input, output and
power cord.
(4) Connect HDMI cable between MHL Zig and HDMI4 port.
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
5. HI-POT Test 6.2. Command Set
5.1. HI-POT auto-check preparation Adjust mode CMD(hex) LENGTH(hex) Description
- Check the POWER cable and SIGNAL cable insertion condition EEPROM WRITE A0h 84h+n n-bytes Write (n = 1~16)
* Description
5.2. HI-POT auto-check FOS Default write : <7mode data> write
(1) Pallet moves in the station. (POWER CORD / AV CORD is Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0,
tightly inserted) Phase
Data write : Model Name and Serial Number write in EEPROM,.
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on.
(4) HI-POT test (Auto) 6.3. Method & notice
- If Test is failed, Buzzer operates. (1) Serial number D/L is using of scan equipment.
- If Test is passed, GOOD Lamp on and move to next proc- (2) S etting of scan equipment operated by Manufacturing
ess automatically. Technology Group.
(3) Serial number D/L must be conformed when it is produced in
production line, because serial number D/L is mandatory by
5.3. Checkpoint D-book 4.0.
(1) Test voltage
- Touchable Metal : 3 KV / min at 100 mA * Manual Download(Model Name and Serial Number)
- SIGNAL : 3KV / min at 100 mA If the TV set is downloaded by OTA or Service man, sometimes
(2) TEST time: 1 second. (case : mass production ) model name or serial number is initialized.(Not always)
(3) TEST POINT There is impossible to download by bar code scan, so It need
- Touchable Metal => LIVE & NEUTRAL : Touchable Metal. Manual download.
- SIGNAL => LIVE & NEUTRAL : SIGNAL. 1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "6.Model Number D/L" like below photo.
3) Input the Factory model name or Serial number like photo.
CMD : A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 +...+ Data_n
Delay : 20ms
Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
7. MAC Address & CI+ key download 7.2. LAN Inspection
7.1 MAC Address 7.2.1. Equipment & Condition
▪ Each other connection to LAN Port of IP Hub and Jig
7.1.1 Equipment & Condition
▪ Play file : Serial.exe
▪ MAC Address edit
▪ Input Start / End MAC address
SET PC
Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
Copyright ©
IC1300
USB SIDE_USB_DM/DP SPI_SCK/SDI/SDO/CS
(JK700)
Serial Flash
USB1_OCP/CTL (8Mbit)
+5V_USB
TPS65282 AVDD5V_MHL,MHL_OCP IC104
SIDE 5V_HDMI_4 I2C_SCL/SDA
System EEPROM
CK+/-, D0+/-, D1+/-, D2+/-,_HDMI4, DDC_SCL/SDA_4, HDMI_CEC (256Kbit)
NAND FLASH
IC102 (1Gbit)
H27U1G8F2CTR -BC
PCM_A[0:7]
TC74LCX244FT
Buffer X- tal
PCM_A[8:14] 24M
CI Slot(P1900)
TS_DATA[0:7]
- 16 -
(IC101) AUD_MASTER_CLK,
IF_N AUD_LRCH, SPK_L
AUD_LRCK, AUD_SCK
TAS5733
AMP_SCL/SDA (IC5600)
SPK_R
CK+/-, D0+/-, D1+/-, D2+/-_HDMI2
HDMI1
BLOCK DIAGRAM
COMP2_L/R_IN
400
900
420
410
121
120
521
310
540
530
501
LV1
820
500
AW1
Set + Stand
A2A10
200
Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
L14 POWER BLOCK (POWER DETECT 2)
Power_DET
+24V +12V +3.5V_POWER_DET +3.5V_ST
OLD_18PIN R435
Q405-*1
D
8.2K 2.7K 0 300
+3.5V_ST 1% 4.7K +12V PANEL_VCC
1% 5% IC401
MMBT3906(NXP) APX803D29 PD_+12V
Q401 PWR ON 1 2 DRV ON R454 G
3.5V PDIM#1 VCC RESET 100 FET_2.5V_DIODE
+3.5V_ST 3 4 3 2 FET_2.5V_NXP
POWER_DET L408 Q405
3.5V 5 6 3.5V
1 3 OPT 1 UBW2012-121F PMV48XP
GND PDIM#2 C415 R431
R412 7 8 C422 120OHM
0.1uF GND
D
R406 33K 1.2K
S
10K 2 24V 9 10 24V 16V POWER_DET_RESET 0.1uF
1%
OPT GND 11 12 GND OPT
R400 R404 C425 R445 C427 R451 R452
10K 12V 13 14 12V 10uF 5.6K 5.6K
4.7K
G
0.1uF 33K
12V 15 16 N.C 25V 16V
GND 17 18 GND +24V +3.5V_POWER_DET OPT
C Q400 R436
R402 R446
RL_ON 10K B MMBT3904(NXP) 100K
OPT 12K
19 OPT
R458 OPT
R427 IC402
R401 R455 27K 0 APX803D29 OPT
10K E R437 R442 C
0 1% 5%
100 10K
VCC 3 2 RESET PANEL_CTL B Q403
R456 OPT MMBT3904(NXP)
0 +3.3V_Normal OPT OPT 1
C413 R428 E
GND R441
0.1uF 5.1K
+3.5V_ST 10K
R419 R420 16V 1%
ZD404 100 1K
+3.5V_POWER_DET 5V NEW_18PIN
P401 C R426
Ready - Dual Power Det
R425
SMAW200-H18S5 10K INV_CTL
L400
B 10K Power Detect activity
CB2012PK501T
+3.5V_ST Use Circuit Designator FET_2.5V_DIODE FET_2.5V_AOS
PWR ON DRV ON
E Q402 Detect Valtage Now is
L401 1 2 MMBT3904(NXP) Q406-*1
C407
10uF
10V
C400
1uF
10V
ZD400
5V
CB2012PK501T 3.5V 3 4 PDIM#1
PWM_DIM
Power Detect +3.5V R432, R454-*1, R438 +3.3V_Normal DMP2130L
Q406-*2
AO3435
D
3.5V 3.5V
S
2012 1005 5 6
GND 7 8 PDMI#2
L402 PWM1
+24V
MLB-201209-0120P-N2 24V 9 10 24V PWM_DIM_PULL_DOWN PWM2_2CH_POWER * Notice Power Detect +12V O R430, R431, R454
OPT +3.5V_ST +3.3V_Normal
- Applying all inch models for LCD L14
G
+24V_CAP GND GND R424 R423
C401 11 12 R467
C432 3.9K 100 - Dual Power Det is used
0.1uF 12V 13 14 12V 1K Power Detect +24V R457, R454
4.7uF for detecting two kinds of voltage FET_2.5V_NXP
50V 50V 12V 15 16 NC
Q406
3216 GND GND L410
L403 17 18 PMV48XP
MLB-201209-0120P-N2 BLM18PG121SN1D
+12V
D
+12V_CAP
C433
4.7uF
C402
0.1uF
19
+1.10V_VDDC C428 C429 C430
G
.
THERMAL
16V 10V 10V 16V
+1.10V_VDDC VIN EN
9
2 7 C
1%
Vout=0.808*(1+R1/R2)
C405 C406
10uF 10uF
16V
[EP]GND
PGND_2
PGND_1
PGOOD
VIN_2
VIN_1
R410
V7V
OPT 100K
C403
100pF +5V_Normal
50V C409 L405
24
23
22
21
20
19
0 . 0 4 7 u F 4.7uH
EN BST 25V
C404
JP4608
JP4609
JP4610
JP4611
R408 4700pF 1 18
4.7K 50V THERMAL
+3.3V_Normal +3.3V_Normal COMP 25 LX_2 R1
MHL_5V_EN 2 17 C411 C412
R421
OPT SS LX_1 18K 82pF 22uF
R459 3 16 1% 50V 16V
MHL_SW_TR MHL_SW_TR OPT OPT 0
R463 R464 Q408 R403 R405 ROSC FB
MHL_SW_TR 4.7K 4.7K 4 IC400 15
2.7K 10K R2
E C EN_SW2 TPS65282REGR SW_IN_2
5 14
Q407 C USB1_CTL
EN_SW1
6
4A 13
SW_IN_1
R422
3.3K
1%
R461
10
11
12
10K B R466
B C410
7
FAULT1
AGND
(Active Low)
SW_OUT2
SW_OUT1
E R465
MHL_SW_TR 10K
MHL_SW_TR R407 R409
10K 10K
Q409 C
R462 R415 5V_HDMI_4 AVDD5V_MHL
10K B 15K
MHL_OCP_EN 5%
MHL_SW_TR
D401 R418
(Active High) E
MHL_SW_TR MBR230LSFT1G 10
30V
OPT C408
R416 10uF
/MHL_OCP_DET
USB1_OCD
100K 10V
Vout=0.8*(1+R1/R2)
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
USB (SIDE)
+5V_USB
JK700
ZD700
C700 C703 C704
SD05
3AU04S-305-ZC-(LG)
OPT
2
SIDE_USB1_DM
R700
0
3
SIDE_USB1_DP
OPT OPT OPT
C701 C702 R701
D700 0
5pF 5pF RCLAMP0502BA
4
50V 50V
5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
HDMI (REAR 1 / SIDE 1 MHL)
HDMI_1 HDMI_2 MHL
VA805
5V_HDMI_2 5V_DET_HDMI_2 5V_HDMI_4 5V_DET_HDMI_4
ESD_HDMI2
R808
HDMI-2
10K R814
HPD4
33
SHIELD ESD_HDMI2
R803 GND VA808
C HDMI-2
20 R809 R815 100
1K 10K 20
Q800 B DDC_SDA_4
MMBT3904(NXP) HPD2
19 19 HP_DET R816 100
DDC_SCL_4
R802 E R810 100 HDMI-2
VA802 DDC_SDA_2 R812
18 1.8K 18 5V
ESD_HDMI1 VA809 VA810
R805
3.3K
R811 100 1.8K
VA800 DDC_SCL_2 R813
17 17 GND HDMI-2 3.3K ESD_HDMI2 ESD_HDMI2
HDMI-2
16 ESD_HDMI1_VARISTOR VA803 VA804 16DDC_DATA
ESD_HDMI1 ESD_HDMI1
15 15 DDC_CLK HDMI_CEC
VA811
HDMI_ARC ESD_HDMI2
14 14 NC
HDMI_CEC
13 13 CE_REMOTE
EAG59023302
EAG62611204
D803 12 CK-
12
1 10 D805
CK-_HDMI2
11 CK_GND
1 10
11 CK-_HDMI4
CK+ 2 9
10 CK+_HDMI2
10
CK+ 2 9
CK+_HDMI4
D0- 3 8
9
9
D0- 3 8
D0_GND 4 7
8 D0-_HDMI2
8
D0_GND 4 7
D0-_HDMI4
D0+ 5 6
7 D0+_HDMI2
7
D0+ 5 6
D1- D0+_HDMI4
6 ESD_HDMI1_IP4294 D1-
6 ESD_HDMI2_IP4294
D1_GND IP4294CZ10-TBR
5 D1_GND IP4294CZ10-TBR
5
D1+ D804
4 D1+ D806
1 10 D1-_HDMI2 4
3
D2-
D2-
1 10
2 9 D1+_HDMI2 3 D1-_HDMI4
2
D2_GND
D2_GND
2 9
3 8 2 D1+_HDMI4
1
D2+
D2+
3 8
4 7 D2-_HDMI2 1
4 7
VA801 5 6 D2+_HDMI2
D2-_HDMI4
ESD_HDMI1_VARISTOR 5 6
JK800 D2+_HDMI4
ESD_HDMI1_IP4294
BODY_SHIELD
ESD_HDMI2
VA800-*1 JK801
IP4294CZ10-TBR VA806 ESD_HDMI2_IP4294
1uF 20
HDMI-2
10V
19
18
HOT_PLUG_DETECT
VDD[+5V]
IP4294CZ10-TBR
17
ESD_HDMI1_CAP DDC/CEC_GND
16
15
SDA MHL_CD_SENSE
SCL
VA801-*1 14
13
RESERVED
1uF 12
CEC
TMDS_CLK-
C800
10V 11
TMDS_CLK_SHIELD VA807 0.047uF R817
10
ESD_HDMI1_CAP 9
TMDS_CLK+
TMDS_DATA0-
5.6V 25V 300K
8
7
TMDS_DATA0_SHIELD
OPT
6
TMDS_DATA0+
TMDS_DATA1-
MHL Spec
5
4
TMDS_DATA1_SHIELD
TMDS_DATA1+
HDMI-2 HDMI-2
3
TMDS_DATA2-
2
TMDS_DATA2_SHIELD
1
TMDS_DATA2+
JK801-*1
DAADR019A
HDMI-2_EMI_FOOSUNG
CEC TMDS_CH1-
D803-*1
NC_4 TMDS_CH1-
D804-*1
NC_4 TMDS_CH1-
D805-*1
NC_4 TMDS_CH1-
D806-*1
NC_4
1 10 1 10 1 10 1 10
100 TMDS_CH2-
4 7
NC_2 TMDS_CH2-
4 7
NC_2 TMDS_CH2-
4 7
NC_2 TMDS_CH2-
4 7
NC_2
HDMI_CEC CEC_REMOTE_S7
TMDS_CH2+ NC_1 TMDS_CH2+ NC_1 TMDS_CH2+ NC_1 TMDS_CH2+ NC_1
5 6 5 6 5 6 5 6
5V_HDMI_4 +5V_Normal
5V_HDMI_2 +5V_Normal +3.5V_ST D803-*2 D804-*2 D805-*2 D806-*2
1 10 1 10 1 10 1 10
2 9 2 9 2 9 2 9
A1
A2
A1
A2
A1
A2
3 8 3 8 3 8 3 8
MMBD6100 MMBD6100
MMBD6100 D801 D802 4 7 4 7 4 7 4 7
D800 5 6 5 6 5 6 5 6
C
C
C
DDC_SCL_4
DDC_SCL_2
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
SPDIF
JK1001
JST1223-001
GND
Fiber Optic
VCC
2
VINPUT
3
SPDIF_OUT
4
C1001 C1002
FIX_POLE
OPT 1uF 18pF
10V 50V
ESD Ready
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+1.5V_DDR +1.5V_DDR Option : Ripple Check !!!
R1201 1K1%
DDR_EXT
C1202 1000pF
A-MVREFDQ A-MVREFCA
1K1%
C1201 0 . 1 u F
C1213 0 . 1 u F
C12141000pF
10uF 10V
C1219
C1220
C1221
C1222
C1223
0.1uF
0.1uF
0.1uF
DDR_EXT
DDR_EXT
DDR_EXT
DDR_EXT
C1217
C1218
C1224
C1216
1uF
1uF
1uF
1uF
1uF
DDR_EXT
DDR_EXT
R1202
DDR_1600_1G_HYNIX
IC1201 M1A_256M
H5TQ1G63EFR-PBC IC101
DDR_1600_2G_HYNIX_NEW
DDR_1600_1G_SS DDR_1600_2G_HYNIX_OLD LGE2132(M1A_256M)
IC1201-*3 EAN61829003
IC1201-*1 IC1201-*2
H5TQ2G63FFR-PBC M8 N3
K4B1G1646G-BCK0 H5TQ2G63DFR-PBC A-MVREFCA A-MA0
EAN61829204 VREFCA A0
EAN61836301 EAN61829203 N3 M8 P7
N3 M8 N3 M8 P7
A0 VREFCA
A1 A-MA1 E11
P7
A0 VREFCA
P7
A0 VREFCA
P3
A1 P3 A-MA0 B_DDR3_A[0]
P3
A1
P3
A1
N2
A2
H1 A2 A-MA2 F12
N2
A2
H1 N2
A2
H1 P8
A3 VREFDQ H1 N2 A-MA1 B_DDR3_A[1]
P8
A3 VREFDQ
P8
A3 VREFDQ
P2
A4 A-MVREFDQ VREFDQ A3 A-MA3 D10
P2
A4
P2
A4
R8
A5
L8 P8 A-MA2 B_DDR3_A[2]
R8
A5
L8 R8
A5
L8 R2
A6 ZQ
A4 A-MA4 B10
R2
A6 ZQ
R2
A6 ZQ
T8
A7
DDR_EXT P2 A-MA3 B_DDR3_A[3]
T8
A7
T8
A7
R3
A8
B2 R1203 A5 A-MA5 E15
R3
A8
B2 R3
A8
B2 L7
A9 VDD_1
D9 L8 R8 A-MA4 B_DDR3_A[4]
L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 R7
A10/AP VDD_2
G7 ZQ A6 A-MA6 B11
R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 N7
A11 VDD_3
K2 240 R2 A-MA5 B_DDR3_A[5]
N7
A11 VDD_3
K2 N7
A11 VDD_3
K2 T3
A12/BC VDD_4
K8 +1.5V_DDR A7 A-MA7 F14
T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8
A13 VDD_5
N1 1% T8 A-MA6 B_DDR3_A[6]
A13 VDD_5
N1
A13 VDD_5
N1 M7
VDD_6
N9 A8 A-MA8 C11
M7
VDD_6
N9 M7
VDD_6
N9
NC_5 VDD_7
R1 B2 R3 A-MA7 B_DDR3_A[7]
NC_5 VDD_7
R1
NC_5 VDD_7
R1 M2
VDD_8
R9 VDD_1 A9 A-MA9 D14
D9 L7
DDR_EXT 10V C1203 A-MA8 B_DDR3_A[8]
VDD_8 VDD_8 BA0 VDD_9
M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9 N8
BA1 10uF VDD_2 A10/AP A-MA10 A12
N8 N8 M3
BA1 BA1 BA2
C1204 0.1uF G7 R7 A-MA9 B_DDR3_A[9]
M3
BA2
A1
M3
BA2
A1 J7
VDDQ_1
A1
A8
DDR_EXT VDD_3 A11 A-MA11 F16
VDDQ_1 VDDQ_1 CK VDDQ_2
C1205 0.1uF K2 N7 A-MA10 B_DDR3_A[10]
J7
K7
CK VDDQ_2
A8
C1
J7
K7
CK VDDQ_2
A8
C1
K7
K9
CK VDDQ_3
C1
C9
DDR_EXT VDD_4 A12/BC A-MA12 D13
CK VDDQ_3 CK VDDQ_3 CKE VDDQ_4
C1206 0.1uF K8 T3 A-MA11 B_DDR3_A[11]
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2 L2
VDDQ_5
D2
E9
DDR_EXT VDD_5 NC_7 A-MA13 D15
VDDQ_5 VDDQ_5 CS VDDQ_6
C1207 0.1uF N1 A-MA12 B_DDR3_A[12]
L2
K1
CS VDDQ_6
E9
F1
L2
K1
CS VDDQ_6
E9
F1
K1
J3
ODT VDDQ_7
F1
H2
DDR_EXT VDD_6 C12
ODT VDDQ_7 ODT VDDQ_7 RAS VDDQ_8
C1208 0.1uF N9 M7 A-MA13 B_DDR3_A[13]
J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9
K3
L3
CAS VDDQ_9
H9
DDR_EXT VDD_7 NC_5 E13
CAS VDDQ_9 CAS VDDQ_9 WE
C1209 0.1uF R1 A-MA14 B_DDR3_A[14]
L3
WE
J1
L3
WE
J1 T2
NC_1
J1
J9
DDR_EXT VDD_8
NC_1 NC_1 RESET NC_2
C1210 0.1uF R9 M2
T2
RESET NC_2
J9 T2
RESET NC_2
J9
NC_3
L1
DDR_EXT VDD_9 BA0 A-MBA0 A-MCK A9
1%
L1 L1 L9
R1207
N8 A-MBA0
DDR_EXT DDR_EXT
NC_3
L9
NC_3
L9 F3
NC_4
T7
DDR_EXT C1211 0.1uF B_DDR3_BA[0]
F3
NC_4
T7 F3
NC_4
T7 G3
DQSL NC_6
BA1 A-MBA1 D16
DQSL NC_6 DQSL NC_6 DQSL
C1212 0.1uF M3 A-MBA1 B_DDR3_BA[1]
DDR_EXT DDR_EXT
56
G3 G3
DQSL DQSL
C7 A9 BA2 A-MBA2 A10
C7 A9 C7 A9 B7
DQSU VSS_1
B3 A1 C1215 A-MBA2 B_DDR3_BA[2]
B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3
DQSU VSS_2
E1 VDDQ_1
1%
DQSU VSS_2 DQSU VSS_2 VSS_3 A8 J7
R1208
E1 E1 E7 G8
E7
VSS_3
G8 E7
VSS_3
G8 D3
DML VSS_4
J2 VDDQ_2 CK 0.01uF C13
D3
DML VSS_4
J2 D3
DML VSS_4
J2
DMU VSS_5
J8 C1 K7 50V A-MCK B_DDR3_MCLK
VDDQ_3 CK B13
56
DMU VSS_5 DMU VSS_5 VSS_6
J8 J8 E3 M1
E3
VSS_6
M1 E3
VSS_6
M1 F7
DQL0 VSS_7
M9 C9 K9 A-MCKB B_DDR3_MCLKZ
F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 F2
DQL1 VSS_8
P1 VDDQ_4 CKE A-MCKE E17
F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 F8
DQL2 VSS_9
P9 D2 A-MCKE B_DDR3_MCLKE
F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 H3
DQL3 VSS_10
T1 VDDQ_5 A-MCKB
H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1 H8
DQL4 VSS_11
T9 E9 L2
H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 G2
DQL5 VSS_12 VDDQ_6 CS A/B_DDR3_CS B8
G2
DQL5 VSS_12
G2
DQL5 VSS_12
H7
DQL6 F1 K1 A-MODT B_DDR3_ODT
H7
DQL6
H7
DQL6 DQL7
B1 VDDQ_7 ODT A-MODT C8
DQL7
B1
DQL7
B1 D7
VSSQ_1
B9 H2 J3 A-MRASB B_DDR3_RASZ
D7
VSSQ_1
B9 D7
VSSQ_1
B9 C3
DQU0 VSSQ_2
D1 VDDQ_8 RAS A-MRASB +1.5V_DDR B9
C3
DQU0 VSSQ_2
D1 C3
DQU0 VSSQ_2
D1 C8
DQU1 VSSQ_3
D8 H9 K3 A-MCASB B_DDR3_CASZ
C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 C2
DQU2 VSSQ_4
E2 VDDQ_9 CAS A-MCASB DDR_EXT D11
C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 A7
DQU3 VSSQ_5
E8 L3 R1206 A-MWEB B_DDR3_WEZ
A-MWEB
A-MDQSL
WE
A-MDQSU
DQU3 VSSQ_5 DQU3 VSSQ_5 DQU4 VSSQ_6
A7 E8 A7 E8 A2 F9
A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 B8
DQU5 VSSQ_7
G1 J1
B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 A3
DQU6 VSSQ_8
G9 NC_1 10K F10
A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9
DQU7 VSSQ_9 J9 T2 A-MRESETB B_RESET
DQU7 VSSQ_9 DQU7 VSSQ_9 NC_2 RESET A-MRESETB
A-MDQSLB
A-MDQSUB
L1
NC_3 D12
L9 A/B_DDR3_CS B_DDR3_CS0
NC_4
T7 F3
A-MA14 NC_6 DQSL A-MDQSL A19
G3 B_DDR3_DQSL
DQSL A-MDQSLB B18
B_DDR3_DQSU
A9 C7
VSS_1 DQSU A-MDQSU C16
B3 B7 A-MDML B_DDR3_DQML
VSS_2 DQSU A-MDQSUB D21
E1 A-MDMU B_DDR3_DQMU
VSS_3
G8 E7
VSS_4 DML A-MDML C18
J2 D3 B_DDR3_DQSBL
VSS_5 DMU A-MDMU C17
J8 B_DDR3_DQSBU
VSS_6
M1 E3
VSS_7 DQL0 A-MDQL0 A20
M9 F7 A-MDQL0 B_DDR3_DQL[0]
VSS_8 DQL1 A-MDQL1 A16
P1 F2 A-MDQL1 B_DDR3_DQL[1]
VSS_9 DQL2 A-MDQL2 C19
P9 F8 A-MDQL2 B_DDR3_DQL[2]
VSS_10 DQL3 A-MDQL3 C15
T1 H3 A-MDQL3 B_DDR3_DQL[3]
VSS_11 DQL4 A-MDQL4 C20
T9 H8 A-MDQL4 B_DDR3_DQL[4]
VSS_12 DQL5 A-MDQL5 C14
G2 A-MDQL5 B_DDR3_DQL[5]
DQL6 A-MDQL6 B21
H7 A-MDQL6 B_DDR3_DQL[6]
DQL7 A-MDQL7 B15
B1 A-MDQL7 B_DDR3_DQL[7]
VSSQ_1 F18
B9 D7 A-MDQU0 B_DDR3_DQU[0]
VSSQ_2 DQU0 A-MDQU0 D19
D1 C3 A-MDQU1 B_DDR3_DQU[1]
VSSQ_3 DQU1 A-MDQU1 D17
D8 C8 A-MDQU2 B_DDR3_DQU[2]
VSSQ_4 DQU2 A-MDQU2 E21
E2 C2 A-MDQU3 B_DDR3_DQU[3]
VSSQ_5 DQU3 A-MDQU3 E19
E8 A7 A-MDQU4 B_DDR3_DQU[4]
VSSQ_6 DQU4 A-MDQU4 D20
F9 A2 A-MDQU5 B_DDR3_DQU[5]
VSSQ_7 DQU5 A-MDQU5 D18
G1 B8 A-MDQU6 B_DDR3_DQU[6]
VSSQ_8 DQU6 A-MDQU6 F20
G9 A3 A-MDQU7 B_DDR3_DQU[7]
VSSQ_9 DQU7 A-MDQU7
R1209
E9
ZQ
240
1%
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Serial Flash for SPI boot
+3.5V_ST +3.5V_ST
SPI_FLASH_MACRONIX
OPT IC1300
R1301
+3.5V_ST 4.7K MX25L8006EM2I-12G
C1300
CS# VCC 0.1uF
/SPI_CS 1 8
OPT
R1300
10K SO/SIO1 HOLD#
SPI_SDO 2 7
WP# SCLK
/FLASH_WP 3 6 SPI_SCK
R1302
GND SI/SIO0 33
4 5 SPI_SDI
SPI_FLASH_WINBOND
IC1300-*1
W25Q80BVSSIG
CS VCC
1 8
DO[IO1] HOLD[IO3]
2 7
%WP[IO2] CLK
3 6
GND DI[IO0]
4 5
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LVDS_EU
28 RXB4+
FOR FHD REVERSE(8bit) 26
27
29 RXB4- Change in S7LR 28
30 RXB3+ 29
31 RXB3-
MIRROR Pol-change Shift
30
RXA4+ RXA4+ RXA4- RXA0-
32 RXBCK+
RXA4- RXA4- RXA4+ RXA0+ 31
33 RXBCK-
RXA3+ RXA0+ RXA0- RXA1-
34
RXA3- RXA0- RXA0+ RXA1+
35 RXB2+
RXACK+ RXA1+ RXA1- RXA2-
36 RXB2-
RXACK- RXA1- RXA1+ RXA2+
37
RXA2+ RXA2+ RXA2- RXACK-
38 RXB1+
RXA2- RXA2- RXA2+ RXACK+
39 RXB1-
RXA1+ RXACK+ RXACK- RXA3-
40 RXB0+
RXA1- RXACK- RXACK+ RXA3+
41 RXB0-
R1802 0 RXA0+ RXA3+ RXA3- RXA4-
EU pin assign is different from NON EU.
42
MO_FHD
R1803 0 RXA0- RXA3- RXA3+ RXA4+
Because of position of HD wafer.
43
MO_FHD
44
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
CI Region * Option name of this page : CI_SLOT
(because of Hong Kong)
CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_DATA[0-7]
+5V_Normal AR1903 33
C1903 FE_TS_DATA[7]
CI_MDI[7]
10uF FE_TS_DATA[6]
10V CI_MDI[6]
FE_TS_DATA[0-7]
R1908 FE_TS_DATA[5]
CI_MDI[5]
10K FE_TS_DATA[4]
CI_SLOT_JACK CI_MDI[4]
/CI_CD1 P1900
10067972-000LF
AR1904 33 FE_TS_DATA[3]
R1914 35 1 CI_MDI[3]
100 CI_DATA[3] FE_TS_DATA[2]
36 2 CI_MDI[2] FE_TS_DATA[1]
AR1900 CI_DATA[4]
CI_DATA[0-7]
33 37 3 CI_MDI[1] FE_TS_DATA[0]
CI_DATA[5] R1919
CI_TS_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
CI_TS_DATA[5] 39 5
CI_DATA[7] FE_TS_DATA[0-7]
CI_TS_DATA[6] 40 6
R1917 R1921 33
CI_TS_DATA[7] 41 7 47 CI_MISTRT FE_TS_SYNC
CI_ADDR[10] /PCM_CE R1922 33
42 8 CI_MIVAL_ERR FE_TS_VAL_ERR
R1910 10K R1923 100
43 9 CI_OE CI_MCLKI FE_TS_CLK
CI_ADDR[11]
CI_IORD 44 10 +5V_Normal
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R1920
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14
CI_MDI[2] 49 15 CI_WE
50 16 R1918 100
CI_MDI[3] /PCM_IRQA
51 17
CI_MDI[4]
GND
C1901
0.1uF
52
53
18
19
C1904
0.1uF
C1905
0.1uF
CI HOST I/F
GND
CI_MDI[5] 54 20
+5V_Normal CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R1900 CI_MDI[7] 56 22 GND +3.3V_Normal
10K R1911 10K CI_ADDR[6]
57 23
R1903 CI_ADDR[5]
47 58 24
PCM_RST CI_ADDR[4]
R1904 47 CI_DET
/PCM_WAIT 59 25 IC1902
CLOSE TO MSTAR CI_ADDR[3]
REG 60 26 C1906
R1905 100 CI_ADDR[2]
CI_TS_CLK 61 27 0.1uF
R1906 33 CI_ADDR[1] 1OE VCC 16V
CI_TS_VAL 62 28 1 20
R1907 33 CI_ADDR[0]
CI_TS_SYNC 63 29 TOSHIBA
CI_DATA[0]
64 30 1A1 2OE
AR1901 33 CI_DATA[1] 2 19
65 31 CI_ADDR[0-14] PCM_A[0]
CI_TS_DATA[0] CI_DATA[2] AR1902 AR1910
66 32 0ITO742440D
100 100
CI_TS_DATA[1] 67 33 2Y4 1Y1
CI_ADDR[7] 3 18 CI_ADDR[0]
CI_TS_DATA[2] 68 34
CI_TS_DATA[3] CI_ADDR[6] CI_ADDR[1]
G2 69 G1 CI_ADDR[5] 1A2 2A4 CI_ADDR[2]
PCM_A[1] 4 17 PCM_A[7]
R1912 CI_ADDR[4] CI_ADDR[3]
100
/CI_CD2 2Y3 1Y2
TC74LCX244FT
+5V_Normal GND 5 16
2Y1 1Y4
CI_MISTRT 9 12
CI_MIVAL_ERR
GND 2A1
10 11 PCM_A[4]
CI_MCLKI
CI DETECT +3.3V_Normal
OR_GARE_CI_PHILIPS
IC1900
74LVC1G32GW +3.3V_Normal AR1905 33
CI_DATA[0] PCM_D[0]
B 1 5 VCC
/CI_CD2 CI_DATA[1] PCM_D[1]
CI_DATA[0-7]
A 2
/CI_CD1 CI_DATA[2] PCM_D[2] IC1902-*1
GND 3 4 Y R1913 CI_DATA[3] PCM_D[3] 74LCX244FT
10K
PCM_D[0-7]
OR_GARE_CI_TI OR_GATE_CI_TOSHIBA R1924 AR1906 33 1OE BUFFER_CI VCC
IC1900-*1 IC1900-*2 0 CI_DATA[4] PCM_D[4] 1 20
SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION
CI_DET CI_DATA[5] PCM_D[5]
A VCC IN_B VCC
1 5 1 5 CI_DATA[6] PCM_D[6] 1A1 2OE
/PCM_CD 2 19
B
2
IN_A
2
R1915 CI_DATA[7] PCM_D[7]
47
GND Y GND OUT_Y
3 4 3 4
2Y4 1Y1
3 18
PCM_D[0-7]
CI_DATA[0-7] 1A2 2A4
4 17
2Y3 1Y2
5 16
CI POWER ENABLE CONTROL CI_ADDR[8]
AR1908 33
PCM_A[8] 1A3 2A3
6 15
CI_ADDR[9] PCM_A[9]
CI_ADDR[10] PCM_A[10]
2Y2 1Y3
CI_ADDR[11] PCM_A[11] 7 14
+5V_Normal IC1901
AP2151WG-7 +5V_CI_ON 1A4 2A2
8 13
L1900
BLM18PG121SN1D AR1909 33
IN OUT
5 1 CI_ADDR[12] PCM_A[12] 2Y1 1Y4
9 12
CI_ADDR[13] PCM_A[13]
GND CI_ADDR[14] PCM_A[14]
2 GND 2A1
R1916 REG /PCM_REG 10 11
C1902
100K
R1902 1uF
100 EN FLG 10V
PCM_5V_CTL 4 3
R1901 AR1907 33
10K CI_OE /PCM_OE
CI_WE /PCM_WE
CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DVB-S2 LNB Part Allegro
(Option:LNB)
3A
+12V_LNB
2A LNB_SX34
D2705-*1
40V
LNB
Max 1.3A
L2702
SP-7850_15
D2705 15uH
LNB LNB_SMAB34
D2703 40V 3.5A
30V
LNB
C2708
LNB LNB LNB LNB 10uF
C2703 C2704 C2705 C2706 25V
0.01uF 10uF 10uF 10uF
50V 25V 25V 25V
[EP]GND
LNB
C2709
GNDLX
BOOST
LNB
NC_3
NC_2
C2707 0.1uF
50V
LX
0.1uF
20
19
18
17
16
LNB
D2702 VCP 1 15 VIN
close to TUNER MBR230LSFT1G
LNB
THERMAL
GND
LNB_OUT 2 21 14
LNB
30V NC_1 VREG R2703
3 13 36K
LNB
LNB LNB LNB TDI ISET 1/16W 1%
R2702 C2712 LNB_SMAB34 4 IC2701 12
LNB LNB LNB LNB C2713
C2714 C2701 C2702 D2701
2.2K 0.22uF 0.1uF D2704 TDO A8303SESTR-T TCAP
1W 25V 50V 40V 5 11
18pF 18pF 33pF
LNB
10
6
9
LNB_SX34 C2710
D2704-*1 0.1uF
IRQ
SCL
SDA
ADD
40V LNB
TONECTRL
C2711
Close to Tuner 0.22uF
Surge protectioin
A_GND A_GND
R2706
0
LNB LNB
R2704 R2705
33 33
R2701
0
LNB_TX
DEMOD_SCL
DEMOD_SDA
A_GND
Max 1.3A
+12V +12V_LNB
LNB
L2701
BLM18PG121SN1D
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
SCART_COMPONENT
REAR COMPONENT PHONE JACK(EAX65149705) SCART AMP
COMPONENT +12V
JK2802
PEJ029-02
8 G_SPRING
EU
C2808
3 E_SPRING
0.1uF
COMP2_Pr+ IC2801 50V
VA2802 R2801 AZ4580MTR-E1
4 R_SPRING 5.5V 75
EU
ESD_COMP R2831
T_SPRING 2.2K OUT1 8 VCC
5 DTV/MNT_L_OUT 1
VA2801
COMP2_Pb+
EU
EU EU
R2800 EU
B_TERMINAL 5.5V C2804 R2834 R2844
7 75 OPT 33K IN1- OUT2 2.2K
10uF 2 7
ESD_COMP R2832 DTV/MNT_R_OUT
16V 470K EU
6 T_TERMINAL R2841 EU
EU IN1+ IN2- 33K C2812
3 6 OPT 10uF
EU R2836
C2807 10K EU R2843 16V
33pF 470K
R2839
VEE 5 IN2+ 10K
4 EU
COMP2_Y+ C2810
33pF
R2804 EU
D2800-*1 D2800 75 R2835
5.6K EU
ESD_COMP_ZENER_KEC ESD_COMP_ZENER_ROHM R2840
SCART1_Lout
5.6K
D2801-*1 D2801 SCART1_Rout
ESD_COMP_ZENER_ROHM 330pF 220K
ESD_COMP_ZENER_KEC C2806 R2833
EU EU EU EU
R2842 C2811
220K 330pF
+3.3V_Normal
R2812 R2814
10K 1K CLOSE TO MSTAR
Rear_COMP_DET
CLOSE TO MSTAR
VA2800
5.6V
OPT
OPT C2800
0.1uF
16V
1
ESD_SCART
EU EU
JK2801 R2825
10K
PSC008-01 SC1/COMP1_R_IN
VA2809
5.6V R2809 R2830
470K 12K
ESD_SCART
EU
DTV/MNT_L_OUT
EU
VA2806 C2813
5.6V 1000pF
OPT 50V
DTV/MNT_R_OUT
EU
VA2805 C2814
5.6V 1000pF
OPT 50V
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
External SPK from EAX653346302
EXT_SPK
+24V JK3001
PEJ034-01
BLM18PG121SN1D
3 E_SPRING
EXT_SPK
L3005
OPT EXT_SPK 4 R_SPRING
EXT_SPK_DET EXT_SPK C3011 C3014 EXT_OUT_R
C3024
0.1uF 0.1uF 4.7uF
+3.5V_ST 50V 50V 50V 5 T_SPRING
EXT_OUT_L
10V C3007 C3009 +3.3V_Normal
HEAD_PHONE
7B B_TERMINAL2
1uF
R3031
1uF
OPT 10V OPT
R3030
EXT_SPK
T_TERMINAL2
10K
1K
R3017
TPA3124D2PWPR L3002-*1 L3003-*1
HEAD_PHONE 15K
22.0uH 22.0uH
R3009 100
EXT_SPK
R3029 100
EXT_SPK
HEAD_PHONE C PVCCL_1 PGNDL_2
C3015
R3032 1 24 EXT_SPK_DET
47uF
25V
47K B Q3012
HP_DET
MMBT3904(NXP) SD PGNDL_1 EXT_SPK_10uH
2 23
HEAD_PHONE
E EXT_OUT_L 10V C3010
L3002 EXT_SPK 1uF
R3015 C3018 C3016
PVCCL_2 LOUT 10.0uH 10K
EXT_SPK 4.7K 0.22uF 0.47uF
3 22 R3010
50V 50V
EXT_SPK C3025 EXT_SPK OPT
EXT_SPK
R3023 0.22uF
HP_MUTE/SUB_MUTE MUTE BSL
EXT_SPK
10K
C3006
4 21 50V C3012 C3021
47uF
EXT_SPK R3007
25V
0.22uF 0.47uF
C3013 10.0uH 4.7K
10V 50V 50V
LIN AVCC_2 L3003 EXT_SPK EXT_SPK OPT
1uF 5 20
EXT_SPK_10uH EXT_OUT_R
HP_LOUT/Ext_LOUT
EXT_SPK
RIN AVCC_1 10K
6 19
HP_ROUT/Ext_ROUT R3027
10V R3013
1uF BYPASS GAIN0 10K
OPT R3016
C3027 7 18 10K
EXT_SPK EXT_SPK
AGND_1 GAIN1 GAIN0 GAIN1 AMP GAIN
8 17
0 0 20dB
R3018 R3008
AGND_2 BSR EXT_SPK 10K 10K 1 0 26dB
9 16 EXT_SPK
C3026 OPT 0 1 32dB
0.22uF
PVCCR_1 ROUT 50V 1 1 36dB
C3023 10 15
1uF
50V VCLAMP PGNDR_2
EXT_SPK 11 14
Headphone
+3.3V_Normal
HEAD_PHONE
R3002
10K HEAD_PHONE
HEAD_PHONE
HP_ROUT/Ext_ROUT JK3002
C3003
OPT
C E PEJ034-01
10uF HEAD_PHONE
C3005 R3001 Q3004 B E_SPRING
16V 1K Q3005 3
1000pF MMBT3904(NXP) MMBT3904(NXP)
50V HEAD_PHONE_POP B HEAD_PHONE_POP
+3.5V_ST E C
E
HEAD_PHONE_POP HEAD_PHONE_POP
HEAD_PHONE_POP Q3006 HP_DET
MMBT3906(NXP) R_SPRING
10K C R3011 B 4
R3006 3.3K
B C
T_SPRING 5
Q3009
HP_MUTE/SUB_MUTE MMBT3904(NXP)
HEAD_PHONE_POP E
B_TERMINAL2 7B
HEAD_PHONE T_TERMINAL2 6B
HP_LOUT/Ext_LOUT
C3001 C E
OPT
R3033
10uF HEAD_PHONE
C3008 R3003 Q3002 B
16V Q3001
1K
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
L14 TUNER_EU T/C_T2/C/S2_CHINA
C3708 C3714
0.1uF Close to TUNER
NC_1 NC_1 NC_1 2100pF
50V 16V
2 2 2
IF_AGC AIF_AGC AIF_AGC should be guarded by ground
+3.3V_TU
3 3 3 C3703 IF_AGC_MAIN
0.1uF R3714
16V 0
SCL SCL_RF SCL_RF TU_I2C_NON_FILTER R3716
R3738 33 1K
R3717
1K
4 4 4 TU_SCL
TU_I2C_FILTER
R3738-*1
SDA SDA_RF SDA_RF TU_I2C_NON_FILTER MLG1005SR27JT
5 5 5 C3705 C3707
R3739 33
TU_SDA
C3710 C3711 R3726OPT 0
20pF 20pF TU_I2C_FILTER
20pF 20pF
IF[P] AIF[P] AIF[P] R3709 50V 50V 50V 50V
R3739-*1
MLG1005SR27JT +3.3V_TU +3.3V_TU
6 6 6 10
IF_P_MSTAR
CHINA CHINA CHINA
IF[N] AIF[N] AIF[N] R3725
470
CHINA
R3728
R3732
220
R3735
220
7 7 7 IF_N_MSTAR
82
TU_SIF TU_CVBS
close to TUNER E
R3710
NC_2 NC_2 NC_2 10 C3726
E
CHINA
CHINA
Q3701
8 8 8 Q3700 B MMBT3906(NXP)
0.1uF R3724 B MMBT3906(NXP) C
4.7K
NC_3 NC_3 NC_3 16V
CHINA
CHINA C
9 9 9 R3731OPT 0
NC_4 NC_4
10 10 CHINA
AR3700-*1 47
TU_GND_B
12 12 FE_TS_ERR CHINA
AR3701-*1 47
FE_TS_CLK
GND_1 GND_1 FE_TS_SYNC
SHIELD 13 13 FE_TS_VAL
T2
MCLK MCLK
14 14 CHINA
AR3702-*1 47
SYNC SYNC
15 15
VAILD VALID
16 16
AR3701
0 FE_TS_DATA[0-7]
D0 D0 1/16W
17 17 FE_TS_DATA[0]
FE_TS_DATA[1]
D1 D1 FE_TS_DATA[2]
18 18 FE_TS_DATA[3]
T2
D2 D2
19 19
D3 D3
20 20
AR3702
0
D4 D4 1/16W
21 21 FE_TS_DATA[4]
+3.3V_LNA +3.3V_TU +3.3V_Normal
FE_TS_DATA[5]
D5 D5 FE_TS_DATA[6]
22 22 FE_TS_DATA[7]
T2 L3701 L3704
D6 D6 UBW2012-121F UBW2012-121F
23 23 C3739 C3706 C3730 C3731 C3733 C3738
22uF 0.1uF 22uF 0.1uF 22uF 0.1uF
D7 D7 10V 16V 10V 16V 10V 16V
24 24
T2_OR_CHINA
RESET_DEMOD RESET_DEMOD R3719 IC3701
25 25 10
DEMOD_RESET
+3.3V_TU AP7361-Y-13
+1.2V_DEMOD
T2_OR_CHINA T2_OR_CHINA
C3716 +3.3V_S2_DE R3723
B3[+3.3V] B3[+3.3V] 0.1uF 3.3K EN
1 5
OUT
26 26 16V
T2_OR_CHINA
T2_OR_CHINA C3725
C3721 C3723 1uF GND T2_OR_CHINA
SCL_DEMOD SCL_DEMOD T2_OR_CHINA 100pF 0.1uF 10V 2 T2_OR_CHINA R3737
1
27 27 R3711
C3702
22
DEMOD_SCL
50V 16V T2_OR_CHINA R3733
12K T2_OR_CHINA
ADJ/NC IN 1% C3737
20pF 3 4 R1
B4[+1.1V] B4[+1.1V] 50V +1.2V_DEMOD 10uF
10V
28 28 T2_OR_CHINA
C3713 C3729 T2_OR_CHINA
100pF 0.1uF C3732
T2_OR_CHINA 50V 16V
F22_OUTPUT F22_OUTPUT R3707 T2_OR_CHINAT2_OR_CHINA
0.1uF
16V
29 29 0
LNB_TX
T2_OR_CHINA
SDA_DEMOD SDA_DEMOD T2_OR_CHINA
R3712 22
R3734
30 30 C3704 DEMOD_SDA
22K
1%
20pF R2
50V
LNB T2_OR_CHINA Vo=0.8*(1+R1/R2)
31 C3709 LNB_OUT
0.1uF
50V GND seperation for CHINA tuner
TU_GND_A
A1 B1 GND T2_OR_CHINA
A1 B1 32
TU_GND_B
47
NON_CHINA
NON_CHINA
NON_CHINA
NON_CHINA
NON_CHINA
NON_CHINA
1C3712
R3708
R3713
R3715
R3718
R3720
R3721
2
2
C3701
1000pF 1000pF
A1 B1 2630V
10
10
10
10
10
10
630V
SHIELD A1 B1 CHINA CHINA
47
TU_GND_A
TU_GND_A
TU_GND_B
TU_GND_B
+3.3V_TU +3.3V_S2_DE
T2_OR_CHINA
47 L3702
BLM18PG121SN1D
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
TP for EU
RF_SWITCH_CTL HDMI_ARC
IF_AGC_SEL CK+_HDMI2
CK-_HDMI2
SPDIF_OUT D0+_HDMI2
D0-_HDMI2
5V_DET_HDMI_2 D1+_HDMI2
D1-_HDMI2
D2+_HDMI2
D2-_HDMI2
DDC_SDA_2
DDC_SCL_2
HPD2
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IR/LED + Digital Eye + Control
+3.5V_ST
R4603 R4604
10K 10K
1% 1%
R4601
100 P4600 OPT
KEY1 P4601
12507WR-10L
C4602 12507WR-08L
0.1uF
16V
R4602 1
100 1
KEY2
C4603 2
+3.5V_ST 0.1uF 2
16V
3
L4600 3
BLM18PG121SN1D
4
4
R4606
+3.5V_ST 1.8K
LED_R/BUZZ 5
C4600 C4601 5
VA4600
0.1uF 1000pF
16V 50V LED_R_Zener
R4600 6
3.3K 6
IR 7
C4604 7
VA4601
100pF IR_Zener
50V 8
8
9 9
+3.5V_ST +3.3V_Normal
10
+3.5V_ST
IR_OUT
IR_OUT R4610 Digital Eye Digital Eye Digital Eye 11
R4612 10K R4605 R4607 C4605
22 IR_OUT 1K 1K 18pF
IR_OUT IR_OUT R4611 50V
47K R4608 100
IR_OUT R4615 SENSOR_SCL
Q4601 C 10K Digital Eye
2SC3052 B IR_OUT
E R4613 R4609 100
SENSOR_SDA
C 47K Digital Eye Digital Eye
IR_OUT B C4606
Q4602 E 18pF
2SC3052 50V
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC102
H27U1G8F2CTR-BC
NAND FLASH MEMORY +3.3V_Normal +3.3V_Normal
NC_1 NC_29
1 NAND_FLASH_1G_HYNIX 48 M1A_256M
NC_2 NC_28
2 EAN35669103 47 IC101
NC_3 NC_27 PCM_A[0-7] <CHIP Config> LGE2132(M1A_256M) M1A_128M
3 46
22 (SPI_SDI, PM_LED, PWM_PM) IC101-*1
NC_4
4
NC_26 LG-NonOS SB51_ExtSPI 3’b000 51boot from SPI LGE2131(M1A_128M)
45 AR101 LG-OS HEMCU_ExtSPI 3’b001 MIPS boot from SPI
R107 R109 NC_5 I/O7 PCM_A[7] U19 D5
1K 3.9K 5 44 RXA4+ LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35 KEY1
NC_6 I/O6 PCM_A[6] T20 F8
AR103 6 43 RXA4- LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36 KEY2 U19 D5
22 T21 E7 LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35
R/B I/O5 PCM_A[5] RXA3+ LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37 SC1_ID PM_MODEL_OPT_0 --> SC1_ID T20 F8
7 42 T19 E6 LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36
RXA3- LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38 PANEL_CTL T21 E7
RE I/O4 PCM_A[4] R21 D6 LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37
/F_RB 8 41 +3.5V_ST RXACK+ LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39 SCART1_MUTE T19 E6
R20 LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38
/PF_OE CE NC_25 RXACK- LVACKM/TTL_B[5]/GCLK/GPIO175 R21 D6
9 40 R19 W10 LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39
/PF_CE0 RXA2+ LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20 MHL_CD_SENSE R20
NC_7 NC_24 P20 Y10 LVACKM/TTL_B[5]/GCLK/GPIO175
10 39 RXA2- LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21 /VBUS_EN R19 W10
P3 LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
4.7K
4.7K
2.7K
OPT NC_8 NC_23 C102 10uF 10V 85C PM_LED/GPIO4 PM_LED P20 Y10
R108 11 38 P19 Y3 LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21
+3.3V_Normal 1K C101 RXA1+ LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7 POWER_DET P3
OPT
OPT
0.1uF VCC_1 VCC_2 CHANGE TO N20 Y5 PM_LED/GPIO4
12 37 RXA1- LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17 AMP_MUTE P19 Y3
OPT 10UF 10V X5R N21 W11 LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7
R115
R117
R165
R105 VSS_1 VSS_2 C103 RXA0+ LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22 INV_CTL N20 Y5
13 36 0.1uF N19 D3 LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
1K RXA0- LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11 POWER_ON/OFF_1 N21 W11
NC_9 NC_22 M21 AA3 LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
14 35 RXB4+ LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14 RL_ON N19 D3
M20 W5 LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11
NC_10 NC_21 RXB4- LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15 /FLASH_WP M21 AA3
15 34 M19 D4 LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14
RXB3+ LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200 LED_R/BUZZ M20 W5
CLE NC_20 L20 L15 LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15
LED_R/BUZZ RXB3- LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8 PM_TXD M19 D4
16 33
AR102 PM_UART_RX/GPIO_PM[5]/GPIO12
Y11
PM_RXD L20
LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200
L15
/PF_CE1 ALE I/O3 PCM_A[3] PM_LED L19 LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8
17 32 RXBCK+ LVBCKP/TTL_R[0]/EPI4+/GPIO186 Y11
PF_ALE WE I/O2 PCM_A[2] K20 PM_UART_RX/GPIO_PM[5]/GPIO12
SPI_SDI RXBCK- LVBCKM/TTL_R[1]/EPI4-/GPIO187 L19
/PF_WE 18 31 K21 LVBCKP/TTL_R[0]/EPI4+/GPIO186
4.7K
4.7K
2.7K
WP I/O1 PCM_A[1] RXB2+ LVB2P/TTL_R[2]/EPI5+/GPIO188 K20
/PF_WP 19 30 K19 LVBCKM/TTL_R[1]/EPI4-/GPIO187
RXB2- LVB2M/TTL_R[3]/EPI5-/GPIO189 K21
OPT
AR104 NC_11 I/O0 PCM_A[0] J21 LVB2P/TTL_R[2]/EPI5+/GPIO188
22 R106 20 29 RXB1+ LVB1P/TTL_R[4]/EPI6+/GPIO190 K19
J20 LVB2M/TTL_R[3]/EPI5-/GPIO189
R116
R118
R121
R102 1K RXB1- J21
NC_12 NC_19 22 J19
LVB1M/TTL_R[5]/EPI6-/GPIO191
LVB1P/TTL_R[4]/EPI6+/GPIO190
3.3K 21 28 RXB0+ LVB0P/TTL_R[6]/EPI7+/GPIO192 J20
NC_13 NC_18 H20 LVB1M/TTL_R[5]/EPI6-/GPIO191
22 27 RXB0- LVB0M/TTL_R[7]/EPI7-/GPIO193 J19
LVB0P/TTL_R[6]/EPI7+/GPIO192
NC_14 NC_17 H20
23 26 LVB0M/TTL_R[7]/EPI7-/GPIO193
NC_15 NC_16
24 25
M1A_256M
IC101
LGE2132(M1A_256M) from CI SLOT
CI_TS_CLK
CI_TS_DATA[0-7]
Y1 V10
NAND_FLASH_2G_HYNIX NAND_FLASH_1G_TOSHIBA GPIO78 TS0CLK/GPIO92 CI_TS_SYNC
A0’h W4 T14 CI_TS_DATA[0] M1A_128M
EAN60708702 CI_TS_VAL
IC102-*1
EAN61508001 5V_DET_HDMI_4 GPIO79 TS0DATA[0]/GPIO82
T13 CI_TS_DATA[1] IC101-*1
H27U2G8F2CTR IC102-*2
R184 22 K17
TS0DATA[1]/GPIO83
U13 CI_TS_DATA[2] LGE2131(M1A_128M)
TC58NVG0S3ETA0BBBH I2C_SCL I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
EEPROM +3.3V_Normal R183 22 J 1 5 V15 CI_TS_DATA[3]
I2C_SDA I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85 CI_TS_DATA[4]
U8 U12
NC_1 NC_29 URSA/VCOM_SDA SDAM2/GPIO55 TS0DATA[4]/GPIO86 CI_TS_DATA[5]
1 48 NC_1 NC_29 NVRAM_RHOM T7 V13 Y1 V10
1 48 URSA/VCOM_SCL SCKM2/GPIO56 TS0DATA[5]/GPIO87 CI_TS_DATA[6] GPIO78 TS0CLK/GPIO92
NC_2 NC_28 IC104 U7 U14 W4 T14
2 47 NC_2 NC_28 SENSOR_SCL SCKM0/GPIO58 TS0DATA[6]/GPIO88 CI_TS_DATA[7] GPIO79 TS0DATA[0]/GPIO82
2 47 BR24G256FJ-3 V7 T11 Internal demod out T13
NC_3 NC_27 SENSOR_SDA SDAM0/GPIO59 TS0DATA[7]/GPIO89 TS0DATA[1]/GPIO83
3 46 NC_3 NC_27 C105 T2_OR_CHINA F6 T12 K17 U13
3 46 0.1uF R113 22 AMP_SCL I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91 FE_TS_CLK I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
NC_4 NC_26 DEMOD_SCL G6 V12 J15 V15
4 45 NC_4 NC_26 A0 VCC R114 22 AMP_SDA I2S_IN_SD/GPIO160 TS0VALID/GPIO90 FE_TS_DATA[0-7] I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85
4 45 1 8 DEMOD_SDA AA4 Y14 U8 U12
NC_5 I/O7 T2_OR_CHINA TU_SCL I2C_SCKM1/GPIO80 TS1CLK/GPIO103 FE_TS_DATA[0] FE_TS_SYNC SDAM2/GPIO55 TS0DATA[4]/GPIO86
5 44 NC_5 I/O8 Y4 Y16 T7 V13
5 44 TU_SDA I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93 FE_TS_DATA[1] FE_TS_VAL_ERR SCKM2/GPIO56 TS0DATA[5]/GPIO87
NC_6 I/O6 A1 WP AA15 U7 U14
6 43 NC_6 I/O7 2 7 TS1DATA[1]/GPIO94 FE_TS_DATA[2] SCKM0/GPIO58 TS0DATA[6]/GPIO88
6 43 J6 Y13 V7 T11
R/B I/O5 Rear_COMP_DET R185 ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95 FE_TS_DATA[3] SDAM0/GPIO59 TS0DATA[7]/GPIO89
7 42 RY/BY I/O6 K6 AA16 F6 T12
7 42 A2 SCL DSUB_DET EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96 FE_TS_DATA[4] FE_TS_DATA[0] I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91
RE I/O4 3 6 R111 22 I2C_SCL 0 W12 G6 V12
8 41 RE I/O5 TS1DATA[4]/GPIO97 FE_TS_DATA[0] I2S_IN_SD/GPIO160 TS0VALID/GPIO90
8 41 R186 G7 AA13 FE_TS_DATA[5] AA4 Y14
CE NC_25 I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98 FE_TS_DATA[6] I2C_SCKM1/GPIO80 TS1CLK/GPIO103
9 40 CE NC_25 GND SDA 0 W14 Y4 Y16
9 40 4 5 R112 22 TS1DATA[6]/GPIO99 I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93
NC_7 NC_24 I2C_SDA J4 W13 FE_TS_DATA[7] AA15
10 39 NC_7 NC_24 C104 C106 DEMOD_RESET ET_COL/GPIO60 TS1DATA[7]/GPIO100 TS1DATA[1]/GPIO94
10 39 J5 Y15 J6 Y13
NC_8 NC_23 8pF 8pF MODEL_OPT_0 ET_TXD[1]/GPIO61 TS1SYNC/GPIO102 ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95
11 38 NC_8 NC_23 W15 K6 AA16
11 38 OPT OPT TS1VALID/GPIO101 EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
VCC_1 VCC_2 EAN62389502 H19 W12
12 37 VCC_1 VCC_2 MODEL_OPT_1 LCK/GPIO194 TS1DATA[4]/GPIO97
12 37 G20 B3 R189 33 G7 AA13
VSS_1 VSS_2 MODEL_OPT_2 LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13 /SPI_CS I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98
13 36 VSS_1 VSS_2 SENSOR_SCL G19 A3 R188 33 W14
13 36 /MHL_OCP_DET LHSYNC/GPIO196 PM_SPI_SCK/GPIO1 SPI_SCK TS1DATA[6]/GPIO99
NC_9 NC_22 SENSOR_SDA G21 A4 J4 W13
14 35 NC_9 NC_22 FRC_RESET LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0 HP_MUTE/SUB_MUTE ET_COL/GPIO60 TS1DATA[7]/GPIO100
14 35 NVRAM_ATMEL 33 R182 C3 EPHY_RP J5 Y15
NC_10 NC_21 DEMOD_RESET PM_SPI_SDI/GPIO2 SPI_SDI ET_TXD[1]/GPIO61 TS1SYNC/GPIO102
15 34 NC_10 NC_21 IC104-*1 J17 A2 R190 33 EPHY_TN W15
15 34 FRC_RESET HP_DET UART2_RX/GPIO69 PM_SPI_SDO/GPIO3 SPI_SDO TS1VALID/GPIO101
CLE NC_20 AT24C256C-SSHL-T J16 EPHY_TP H19
16 33 CLE NC_20 SC1/COMP1_DET UART2_TX/GPIO70 LCK/GPIO194
16 33 E8 B1 EPHY_RN G20 B3
ALE I/O3 MHL_OCP_EN UART3_TX/GPIO52 RP EPHY_RP LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
17 32 ALE I/O4 A0 VCC D7 C2 G19 A3
17 32 1 8 RF_SWITCH_CTL
AMP_RESET UART3_RX/GPIO53 TN EPHY_TN LHSYNC/GPIO196 PM_SPI_SCK/GPIO1
WE I/O2 U6 C1 G21 A4
18 31 WE I/O3 MODEL_OPT_4 GPIO46[CTS] TP EPHY_TP IF_AGC_SEL LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
18 31 A1 WP V6 B2 C3
WP I/O1 2 7
RF_SWITCH_CTL GPIO47[RTS] RN EPHY_RN PM_SPI_SDI/GPIO2
19 30 WP I/O2 33 R181 K15 CI_DET J17 A2
19 30 /CI_CD1 UART1_TX/GPIO48 UART2_RX/GPIO69 PM_SPI_SDO/GPIO3
NC_11 I/O0 A2 SCL L16 D2 /CI_CD1 J16
20 29 NC_11 I/O1 3 6
/CI_CD2 UART1_RX/GPIO49 SPDIF_IN/GPIO161 5V_DET_HDMI_2 UART2_TX/GPIO70
20 29 D1 R192 100 /CI_CD2 E8 B1
NC_12 NC_19 +3.3V_Normal SPDIF_OUT/GPIO162 SPDIF_OUT UART3_TX/GPIO52 RP
21 28 NC_12 NC_19 GND SDA H5 SPDIF_OPTIC D7 C2
21 28 4 5 SPDIF_OUT
USB1_CTL ET_TX_EN/GPIO63 UART3_RX/GPIO53 TN
NC_13 NC_18 R180 K5 D8 U6 C1
22 27 NC_13 NC_18 10K MODEL_OPT_5 ET_RXD[0]/GPIO65 HWRESET SOC_RESET 5V_DET_HDMI_2 GPIO46[CTS] TP
22 27 K4 E5 V6 B2
NC_14 NC_17 R197 0 MODEL_OPT_6 ET_MDC/GPIO66 IRIN/GPIO5 IR GPIO47[RTS] RN
23 26 NC_14 NC_17 EAN61133501 CI_DET H6 G4 K15
23 26 R178 22 USB1_OCD ET_MDIO/GPIO67 DDCA_CK/UART0_RX RGB_DDC_SCL UART1_TX/GPIO48
NC_15 NC_16 /PCM_CD L5 G5 L16 D2
24 25 NC_15 NC_16 PCM_A[0-14] ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX RGB_DDC_SDA UART1_RX/GPIO49 SPDIF_IN/GPIO161
24 25 D1
PCM_A[0] SPDIF_OUT/GPIO162
U17 J18 H5
PCM_A[1] PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71 PWM0 ET_TX_EN/GPIO63
R18 K18 K5 D8
PCM_A[2] PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72 PWM1 ET_RXD[0]/GPIO65 HWRESET
V17 K16 K4 E5
PCM_A[3] PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73 PWM2 ET_MDC/GPIO66 IRIN/GPIO5
R16 L18 H6 G4
PCM_A[4] PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74 DSUB/SC1_OUT_CTRL ET_MDIO/GPIO67 DDCA_CK/UART0_RX
U16 L17 L5 G5
NAND_FLASH_2G_TOSHIBA NAND_FLASH_1G_SS PCM_A[5] PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75 PCM_5V_CTL ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX
T17
EAN60991001 EAN61857001 I2C PCM_A[6] PCMADR[5]/NF_AD[5]/GPIO106
+3.3V_Normal W18 T8 U17 J18
IC102-*3 IC102-*4 PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146 PF_ALE +3.3V_Normal PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71
PCM_A[7] U20 T9 R18 K18
TC58NVG1S3ETA00 K9F1G08U0D-SCB0 PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142 /PF_CE0 PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72
PCM_A[8] Y19 U9 L101 V17 K16
PCMADR[8]/GPIO113 NF_CLE/GPIO141 /PF_CE1 BLM18PG121SN1D PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73
PCM_A[9] AA19 U11 R16 L18
PCM_A[10] PCMADR[9]/GPIO115 NF_RBZ/GPIO147 /F_RB PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74
NC_1 NC_29 NC_1 NC_29 AA20 V9 U16 L17
1 48 1 48 PCM_A[11] PCMADR[10]/GPIO119 NF_REZ/GPIO144 /PF_OE PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75
W21 U10 T17
NC_2 NC_28 NC_2 NC_28 PCMADR[11]/GPIO117 NF_WEZ/GPIO145 /PF_WE R193 C119 PCMADR[5]/NF_AD[5]/GPIO106
2 47 2 47 R140 R141 R144 R145 PCM_A[12] V20 T10 10K 0.1uF W18 T8
1K 1K 2.2K 2.2K PCMADR[12]/GPIO109 NF_WPZ/GPIO199 /PF_WP PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
NC_3 NC_27 NC_3 NC_27 PCM_A[13] Y17 U20 T9
R196
3 46 3 46 PCM_A[14] PCMADR[13]/GPIO112 0 PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142
V18 W2 Y19 U9
NC_4 NC_26 NC_4 NC_26 PCMADR[14]/GPIO111 IF_AGC IF_AGC_MAIN PCMADR[8]/GPIO113 NF_CLE/GPIO141
4 45 4 45 AMP_SDA V19 W1 AA19 U11
PCM_D[0-7] /PCM_CD PCMCD_N/GPIO135 SIFM PCMADR[9]/GPIO115 NF_RBZ/GPIO147
NC_5 I/O8 NC_5 I/O7 AMP_SCL W19 W3 C120 AA20 V9
5 44 5 44 /PCM_CE PCMCE_N/GPIO120 SIFP 0.047uF PCMADR[10]/GPIO119 NF_REZ/GPIO144
PCM_D[0] U18 V2 W21 U10
NC_6 I/O7 NC_6 I/O6 I2C_SDA PCMDATA[0]/GPIO131 IM 25V PCMADR[11]/GPIO117 NF_WEZ/GPIO145
6 43 6 43 PCM_D[1] V16 V1 V20 T10
I2C_SCL PCMDATA[1]/GPIO132 IP PCMADR[12]/GPIO109 NF_WPZ/GPIO199
RY/BY I/O6 R/B I/O5 PCM_D[2] W17 Y17
7 42 7 42 PCMDATA[2]/GPIO133 PCMADR[13]/GPIO112
PCM_D[3] Y20 AA2 V18 W2
RE I/O5 RE I/O4 PCMDATA[3]/GPIO125 XIN CHINA PCMADR[14]/GPIO111 IF_AGC
8 41 8 41 PCM_D[4] R15 Y2 C115 0 . 1 u F R198CHINA47 V19 W1
PCMDATA[4]/GPIO124 XOUT PCMCD_N/GPIO135 SIFM
CE NC_25 CE NC_25 PCM_D[5] AA18 C116 0 . 1 u F R199 47 W19 W3
9 40 9 40 PCMDATA[5]/GPIO123 PCMCE_N/GPIO120 SIFP
PCM_D[6] T15 C123 U18 V2
NC_7 NC_24 NC_7 NC_24 PCMDATA[6]/GPIO122 CHINA CHINA 1000pF PCMDATA[0]/GPIO131 IM
10 39 10 39 PCM_D[7] Y21 ANALOG SIF OPT V16 V1
PCMDATA[7]/GPIO121 PCMDATA[1]/GPIO132 IP
NC_8 NC_23 NC_8 NC_23 W20 Close to MSTAR TU_SIF W17
11 38 11 38 /PCM_IORD PCMIORD_N/GPIO116 PCMDATA[2]/GPIO133
V21 Y20 AA2
VCC_1 VCC_2 VCC_1 VCC_2 DIMMING /PCM_IOWR PCMIOWR_N/GPIO114 PCMDATA[3]/GPIO125 XIN
12 37 12 37 Y18 R15 Y2
VSS_1 VSS_2 VSS_1 VSS_2
/PCM_IRQA
T16
PCMIRQA_N/GPIO110 Close to MSTAR AA18
PCMDATA[4]/GPIO124 XOUT
13 36 13 36 /PCM_OE PCMOE_N/GPIO118 PCMDATA[5]/GPIO123
R157 R17 IF_N_MSTAR T15
NC_9 NC_22 NC_9 NC_22 100 /PCM_REG PCMREG_N/GPIO128 PCMDATA[6]/GPIO122
PWM_DIM PWM2 R194 0 C117 0.1uF
14 35 14 35 T18 OPT Y21
NC_10 NC_21 NC_10 NC_21
PCM_RST
W16
PCM_RESET/GPIO134 C121 DTV_IF W20
PCMDATA[7]/GPIO121
15 34 15 34 /PCM_WAIT PCMWAIT_N/GPIO105 100pF PCMIORD_N/GPIO116
U15 V21
CLE NC_20 CLE NC_20 R156 10K /PCM_WE PCMWE_N/GPIO198 IF_P_MSTAR PCMIOWR_N/GPIO114
16 33 16 33 PWM0 R195 0 C118 0.1uF C122 C124 Y18
33pF 33pF PCMIRQA_N/GPIO110
ALE I/O4 ALE I/O3 T16
17 32 17 32 PCMOE_N/GPIO118
R17
WE I/O3 WE I/O2 PCMREG_N/GPIO128
18 31 18 31 T18
PCM_RESET/GPIO134
WP I/O2 WP I/O1 XTAL_LOAD_22pF W16
19 30 19 30 PCMWAIT_N/GPIO105
XTAL_LOAD_27pF U15
NC_11 I/O1 NC_11 I/O0 PCMWE_N/GPIO198
R187
20 29 20 29 X101 C113 22pF XTAL_LOAD_30pF C113-*2 27pF
1M
24MHz C114 C113-*1 30pF
NC_12 NC_19 NC_12 NC_19 22pF
21 28 21 28
XTAL_LOAD_22pF XTAL_LOAD_30pF C114-*2 27pF
NC_13 NC_18 NC_13 NC_18
22 27 22 27 C114-*1 30pF
XTAL_LOAD_27pF
NC_14 NC_17 NC_14 NC_17
23 26 23 26
NC_15 NC_16 NC_15 NC_16
24 25 24 25
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
MODEL OPTION +3.3V_Normal
SOC_RESET +3.5V_ST
STby 3.5V Normal Power 3.3V DDR3 1.5V VDDC 1.05V +1.10V_VDDC
+1.10V_VDDC Normal 2.5V
MO_DVB_T2/C/S2
SWITCH_POSTEC
MO_S/W_EU/AJ
1K
1K
1K
1K
1K
1K
1K
DDR_EXT:256
DDR_EXT:128
MO_DUALSTREAM
L206
1K
SW200-*1 AVDD_NODIE
MO_S/W_AJ
BLM18PG121SN1D +1.5V_DDR VDDC : 2026mA
TMSV153BRA +3.3V_Normal VDD33
MO_M120
M1A 2.5V inbeded
MO_HD
+1.10V_VDDC
4
C289 C286 C252 +1.10V_VDDC
POWER_DET_RESET +3.5V_ST SWITCH_NAMAE 10uF 0.1uF 0.1uF AVDD_DDR0:55mA
SW200 C296 C210 C279
L204 10uF 0.1uF 0.1uF
R291
R222
R221
R206
R208
R211
R226
0.1uF
0.1uF
R290
JTP-1127WEM
0.1uF
BLM18PG121SN1D 10V
10uF
0.1uF
OPT
10V
1uF
10uF 10V85C
10uF 10V85C
0.1uF
0.1uF
0.1uF
0.1uF
10V
10V
1uF
1uF
0.1uF
R201 OPT 100 R266
IF_AGC_SEL MODEL_OPT_0 470 SWITCH L207
R202 OPT 100 R205 BLM18PG121SN1D AVDD_DMPLL
MODEL_OPT_1 100
C275
C248
C207
C254
C278
C228
1
C266
R203 OPT 100
10uF
10uF
C288 C205
C277
C280
C283
MODEL_OPT_2 C202 C200
C284
C204
10uF 0.1uF
C209
C235
C245
R204 OPT 100
C255
C259
AUD_LRCH 4.7uF 4.7uF R217
R225 OPT 100 10V 10V 0
MODEL_OPT_4 OPT
R228 OPT 100 L208 CHANGE TO AVDD_DDR1:55mA
MODEL_OPT_5 AVDD_AU33 10UF 10V X5R CHANGE TO
OPT 100 SOC_RESET BLM18PG121SN1D
R230 MODEL_OPT_6 10UF 10V X5R
R229 OPT 100 C201
AUD_LRCK R200 C240 C287 C241
470K 0.1uF
DDR_EXT:128 or NON
DDR_EXT:256 or NON
0.1uF 10uF 0.1uF
MO_DUALSTREAM_NON
MO_S/W_NON_AJ
1K
1K
1K
1K
1K
1K
MO_S/W_TW/CN
1K
1K
MO_M120_NON
MO_DVB_T/C
MO_FHD
R212
R294
R293
R224
R223
R207
R209
R227
M1A_256M M1A_128M
M1A_128M IC101 IC101-*1
IC101-*1 LGE2132(M1A_256M) LGE2131(M1A_128M)
LGE2131(M1A_128M)
MODEL OPTION AVDD_AU33
R4 U3
AUVRM R4 U3
AVDD_AU33 AUVRM
PIN NAME PIN NO. LOW HIGH M4 T6 L11 A6 L11
AVDD_AU33 AUVRM
A6
ARC0 CVBSOUT1 AVDD_DDR0_CLK GND_1 AVDD_DDR0_CLK GND_1
W7 V5 L13 A13 L13 A13
MODEL_OPT_0 J5 MO_FHD MO_HD RXC0N CVBS0 M11
AVDD_DDR1_CLK GND_2
A15 AVDD_DDR1_CLK GND_2
Y8 U5 M11 A15
RXC0P CVBS1 AVDD_DDR0_CMD GND_3 AVDD_DDR0_CMD GND_3
T5 K13 A18 K13
MODEL_OPT_1 H19 MO_S/W_NON_AJ MO_S/W_AJ W8
RXC1N CVBS2 AVDD_DDR1_CMD GND_4 AVDD_DDR1_CMD GND_4
A18
Y9 V4 +1.5V_DDR C5 B12 C5 B12
RXC1P VCOM AVDD_DDR0_D_1 GND_5 AVDD_DDR0_D_1 GND_5
K12 B14
MODEL_OPT_2 G20 MO_DVB_T/C MO_DVB_T2/C/S2 AA9 AVDD_DDR0_D_2 GND_6
K12 B14
RXC2N L12 B16 AVDD_DDR0_D_2 GND_6
W9 E4 L12 B16
RXC2P I2S_OUT_BCK/GPIO165 AVDD_DDR0_D_3 GND_7 AVDD_DDR0_D_3 GND_7
AUD_LRCH G19 MO_M120_NON MO_M120 AA7 F4 C6 B17 C6 B17
RXCCKN I2S_OUT_MCK/GPIO163 AVDD_DDR1_D_1 GND_8 AVDD_DDR1_D_1 GND_8
Y7 F7 K14 B19 K14 B19
MODEL_OPT_4 AVDD_DDR1_D_2 GND_9
U6 DDR_EXT:256 or NON DDR_EXT : 128 N2
RXCCKP I2S_OUT_SD/GPIO166
F5 L14 B20 L14
AVDD_DDR1_D_2 GND_9
B20
CEC/GPIO6 I2S_OUT_WS/GPIO164 AVDD_DDR1_D_3 GND_10 AVDD_DDR1_D_3 GND_10
E3 B5 C9 B5 C9
MODEL_OPT_5 K5 MO_S/W_TW/CN MO_S/W_EU/AJ DDCDA_CK/GPIO27 B6
AVDD_DRAM_1 GND_11
C10 AVDD_DRAM_1 GND_11
E2 C4 B6 C10
DDCDA_DA/GPIO28 USB0_DM AVDD_DRAM_2 GND_12 AVDD_DRAM_2 GND_12
W6 Y12 R8 C21 R8 C21
MODEL_OPT_6 K4 DDR_EXT:128 or NON DDR_EXT : 256 DDCDC_CK/GPIO31 USB1_DM
AVDD_NODIE AVDD_DVI_USB_MPLL_1 GND_13 AVDD_DVI_USB_MPLL_1 GND_13
AA6 B4 R9 D9 R9 D9
DDCDC_DA/GPIO32 USB0_DP AVDD_DVI_USB_MPLL_2 GND_14 AVDD_DVI_USB_MPLL_2 GND_14
L4 AA12 L7 E20 L7 E20
AUD_LRCK L5 MO_DUALSTREAM_NON
MO_DUALSTREAM HOTPLUGA/GPIO23 USB1_DP
VDD33 AVDD_MOD_1 GND_15 AVDD_MOD_1 GND_15
Y6 L8 F9 L8 F9
HOTPLUGC/GPIO25 AVDD_MOD_2 GND_16 AVDD_MOD_2 GND_16
F1 J2 P8 F11 P8 F11
* Dual Stream is only Korea 3D spec RXA0N BIN0M
AVDD_NODIE AVDD_NODIE GND_17 AVDD_NODIE GND_17
G3 J3 K9 F13 K9 F13
VDD33 AVDD_PLL GND_18
RXA0P BIN0P R5 F15 AVDD_PLL GND_18
G1 K3 AVDD_DMPLL R5 F15
RXA1N GIN0M AVDD3P3_DMPLL GND_19 AVDD3P3_DMPLL GND_19
Memory OPTION G2
H3
RXA1P GIN0P
J1
K2
+1.10V_VDDC
+1.10V_VDDC
P11
C7
AVDDL_MOD
DVDD_DDR_1
GND_20
GND_21
F17
F19
P11
C7
AVDDL_MOD GND_20
F17
F19
RXA2N RIN0M M13 F21 DVDD_DDR_1 GND_21
Memory Auto H2 K1 M13 F21
MODEL_OPT_4 MODEL_OPT_6 RXA2P RIN0P 1uFC260 R6
DVDD_DDR_2 GND_22
G8 DVDD_DDR_2 GND_22
INT+EXT Det F3 M6 DVDD_NODIE GND_23
R6 G8
RXACKN HSYNC0 A7 G9 DVDD_NODIE GND_23
F2 L6 A7 G9
128M Only 0 0 0 RXACKP VSYNC0 M12
DVDD_RX_1_1 GND_24
G10 DVDD_RX_1_1 GND_24
M12 G10
DVDD_RX_1_2 GND_25 DVDD_RX_1_2 GND_25
U4 L2 B7 G11 B7 G11
256M Only 1 0 0 EAR_OUTL BIN1M M14
DVDD_RX_2_1 GND_26
G12 DVDD_RX_2_1 GND_26
T4 L3 M14 G12
EAR_OUTR BIN1P DVDD_RX_2_2 GND_27 DVDD_RX_2_2 GND_27
P2 M1 N11 G13 N11 G13
128M+128M 0 1 0 AUL1 GIN1M +1.10V_VDDC VDDC_1 GND_28 VDDC_1 GND_28
R2 M2 N12 G14 N12 G14
AUL2 GIN1P VDDC_2 GND_29 VDDC_2 GND_29
T1 N1 N13 G15 N13 G15
128M+256M 0 0 1 AUL3 RIN1M N14
VDDC_3 GND_30
G16 VDDC_3 GND_30
R3 N3 N14 G16
AUR1 RIN1P VDDC_4 GND_31 VDDC_4 GND_31
R1 M3 N15 G17 N15 G17
256M+256M 1 0 1 AUR2 SOGIN1 P12
VDDC_5 GND_32
G18 VDDC_5 GND_32
T3 P12 G18
AUR3 VDDC_6 GND_33 VDDC_6 GND_33
U2 P13 H7 P13 H7
AUOUTL0 VDDC_7 GND_34 VDDC_7 GND_34
V3 P14 H8 P14 H8
AUOUTR0 VDDC_8 GND_35 VDDC_8 GND_35
L9 H9
Country Option T2
AUVAG
VDD33
AA10
VDDP GND_36
GND_37
H10
H11
L9
VDDP GND_36
GND_37
H9
H10
AA10 H11
AVDD5V_MHL AVDD5V_MHL GND_38
MODEL_OPT_1 MODEL_OPT_5 H12 AVDD5V_MHL GND_38
H12
GND_39 GND_39
H13 H13
GND_40 GND_40
TW 0 0 H14 H14
GND_41 GND_41
H15 H15
M1A_256M GND_42 GND_42
H16 H16
EU 0 1 IC101 GND_43
H17 GND_43
H17
LGE2132(M1A_256M) GND_44
H18 GND_44
H18
GND_45 GND_45
CN 1 0 J7 J7
GND_46 GND_46
J8 J8
C212 GND_47 GND_47
HDMI1_ARC HDMI1_ARC M4 T6 J9 J9
HDMI
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
AUDIO AMP(TI)
AMP_COIL_GET AMP_COIL_GET AMP_COIL_GET AMP_COIL_GET
L5603-*1 L5604-*1 L5605-*1 L5606-*1
10.0uH 10.0uH 10.0uH 10.0uH
+24V +24V_AMP
This parts are Located
on AVSS area.
R5610
L5600
470
UBW2012-121F
C5611 4700pF
AMP_COIL_ABCO Close to Speaker
0.047uF
C5612
L5605
C5601 10uH
0.1uF
C5613 2200pF
SPK_L+
0.033uF
50V
C5616
50V
R5611
C5609 4700pF +24V_AMP 18
50V
C5608 R5609 C5626 OPT
330pF C5632 C5636
0.047uF 470 C5640 50V 0.1uF 2200pF
C5618 C5620
0.1uF 10uF 4.7uF 50V 50V
3 PVDD_AB_2
2 PVDD_AB_1
11 PLL_FLTP
35V
10 PLL_FLTM
+3.3V_Normal 50V 50V
SSTIMER
3216 C5630
12 VR_ANA
BST_A
1 OUT_A
0.47uF
NC_2
NC_1
PBTL
OPT
9 AVSS
C5627
50V
C5633
C5637 SPEAKER_L
330pF 2200pF
0.1uF 50V
[EP] 50V
8
7
6
5
4
50V
AVDD 13 48 PGND_AB_2 R5612
+3.5V_ST 18
THERMAL
C5604 R5608 2K A_SEL_FAULT 14 47 PGND_AB_1
0.1uF MCLK OUT_B
46
49
16V 15 SPK_L-
18K OSC_RES NC_6
16 45 50V L5606
TAS5733
IC5600
R5601 R5607 1% DVSSO 17 44 NC_5 0.033uF 10uH
10K VR_DIG BST_B C5624
AUD_MASTER_CLK 18 43 AMP_COIL_ABCO
R5603 PDN BST_C
19 42
C 100 LRCLK 20 41 NC_4 AMP_COIL_ABCO
OPT C5602 50V
OPT SCLK 40 NC_3 L5604
R5600 B 1000pF C5607 21 0.033uF 10uH
AMP_MUTE Q5600 50V SDIN OUT_C
0.1uF 22 39 C5625
10K MMBT3904(NXP) SPK_R+
SDA 23 38 PGND_CD_2
E
SCL PGND_CD_1 OPT SPEAKER_R
1/16W
R5613
24 37
C5634 C5638
C5631
25
26
27
28
29
30
31
32
33
34
35
36
0.1uF 2200pF
18
AUD_LRCK
OPT 0.47uF 50V
AUD_SCK 50V 50V
DVDD
AGND
GND
GVDD_OUT
R3405
VREG
OUT_D
DVSS
PVDD_CD_1
PVDD_CD_2
RESET
BST_D
STEST
0 AUD_LRCH C5628
OPT
POWER_DET AMP_SDA 330pF C5639
+24V_AMP 50V 2200pF
AMP_SCL C5635
0.1uF 50V
C5629 50V
C5614
1/16W
R5614
50V 35V 50V
3216
18
C5606 SPK_R-
ZD5600
10uH
OPT
C5610 AMP_COIL_ABCO
0.1uF
16V
WAFER-ANGLE
SPK_L+
4
SPK_L-
3
SPK_R+
2
SPK_R-
1
P5600
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
RGB/RS232C (RGB/SCART Switch from EAX65377501)
DSUB/SCART Switch
+5V_Normal
OPT OPT
IC3102 C3103 C3122 C3104
0.1uF 22uF 22uF
BA7657F 10V 10V
R3113 470K
GREEN_1_INUT HD_OUTPUT
3 22 DSUB/SC1_HSYNC
C3102
SC1_G+ 6.3V
22uF R3110
C3114 GROUND1 RED_OUTPUT 75 C3125
0.01uF 4 21 0.01uF DSUB/SC1_R+
25V 25V
BLUE_1_INPUT VCC
5 20
C3135 R3108 R3120
SC1_B+ 6.3V
22uF 68K 2K R3115
GROUND2 GREEN_OUTPUT 75 C3101
C3128 6 19 0.01uF DSUB/SC1_G+
0.01uF 25V
25V
RED_2_INPUT COMPOSITE_VIDEO_INPUT
7 18
C3126
DSUB_R+ 6.3V GROUND3 COMPOSITE_SYNC_OUTPUT
22uF 8 17
C3136 DSUB/SC1_OUT_CTRL
0.01uF R3119
25V GREEN_2_INPUT CONTROL 22
9 16
SCART Low
C3116 R3102
0.01uF GROUND4 BLUE_OUTPUT 75 C3110
DSUB_G+ 25V 10 15 0.01uF
25V DSUB/SC1_B+
C3117 RGB High
6.3V
22uF BLUE_2_INPUT VD_OUTPUT
11 14 DSUB/SC1_VSYNC
VD_1_INPUT VD_2_INPUT
SC1_FB 12 13 DSUB_VSYNC
C3130
DSUB_B+ 0.01uF
25V
C3107
6.3V
RGB PC 22uF
+3.5V_ST
+5V_Normal
RGB_PC
D3112
MMBD6100
A2 R3121
C 10K
A1
R3122
DSUB/SC1_OUT_CTRL Q3101
RGB_PC RGB_PC NON_CI_CAP_RGB_PC 4.7K
C3109 MMBT3904(NXP)
R3111 0.1uF
R3106 16V
2.2K
2.2K
RGB_DDC_SCL
NON_CI_CAP_RGB_PC
RGB_DDC_SDA
NON_CI_CAP_RGB_PC
C3105 C3106
18pF 18pF
50V 50V
DSUB_VSYNC
DSUB_HSYNC
OPT OPT
OPT OPT OPT VA3110
C3124 C3118
R3109 R3114 VA3101 68pF VA3104 5.6V
68pF 20V 20V
2.4K 10K 50V 50V
ADUC 20S 02 010L ADUC 20S 02 010L
OPT
R3801-*1
0
VA3111
5.6V RS232C
NON_EMI_RGB 10
L3801
DSUB_B+ EMI_RGB 5
ADUC 20S 02 010L BLM15BD121SN1 9
OPT RGB_PC RGB_VARISTOR
C3800R3118 VA3106 IR_OUT 4
75 20V
47pF
50V R3117 8
100
3
R3802-*1 7
0 R3104
+3.5V_ST 100
NON_EMI_RGB
2
L3802
EMI_RGB
DSUB_G+ 6
D3107 D3103
OPT ADUC 20S 02 010L BLM15BD121SN1 CDS3C30GTH CDS3C30GTH
RGB_PC +3.3V_Normal 30V 30V 1
C3802 RGB_VARISTOR
47pFR3101
75
VA3108 OPT OPT
50V 20V
RGB_PC C3108 0 . 3 3 u F
R3103 SPG09-DB-009
10K RGB_PC
R3105 IC3101 JK3101
C3113
R3800-*1 1K MAX3232CDR 0.1uF
0 DSUB_DET +3.5V_ST
NON_EMI_RGB
L3800 C1+ VCC
EMI_RGB OPT 1 16 D3109
DSUB_R+
VA3102 BAP70-02 R3112
ADUC 20S 02 010L
BLM15BD121SN1 5.6V C3127 1K
RGB_PC RGB_VARISTOR 0.1uF V+ GND
C3801 ADMC 5M 02 200L
VA3105 2 15 50V
47pF R3107 20V
50V 75 C3119
0.1uF C1- DOUT1
OPT 3 14
GREEN_GND
DDC_CLOCK
DDC_DATA
SYNC_GND
BLUE_GND
DDC_GND
RED_GND
C2+ RIN1
H_SYNC
V_SYNC
4 13
GREEN
GND_2
GND_1
BLUE
C3120
RED
NC
V- DIN1
SHILED
6 11
11
12
13
14
15
PM_TXD
C3121
0 . 1 u FDOUT2 DIN2
7 10
16
10
6
RIN2 ROUT2
8 9
1
EAN41348201
JK3102
SPG09-DB-010
RGB_PC
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_Normal
MHL_SW_AND_GATE
IC5801
74LVC1G08GW
B VCC
1 5
MHL_CD_SENSE
A
2
MHL_OCP_EN
GND Y
3 4
MHL_5V_EN
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
ETHERNET
* H/W option : ETHERNET
JK2100
RJ45VT-01SN002
1
1
EPHY_TP
ETHERNET
2
2
3
3
EPHY_TN
4
4
EPHY_RP
5
5
6
6
EPHY_RN
7
7
8
8
ETHERNET ETHERNET
C2605 C2606
0.01uF 0.01uF
50V 50V
Copyright © 2014 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
4 Color error 5
* First of all, Check whether there is SVC Bulletin in GCSC System for these model.
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable, Speaker Cable, IR B/D Cable,,,)
☞A1 ☞A4
Y Y Check Power Y
No video Normal Check Back Light Normal Replace T-con
On Board
Normal audio Audio On with naked eye Voltage Board or module
3.5V, 12V, 24V etc.
N N N
☞A2
Established
Error A. Video error date 2012 . 01 .14
LCD TV symptom
No video/ No audio Revised date 2/14
☞A4
Check various Check and
No Video/ Normal Y
voltages of Power replace
No audio Voltage
Board ( 3.5V,12V, 24V) MAIN B/D
N End
Replace Power
Board and repair
parts
Established
Error A. Video error date 2012. 01 .14
LCD TV symptom
Picture broken/ Freezing Revised date 3/14
N
☞ A6
Check RF Cable
Connection Normal Y Check SVC N Check Normal Y
End
1. Reconnection Picture S/W Version Bulletin Tuner soldering Picture
2. Install Booster
N Y N
Normal N
End
Picture
End
Established
Error A. Video error date 2012. 01 .14
LCD TV symptom
Tuning fail, Picture broken/ Freezing Revised date 4/14
Normal N Normal N
Picture Picture
End Y Y
End End
Established
Error A. Video error date 2012. 01 .14
LCD TV symptom
Color error Revised date 5/14
☞ A8/ A9
☞A7
※ Check and Y
Check color by input
replace Link Y
-External Input Y
Color Cable Color Color
-COMPONENT Replace Main B/D Replace module
error (LVDS) and error error
-RGB
contact
-HDMI/DVI N N N
condition
Request repair
for external
device/cable
N
External Y
Check external
HDMI device/
device and Replace Main B/D
error Cable
cable
Normal
Established
Error B. Power error date 2012. 01 .14
LCD TV symptom
No power Revised date 7/14
☞A11 ☞A13
DC Power on Normal Replace
Check Power Y N Check Power Y
by pressing Power Key Operati OK Power
Power LED LED On On ‘”High”
On Remote control on B/D
Stand-By : Red N Y
N
Normal Y
☞A12
※ Normal Normal Y
Y Check ST-BY 3.5V Replace Main B/D
Voltage Voltage
N N
End
Established
Error B. Power error date 2012. 01 .14
LCD TV symptom
Off when on, off while viewing, power auto on/off Revised date 8/14
Check outlet
☞A14
CPU Y
N Check Power Off
Check A/C cord Error Abnorm Replace Main B/D Normal End
Mode
al
Y N
Check for all 3- phase Abnorm
power out al1 Replace Power B/D
☞A13
* Please refer to the all cases which Status Power off List Explanation
can be displayed on power off mode. "POWEROFF_REMOTEKEY" Power off by REMOTE CONTROL
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
Normal "POWEROFF_ONTIMER" Power off by ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF_UNKNOWN" Power off by unknown status except listed case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
Copyright © 2014 LG Electronics. Inc. All rights reserved.
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
Only for training and service purposes LGE Internal Use Only
Standard Repair Process
Established
Error C. Audio error date 2012. 01 .14
LCD TV symptom
No audio/ Normal video Revised date 9/14
☞A15 ☞A16
Check
Disconn N
Speaker Replace MAIN Board End
ection
disconnection
Y
Replace Speaker
Established
Error C. Audio error date 2012. 01 .14
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 10/14
Wrecked Audio/
Discontinuation/ Replace Power B/D
Noise only for Analog
Wrecked Audio/
Connect and check
Discontinuation/
other external Replace Main B/D End
Noise only for
device
External Input
(When RF signal is not
received) N
Normal
Request repair to external Audio
cable/ANT provider
Y
(In case of
External Input
signal error) Check and fix external device
Check and fix
external device
☞A17 Y
☞A17 ☞A17
Y Check & Repair
Check R/C itself Normal Normal N Check B+ 3.5V Normal Y Check IR Normal
Cable connection
Operation Operating Operating On Main B/D Voltage Output signal Signal
Connector solder
N Y N N
☞A4
Check R/C Operating Check & Replace Check 3.5v on Power B/D Repair/Replace
End
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal Y
Explain the customer End
Operating
cause is interference
from light in room. N
Replace R/C
Established
Error D. Function error date 2012. 01 .14
LCD TV symptom
External device recognition error Revised date 12/14
Check technical
Check Y Technical N External Input
Signal information
input information and Component Replace Main B/D
Input - Fix information
signal Recognition error
- S/W Version
N Y
Fix in
Check and fix accordance HDMI, Optical Replace Main B/D
external device/cable with technical Recognition error
information
Established
Error E. Noise date 2012. 01 .14
LCD TV symptom
Circuit noise, mechanical noise Revised date 13/14
※ Mechanical noise is a natural ※ When the nose is severe, replace the module
phenomenon, and apply the 1st level (For models with fix information, upgrade the S/W or
description. When the customer does not provide the description)
agree, apply the process by stage.
OR
※ Describe the basis of the description in ※ If there is a “Tak Tak” noise from the cabinet,
“Part related to nose” in the Owner’s Manual. refer to the KMS fix information and then proceed
as shown in the solution manual
(For models without any fix information, provide
the description)
Established
Error F. Exterior defect date 2012. 01 .14
LCD TV symptom
Exterior defect Revised date 14/14
Cabinet
Replace cabinet
damage
Remote
Controller Replace remote controller
damage
Stand
Replace stand
damage
25
B. Power error_Off when on, off while
26 POWER OFF MODE checking method A14
viewing
Checking method in menu when there is no
28 A15
audio
C. Audio error_No audio/Normal video
Voltage and speaker checking method when
29 A16
there is no audio
C. Audio error_Wrecked Voltage and speaker checking method in
30 A16
audio/discontinuation case of audio error
D. Function error_ No response in
31 Remote controller operation checking method A17
remote controller, key error
<ALL MODELS>
<ALL MODELS>
Entry
Entry method
method
1.
1. Press
Press the
the ADJ
ADJ button
button on
on the
the remote
remote controller
controller for
for adjustment.
adjustment.
2.
2. Enter
Enter into
into White
White Balance
Balance of
of item
item 6.
7.
3. After
3. After recording
recording the
the R,
R, G,
G, B
B (GAIN,
(GAIN, Cut)
Cut) value
value of
of Color
Color Temp
Temp (Cool/Medium/Warm),
(Cool/Medium/Warm), re-
re-
enter the value after replacing the MAIN BOARD.
enter the value after replacing the MAIN BOARD.
SMAW200-H18S5
1 Power on 2 DRV ON
3 3.5V 4 PDIM#1
5 3.5V 6 3.5V
7 GND 8 PDIM#2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 NC
17 GND 18 GND
Version
<ALL MODELS>
<ALL MODELS>
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes LGE Internal Use Only
Appendix : Exchange T-Con Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
No picture/Sound Ok
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Un-repairable Cases
In this case please exchange the module.
Press damage
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes LGE Internal Use Only
Appendix : Exchange the Module (2)
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
SMAW200-H18S5
1 Power on 2 DRV ON
3 3.5V 4 PDIM#1
5 3.5V 6 3.5V
7 GND 8 PDIM#2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 NC
17 GND 18 GND
SMAW200-H18S5
1 Power on 2 DRV ON
3 3.5V 4 PDIM#1
5 3.5V 6 3.5V
7 GND 8 PDIM#2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 NC
17 GND 18 GND
<ALL MODELS>
Checking order
<ALL MODELS>
Checking order
1. Press the MENU button on the remote controller
2. Select the AUDIO function of the Menu
3. Select TV Speaker Check
<ALL MODELS>
② SMAW200-H18S5
①
1 Power on 2 DRV ON
3 3.5V 4 PDIM#1
5 3.5V 6 3.5V
7 GND 8 PDIM#2
9 24V 10 24V
11 GND 12 GND
13 12V 14 12V
15 12V 16 NC ③
17 GND 18 GND
< Main Ass’y>
Checking order
1. Check the contact condition of or 24V connector of Main Board
2. Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
3. Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound
when you touch the GND and output terminal, the speaker is normal.
<ALL MODELS>
P4600
1 GND
2 KEY1
3 KEY2
③
4 3.5V_ST
5 GND
6 LED_R
④ 7 IR
② 8 GND
① < Sub Ass’y>
9 SCL
10 SDA
Checking order
1, 2. Check IR cable condition between IR & Main board.
3. Check the st-by 3.3V on the terminal 4.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the Analog
Tester needle moves slowly, and defective when it does not move at all.