PUBLIC

EXHIBIT 33
 U.S. Patent No. 10,049,080
Samsung / Qualcomm Product
 U.S. Patent No. 10,049,080
1(pre). A multi-core processor comprising:
1(pre). A multi-core processor comprising: The Samsung S21 FE 5G smartphone, semiconductor devices incorporated in the same, and Qualcomm
components thereof (hereinafter, the “Samsung / Qualcomm Product”) includes a multi-core processor.

See Ex. 72 at 2, Samsung Galaxy S21 FE 5G Fan Edition Samsung US,

https://www.samsung.com/us/smartphones/galaxy-s21-5g/galaxy-s21-fe-5g/.

For example, the Samsung / Qualcomm Product includes the Qualcomm Snapdragon 888 5G system on
chip (the “Qualcomm SoC”).

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 U.S. Patent No. 10,049,080: Claim 1(pre)
“A multi-core processor comprising:”

See Ex. 152 at 7, Photographs for the Samsung Qualcomm Representative Article - Samsung Galaxy S21
FE 5G, Samsung Galaxy S21 FE 5G - About Phone.

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 U.S. Patent No. 10,049,080: Claim 1(pre)
“A multi-core processor comprising:”
See Ex. 152 at 7, Photographs for the Samsung Qualcomm Representative Article - Samsung Galaxy S21
FE 5G, Samsung Galaxy S21 FE - SoC Model.

See Ex. 73 at 1, Qualcomm, Samsung Galaxy S21 Fan Edition 5G, Powered by Snapdragon 888 Mobile
Platform, https://www.qualcomm.com/snapdragon/smartphones/samsung-galaxy-s21-fan-edition-5g.

Upon information and belief, the Qualcomm SoC is layered beneath the Samsung K3LK2K20CM-BGCP
RAM.

See Ex. 152 at 8, Photographs for the Samsung/Qualcomm Representative Article.

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 U.S. Patent No. 10,049,080: Claim 1(pre)
“A multi-core processor comprising:”

The Qualcomm SoC includes a Kryo 680 central processing unit (CPU).

See Ex. 75 at 2, Qualcomm Snapdragon 888 5G mobile platform Product Brief,

https://www.qualcomm.com/system/files/document/files/prod_brief_qcom_sd888_5g_1_0.pdf.

See Ex. 76 at 2, Qualcomm's New Snapdragon 888 Brings Built-In 5G to Android Phones – IGN,
https://www.ign.com/articles/qualcomm-snapdragon-888-mobile-processor-android-smartphone.

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 U.S. Patent No. 10,049,080: Claim 1(pre)
“A multi-core processor comprising:”
The Kryo 680 CPU is built on ARM Cortex technology and includes multiple processor cores including
an ARM Cortex-X1 core, three ARM Cortex-A78 cores, and four ARM Cortex-A55 cores (collectively,
the “ARM Cores”).

See Ex. 77 at 6, AnandTech, Qualcomm Details The Snapdragon 888:3rd Gen 5G & Cortex-X1 on 5nm,
https://www.anandtech.com/show/16271/qualcomm-snapdragon-888-deep-dive; see also Ex. 147 at 3,
NanoReview, Qualcomm Snapdragon 888, https://nanoreview.net/en/soc/qualcomm-snapdragon-875.

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 U.S. Patent No. 10,049,080: Claim 1(pre)
“A multi-core processor comprising:”

See Ex. 22 at 9, Photographs of Samsung Galaxy S21 FE - SoC Model.

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 U.S. Patent No. 10,049,080
1(a). a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power,
for a same applied operating frequency and supply voltage, than the first plurality of cores; and
1(a). a first plurality of cores and a second The Samsung / Qualcomm Product includes a first plurality of cores and a second plurality of cores that
plurality of cores that support a same support a same instruction set, wherein the second plurality of cores consume less power, for a same applied
instruction set, wherein the second plurality operating frequency and supply voltage, than the first plurality of cores.
of cores consume less power, for a same
applied operating frequency and supply The Samsung / Qualcomm Product includes a first plurality of cores and a second plurality of cores that
voltage, than the first plurality of cores; and support a same instruction set. For example, the ARM Cores all implement the Armv8-A architecture and
support A64, A32 and T32 instruction sets.

See Ex. 78 at A2-38, Arm Cortex-X1 Core Technical Reference Manual, rev. r1p1,
https://developer.arm.com/documentation/101433/0101/Functional-description/Introduction/About-the-
core.

See Ex. 79 at 1-2, Cortex-A78, arm Developer, https://developer.arm.com/ip-products/processors/cortex-

a/cortex-a78.

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 80 at 1-2, Cortex-A55, arm Developer, https://developer.arm.com/ip-products/processors/cortex-

a/cortex-a55.

The Qualcomm SoC supports ARM DynamIQ big.LITTLE, which combines high-performance cores and
power-efficient cores to form a single, fully integrated CPU cluster.

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 81 at A1-20, Arm DynamIQ Shared Unit Technical Reference Manual, rev. r4p1,
https://documentation-service.arm.com/static/5e7e1bd8b2608e4d7f0a35b4?token=.

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 122 at 7, What is the big.LITTLE Architecture?, https://www.makeuseof.com/what-is-the-biglittle-

architecture/.

See Ex. 122 at 8, What is the big.LITTLE Architecture?, https://www.makeuseof.com/what-is-the-biglittle-

architecture/.

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 82 at 2, Arm DynamIQ_ Expanding the possibilities for AI - Architectures and Processors blog -
Arm Community blogs - Arm Community, https://community.arm.com/arm-community-
blogs/b/architectures-and-processors-blog/posts/arm-dynamiq-expanding-the-possibilities-for-artificial-
intelligence?_ga=2.61319980.1068846407.1641581924-107082491.1634835893.

See Ex. 83 at 2-3, Where does big.LITTLE fit in the world of DynamIQ_ - Architectures and Processors
blog - Arm Community blogs - Arm Community, https://community.arm.com/arm-community-
blogs/b/architectures-and-processors-blog/posts/where-does-big-little-fit-in-the-world-of-dynamiq.

Further, big cores and LITTLE cores in the DynamIQ big.LITTLE system share the same instruction set
architecture (ISA).

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 84 at 16-2, ARM Cortex-A Series Programmer’s Guide for Armv8-A, ver. 1,
https://developer.arm.com/documentation/den0024/a.

The second plurality of cores consume less power for a same applied operating frequency and supply
voltage than the first plurality of cores. For example, the Cortex-A55 cores are the power-efficient
“LITTLE” cores and Cortex-A78 and Cortex-X1 cores are the high-performance “big” cores in the ARM
DynamIQ big.LITTLE system.

See Ex. 122 at 8, What is the big.LITTLE Architecture?, https://www.makeuseof.com/what-is-the-biglittle-

architecture/.

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 U.S. Patent No. 10,049,080: Claim 1 (a)
“a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a
same applied operating frequency and supply voltage, than the first plurality of cores; and”

See Ex. 85 at 2, Developers, Balancing performance and power consumption with big.LITTLE,
https://www.qualcomm.com/news/onq/2018/06/11/balancing-performance-and-power-consumption-
biglittle.

“LITTLE cores are built using a completely different microarchitecture than the big cores, so the LITTLE
cores save power by the nature of their simpler design.”

See Ex. 86 at 5, Ten Things to Know About big.LITTLE - Architectures and Processors blog,
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/ten-things-
to-know-about-big-little.

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 U.S. Patent No. 10,049,080
1(b). power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first
plurality of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on
the multi-core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.
1(b). power management hardware to, from The Samsung / Qualcomm Product includes power management hardware to, from a state where the first
a state where the first plurality of cores and plurality of cores and the second plurality of cores are enabled, disable all of the first plurality of cores for
the second plurality of cores are enabled, a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an
disable all of the first plurality of cores for a operating system to execute on the multi-core processor is to monitor a demand for the multi-core processor
drop in demand below a threshold without and control the power management hardware based on the demand.
disabling any of the second plurality of
cores, wherein an operating system to For example, the Qualcomm SoC includes a resource and power manager, including the following key
execute on the multi-core processor is to blocks: “RPM [(Resource Power Manager)] core, Cortex M3, security controller, MPM [(Master Power
monitor a demand for the multi-core Management)].”
processor and control the power
management hardware based on the
demand.

See Ex. 87 at 20, Qualcomm Snapdragon 820E Processor (APQ8096SGE) Device Specification,
https://developer.qualcomm.com/qfile/35457/lm80-p2751-1_e.pdf1

1
Upon information and belief, Qualcomm Snapdragon 8 series processors, including Qualcomm Snapdragon 820E processor and the Qualcomm SoC include substantially similar power
management solution.
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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 87 at 13, Qualcomm Snapdragon 820E Processor (APQ8096SGE) Device Specification,
https://developer.qualcomm.com/qfile/35457/lm80-p2751-1_e.pdf.

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 88 at 6, Resource Power Manager, API Reference, LM80-P0436-74 Rev. A, ,

https://developer.qualcomm.com/qfile/35417/lm80-p0436-
74_a_resource_power_manager_api_reference.pdf.

The RPM system is “[t]he only master of the APQ power management (MPM),” which “coordinates the
shutdown/wakeup, clock rates, and VDDs.”

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 87 at 17, Qualcomm Snapdragon 820E Processor (APQ8096SGE) Device Specification,
https://developer.qualcomm.com/qfile/35457/lm80-p2751-1_e.pdf.

The Qualcomm SoC uses an advanced form of RPM, called RPM-hardened (RPMH). The new architecture,
RPM-hardened (RPMH), “uses h/w (hardened I/P) blocks for aggregating requests and applying the result
on the resource. The resources could be clocks, regulators or bandwidth requests for buses.”

See Ex. 89 at 1, drivers/qcom: add RPMH communication support, https://lwn.net/Articles/748981/.2

2
Upon information and belief, Qualcomm Snapdragon 8 series processors, including Qualcomm Snapdragon 845 (SDM845) and the Qualcomm SoC include substantially similar power
management solution.
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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 90 at 1, QCOM, SDM845,

https://www.kernel.org/doc/Documentation/devicetree/bindings/interconnect/qcom%2Csdm845.yaml.

Further, the Qualcomm SoC uses the CPUFreq framework for the CPU cores, which includes an on-demand
governor to “adjust the [CPU] frequency proportional to load[.]”

See Ex. 92, SM-G990U1_NA_12_Opensource.zip (Version: G990U1UEU2BUL8), available at

https://opensource.samsung.com/uploadList?menuItem=mobile&classification1=mobile_phone, SM-
G990U1_NA_12_Opensource\Kernel.tar.gz\Kernel.tar\.\drivers\cpufreq\cpufreq_ondemand.c at ll. 129-
140.

Additionally, the Qualcomm SoC includes a task scheduler to “allocate or migrate tasks to specific cores.”
The task scheduler has “key knowledge and sophisticated analytics about the demands being made by each
task (e.g. threads)” and can “idle unused cores[.]”

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 91 at 3, The Impact of Big Core & Little Core Architecture on Application Development,
https://developer.qualcomm.com/blog/impact-big-core-little-core-architecture-application-development.

The Qualcomm SoC includes a task scheduler that can perform global task scheduling (GTS) – “all physical
cores are available all of the time, and global task scheduler allocates tasks on a per-core basis depending
on demands.” “This is the optimal method because the OS scheduler can allocate work on any core, all
cores, or any combination, which unused cores are automatically turned off.”

See Ex. 91 at 3, The Impact of Big Core & Little Core Architecture on Application
Development,https://developer.qualcomm.com/blog/impact-big-core-little-core-architecture-application-
development.

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 85 at 3, Developers: Balancing performance and power consumption with big.LITTLE,
https://www.qualcomm.com/news/onq/2018/06/11/balancing-performance-and-power-consumption-
biglittle.

See Ex. 86 at 3, Ten Things to Know About big.LITTLE - Architectures and Processors blog,
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/ten-things-
to-know-about-big-little.

The operating system task scheduler is “aware of the differences in compute capacity between big and
LITTLE cores.” The scheduler “tracks the performance requirement for each individual software
thread…to decide which type of core to use for each.”

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 84 at 16-4, ARM Cortex-A Series Programmer’s Guide for Armv8-A, Ver. 1,
https://developer.arm.com/documentation/den0024/a.

See Ex. 84 at 16-5, 16-6, ARM Cortex-A Series Programmer’s Guide for Armv8-A, Ver. 1,
https://developer.arm.com/documentation/den0024/a.

In addition, GTS enables software to “run on big or the LITTLE processors (or both) depending on
performance requirements.”

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 84 at 16-1, 16-6, ARM Cortex-A Series Programmer’s Guide for Armv8-A, Ver. 1,
https://developer.arm.com/documentation/den0024/a.

“As a general rule of thumb, a good approach is to run on little cores if possible because that can reduce
both heat and power consumption.”

See Ex. 91 at 3, The Impact of Big Core & Little Core Architecture on Application Development,
https://developer.qualcomm.com/blog/impact-big-core-little-core-architecture-application-development.

Further, the ARM Cores support “hotplug” which can disable the ARM Cores.

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 U.S. Patent No. 10,049,080: Claim 1(b)
“power management hardware to, from a state where the first plurality of cores and the second plurality of cores are enabled, disable all of the first plurality
of cores for a drop in demand below a threshold without disabling any of the second plurality of cores, wherein an operating system to execute on the multi-
core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand.”

See Ex. 93, SM-G990U1_NA_12_Opensource.zip (Version: G990U1UEU2BUL8), available at

https://opensource.samsung.com/uploadList?menuItem=mobile&classification1=mobile_phone, SM-
G990U1_NA_12_Opensource\Kernel.tar.gz\Kernel.tar\.\arch\arm64\boot\dts\vendor\qcom\lahaina-
thermal.dtsi at ll. 121-62.

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