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Design of Depletion Type N Channel Mosfet Biasing Circuit

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Trần Minh Đức
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43 views2 pages

Design of Depletion Type N Channel Mosfet Biasing Circuit

Uploaded by

Trần Minh Đức
Copyright
© © All Rights Reserved
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DESIGN OF DEPLETION NMOS SELF BIASING CIRCUIT

Design D type MOSFET self-biasing circuit to achieve Q – Point of VDSQ, VGSQ and IDQ employing N-
channel MOSFET. Also draw neatly the designed circuit with standard component values. For NMOS D
type: Vp & IDSS will be given.

STEP 1 – Calculation of Gate Resistor (RG)

To maintain high input resistance or input impedance (Ri or Zi) gate resistor (RG) has to be kept extremely
high in order to prevent or minimize the loading effects. Hence select the nearest highest value of the gate
resistor (RG) which is RG = 1 MΩ.

STEP 2 – Calculation of Source Resistor (RS)

For the MOSFET self-biasing circuit, applying KVL in the gate-to-source loop :-

VGS   I D RS . . . . . . . . . . (1)

The gate-to-source voltage (VGS) can be easily calculated from Equation 2:-

ID = IDSS (1- VGS/VP)2 . . . . . . . . . . (2)

Calculate VGS from (2) & substitute it in (1) to obtain the value of the source resistor (RS).

STEP 3 – Calculation of Drain Resistor (RD)

Applying KVL in the drain-to-source loop:-

VDD  VDS  I D RS
RD  . . . . . . . . . . (3)
ID

Calculate RD from (3)


DESIGN OF MOSFET D TYPE VOLTAGE DIVIDER BIASING CIRCUIT

Design MOSFET voltage divider biasing circuits to achieve Q-Point of VDSQ and IDQ employing N-channel
MOSFET. Also draw neatly the designed circuit with standard component values. For NMOS D type: Vp
& IDSS will be given.

STEP 1 – Selection of Biasing Resistors (R1 & R2)

Applying the voltage divider rule at the gate terminal:-

VG = VDD R2 / (R1 +R2). . . . . . . . . . . (1)

Assume VG as typically 25 % of the DC supply voltage (+VDD) where VG = 25 % of +VDD


Assume R2 = ____ kΩ (select any standard value from 100 kΩ to 470 kΩ) hence from above equation
calculate R1 & select nearest standard value.

STEP 2 – Calculation of Source Resistor (RS)

For the MOSFET voltage divider biasing circuit, applying KVL in the gate-to-source loop:-

VGS  VG  I D RS . . . . . . . . . . (2)

The gate-to-source voltage (VGS) can be easily calculated from Equation (3):-

ID = IDSS (1- VGS/VP)2 . . . . . . . . . . (3)

Calculate VGS from (3) & substitute it in (2) to obtain the value of the source resistor (RS)

STEP 3 – Calculation of Drain Resistor (RD)

Applying KVL in the drain-to-source loop:-

VDD  VDS  I D RS
RD  . . . . . . . . . . (4)
ID
Calculate RD from (4)

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