12th International Conference on Frontiers of Information Technology

Real-Time Signal Processing Architecture and its

Implementation for Circular Sensor Arrays

Umar Hamid1, Syed Ali Abbas2

1
Institute of Communication Technologies, Islamabad, Pakistan
2
Muhammad Ali Jinnah University, Islamabad, Pakistan
[email protected], [email protected]

Abstract–This paper focuses on the design of a signal This paper presents a parallel processing system that
processing architecture and its implementation for a circular executes advanced signal processing techniques for circular or
sensor array in real-time. The processor architecture presented cylindrical bow sonar. The system comprises multiple DSP
consists of multiple ADC and DSP boards along with a host boards plugged into a host computer. The system performs data
computer. This parallel processing system includes algorithm acquisition, signal processing and display processing tasks in
mapping onto multiple DSP processors and satisfies the demands real-time.
of real-time operation. This processing architecture has been
designed and implemented for a multi-channel sensor array used
in underwater surveillance systems.
II. SENSOR ARRAY CONFIGURATION
Keywords–signal processing, sensor array, ADC, DSP, FFT,
beamforming, spectral analysis A passive circular array with uniformly spaced sensors has
been selected in this paper. This configuration is in use in many
real world systems including phased array Radars, smart
antenna systems and underwater surveillance systems. A
I. INTRODUCTION circular array provides uniform beam width when steered in
azimuth () due to its circular and symmetric nature. With a
Design and implementation of a signal processing fixed elevation angle () it provides full 360o coverage.
architecture for sensor arrays mainly depends upon sensor array
configuration that includes array geometry and its operating Figure 2 below shows uniform circular array (UCA) with N
frequency range. In addition data rates and processing load of sensors and radius r. A plane wave is incident on the array from
various signal processing algorithms involved provide an a direction denoted by elevation angle () and azimuth ().
estimation of the computational requirements so that an With fixed elevation angle (=/2), the array lies on x-y plane.
appropriate processing architecture can be selected.
Figure 1 below shows a bow sensor array in a surface ship
and a submarine. The function of each sensor array system is
different according to its installation platform, position, and
configuration.

Figure 2 Uniform Circular Array [2]

In this paper a circular array with 32 sensors has been

nominated for evaluation. The array frequency is selected as
Figure 1 Circular Sensor Array for Underwater Surveillance Systems [1] 8000 Hz. The sampling frequency is selected as 20000 Hz.

978-1-4799-7505-1/14 $31.00 © 2014 IEEE 109

DOI 10.1109/FIT.2014.29
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 III. SIGNAL PROCESSING REQUIREMENTS B. Beamforming
Figure 2 below shows the passive signal processing The processing load of 2D-FFT beamforming with array
functions for circular arrays that are responsible for target shading is given by [4]:
detection, localization and classification [3].
LOAD (T-FFT) = N x M x [log2 (M) + 1] (2)
LOAD (S-FFT) = 2 x M x N1 x [log2 (N1) + 2] (3)
The circularity of the sensors means that the incident wave
is non-uniformly sampled in the spatial domain. Hence it
becomes obvious that the second frequency transform in the
spatial domain (i.e. S-FFT) must be a DFT structure and,
because of aperiodic sampling, cannot be zero padded or
reduced to an FFT operation. Therefore the processing load of
circular array beamforming with array shading is given by:
LOAD (S-FFT) = 2 x M x (N1)2 (4)

C. Audio Processing
Audio processing applies digital filtering and IFFT
operations on the beamformed data as mentioned above in eq.
Figure 3 Passive Signal Processing Functions 2 and eq. 4 respectively to provide directional audio to
operators for target classification.
The processing load of FIR filter is given by [4]:
This section calculates the data rates and processing LOAD (FIR) = Ftaps x N1 x 3 (5)
requirements of the above mentioned algorithms. This will
help in determining the capability of the processor to be used where Ftaps is the number of taps for FIR filter.
in designing a real-time system. The processing load of IFFT is given by [4]:
A. Data Rate LOAD (IFFT) = 2 x N1 x M x log2 (M) (6)
Data rate for the above mentioned array configuration can The processing load of overlap and add structure (OAS) is
be calculated using the following formula [4]: given by [4]:
Data Rate = N x fs x ADC sample size (1) LOAD (OAS) = O-overlap x [LOAD (T-FFT) + octaves
LOAD (S-FFT) + octaves LOAD (IFFT)] (7)
Table 1 below shows the array design parameters with
values for the above mentioned array configuration. where O-overlap is calculated from the overlap factor that
is expressed in percentage i.e. 50% or 75 %.

TABLE I D. Spectral Analysis

Parameters Symbol Values Units High resolution spectral analysis is based on Zoom FFT
processing that involves FFT and IFFT transform pair [5].
Octaves 1
This plays a vital role in LOFAR and DEMON analysis that
Sensors per Octave N 32 provide information about target noise and acoustic
characteristics of the target in terms of shaft, blades and
Array Frequency 8 kHz propellers [3].
Sampling Frequency Fs 20 kHz The processing load of spectral analysis (SA) is given by
Data Rate 2.5 Mbytes/sec the following equations [4]:
Time Samples M 1024 LOAD (IFFT) = 2 x Freq. x log2 (Freq.) (8)
Beams N1 64 where Freq. is the number of frequency bins.
Frequency Bins M 1024 LOAD (FFT) = 2 x Ts x log2 (Ts) (9)
Spectral Resolution 19.53 Hz where Ts is the number of time samples gathered to meet
the desired frequency resolution.
Matrix Fill Time Mft 51.2 milliseconds

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 LOAD (SA) = Fig. 5 below further elaborates the above mentioned signal
processing architecture for a circular array. An array of
[N1 x LOAD (IFFT)] + [N1 x LOAD (FFT)] (10) sensors is connected to signal conditioning electronics that
The computational load of signal processing algorithms amplifies and converts the analog signals into digital form for
based on eq. 2 to eq. 10 has been developed in Table 2 below: subsequent processing using signal processing algorithms
already mentioned in section III.

TABLE II

Beamforming

Values

LOAD (T-FFT) 360448

LOAD (S-FFT) 8388608

LOAD 8749056

Audio Processing

Values

LOAD (FIR) 24576 Figure 5 Signal Processing of Circular Sensor Array

LOAD (IFFT) 1310720

Overlap Factor 50%

A sensor array system with circular array geometry is
LOAD (OAS) 2670592 usually a high frequency system (i.e. up to 20 kHz) for
medium range target detection and classification. An increase
Spectral Analysis in number of sensors and array frequency results in increased
Values data rates and processor loading as mentioned above. In this
context general-purpose processors fail to execute the
LOAD (SA) 14942208 computationally extensive signal processing algorithms in
for 2.44 Hz Resolution
real-time thereby raising the need of dedicated DSP processors
Signal Processing to perform this task.
Total LOAD 26361856 A signal processing architecture should be designed in a
way to meet real-time operation across the whole system.
Computational Load 515 MFLOPS (w.r.t Mft) Hence it becomes necessary to measure the capability of the
processor to be used. Processor selection depends upon the
processor clock speed, MFLOPS, on-chip RAM, power
consumption, and execution times for various signal
IV. SIGNAL PROCESSING ARCHITECTURE processing algorithms already mentioned in section III. The
In general a signal processing architecture consists of data signal processing requirements calculated above are estimates
acquisition, signal processing, and display processing but highlight the computational burden to be undertaken by
modules. Data acquisition and signal processing tasks can be the processor. ADC and DSP boards by National Instruments,
performed using ADC and DSP boards. Fig. 4 below shows a Texas Instruments, and Analog Devices etc are available in the
generic signal processing architecture for sensor arrays. market. These boards in PCI/cPCI form factor are being used
in many real-world applications like phased array Radar, smart
antennas, and underwater surveillance systems [4].
In this paper data acquisition, signal processing and
display processing functions are performed using two PC
based modules. These two modules are connected to each
other through Ethernet. The DSP board is from Analog
Devices and is in PCI form factor. The ADC board is an 8-
channel board with PMC form factor and is inserted on top of
the PMC Mezzanine slot of DSP board. In this approach 04
ADC boards and 04 DSP boards are utilized to digitize and
process 32 channels of the uniform circular array mentioned
above. Normal PC based motherboards comprise 2 to 3 PCI
slots, therefore, special PCI backplane up to 10 PCI slots is
Figure 4 Generic Signal Processing Architecture
used to house all the processing elements. The DSP boards
perform beamforming, audio processing and spectral analysis

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functions. The processed data is then sent to display A rack mount enclosure with up to ten 64-bit 66 MHz PCI
processing module over Ethernet. The display processing slots has been used to accommodate four DSP boards keeping
module is an Intel based motherboard. It performs some data in view the possible future up gradation. This enclosure
processing on the data coming from DSP module such as comprises Intel based Dual processor motherboard and is
normalization, integration and tracking. Finally the results are shown in fig. 8 below. Importantly, the motherboard has built
displayed in real-time. in gigabit Ethernet network interfaces for coupling with
parallel systems.

V. REAL-TIME SYSTEM IMPLEMENTATION

This paper presents a signal processing architecture for a
circular sensor array that consists of multiple ADC and DSP
boards along with a host PC and display PC. The details of
complete system in terms of its hardware and software
components have been discussed below.

A. System Hardware Figure 8 Rack Mount Chassis with Digital PCI Backplane [8]

The selected DSP processor is provided by the Tiger-PCI

B. System Software
board from Analog Devices as shown in fig. 6 below. The
Tiger-PCI board consists of four ADSP-TS101S processors, The system software consists of real-time parallel
each running at 250 MHz. The provision of four processors processing program along with host control program. The
makes parallel operation across each of the processors possible integrated development environment is VisualDSP++ 3.5.
and an ASIC is provided on the card to provide shared access Real-time processing program is developed with ANSI C/C++
to 256 MB of DRAM. Additional communications between and EZ-DSP signal processing library. The operating system
processors is provided by four, 250 MB/s, link ports on each of the host computer and display computer is Windows XP.
DSP. These high speed communication ports have been used The developing environment of host control program is Visual
to parallelise the task, partition the data and execute it across Studio 2000. The signal processing software performs
the four processors. beamforming, audio processing, and spectral analysis in
parallel on 4 DSP boards. The processed data is then sent to
display processor over gigabit Ethernet. The display
processing software has been developed in C++ along with
OpenGL and DirectX graphic libraries.

C. Implementation Mechanism
A real-time implementation of the processor architecture is
depicted in fig. 9 below:
Figure 6 Quad ADSP-TS101S DSP Board [6]

This DSP board is a standard 66 MHz format PCI format.

Up to six boards can be utilised on the PCI bus. The 66 MHz
bus uses 64 bit data transfers and has a theoretical bandwidth
of over 500 MB/s thereby providing adequate communication
bandwidth. The Tiger-PCI board has a PCI Mezzanine Card
PMC port. The PMC port supports a number of interfaces but
the most relevant to the application at hand is an 8-channel,
24-bit, 96 kHz, analog to digital converter named Audio-
PMC+ shown in fig. 7 below:

Figure 9 Implementation of Signal Processing Architecture

Figure 7 Audio PMC+ ADC Boards [7]

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 The combination of items used in this processing
architecture shown above provides a flexible and powerful
signal processing platform. The DSP board provides a
theoretical 6 GFLOPS performance from the four ADSP-
TS101S processors thereby easily meeting the processing
requirements.
The signal processing architecture shown above comprises
4 DSP boards in a standard PCI bus hosted by a standard
industrial PC. Each board contains four DSP processors and
each board communicates across the link ports. This system
can be further extended for additional analog input channels
using multiples of structures depicted above and using the
gigabit Ethernet. This processing architecture requires
distribution of time references. Sampling across the ADC
input channels must be synchronous and the PMC mezzanine
ADC boards share a common conversion clock thereby
ensuring that sampling takes place synchronously. Similarly
one DSP board acts as the master and the other three DSP
boards act as slave driving their clock from the master board
for proper synchronization. The advantage of a symmetrical
structure as shown above is that each of the DSP boards runs
identical executables in parallel. This system utilizes all COTS
components and is physically compact.
Each DSP board has a total shared outer memory called
SDRAM that acts as a data buffer for the four DSP chips
onboard and other external interfaces. This SDRAM and each
DSP on-chip RAM connect to PCI bus through shared local
bus and PCI interface controller. The host computer accesses
any inner memory of DSP and SDRAM using these interfaces.
In this way the parallel processing software is easily
implemented using the system hardware mentioned above.
Figure 10 Parallel Execution on DSP Boards
The interface between ADC and DSP board is a FIFO that
addresses information between ADC and DSP. This interface
is mapped through FPGA on the DSP board. Each ADC
channel matches with this address information. Data exchange Keeping all this in view the execution time on a single
between ADC FIFO and DSP on-chip RAM is implemented in DSP board handling 8x1024 data size is calculated as follows:
software by using external Link Ports. The point-to-point
communication among DSP processors onboard is through a. Beamforming process involves 2D-FFT analysis. At first
local Link Ports. 1024 point complex FFT is applied on the time series data of
all the 8 channels. Secondly 16 point spatial FFT is applied on
all the 1024 frequency bins. The execution time for
D. Execution of Processing Algorithms on DSP Board
beamforming comes out to be 1.0 msec.
The data size for a circular array is 32 by 1024; where 32
is the number of sensors and 1024 is the number of time b. Audio processing involves FIR filtering and IFFT on the
samples for each sensor. For parallel processing, the data is beamformed data. This FIR filtering and IFFT is applied to all
divided among four DSP boards such that each is having a the 16 spatial beams. In this way the execution time for audio
data size of 8x1024. In this way all the four boards perform processing comes out to be 5.2 msec.
the signal processing tasks in parallel, the results are c. The purpose of signal analysis function is to obtain high
accumulated in the host PC and further sent to display PC. frequency resolution data to be used for target classification. It
The next step is to calculate the execution time on each involves FFT and IFFT pairs to obtain the desired resolution.
DSP board in order to satisfy the demand of a real-time In this work 1024 point IFFT along with 8192 point FFT is
processing system. The execution time of 1024 point complex applied to all the 16 spatial beams to obtain a frequency
FFT/IFFT on a single ADSP-TS101S is 40 μsec. The resolution of 1 Hz/bin. Hence the execution time for signal
execution time of 50-taps FIR filter on a single ADSP-TS101S analysis comes out to be 5.8 msec.
is 110 μsec [9]. The signal processing functions mainly used The overall execution time on a single DSP board is 12
in this work involves FFT, IFFT and FIR filter. msec. All four DSP boards operate in parallel and run identical
The parallel implementation of this system has been executables to produce 64 beams data. This 12 msec execution
carried out as shown in the fig. 10 below: time is well within 51.2 msec i.e. matrix fill time for every
incoming data chunk, to maintain real-time operation.

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 VI. EXPERIMENTAL RESULTS VII. CONCLUSIONS
Fig. 11 and 12 below show the results of test and trials This paper presented a signal processing system consisting
conducted at field. These tests have shown that the designed of multiple ADC and DSP boards along with a host computer.
signal processing system provides adequate results. In addition this paper also explained passive signal processing
requirements for a circular sensor array. The implementation
Fig. 11 below shows a bearing time waterfall display. This mechanism discussed shows that this architecture can be easily
display shows bearing on the x-axis and time on the y-axis. modified, reconfigured and meets the real-time processing
This display has two parts i.e. amplitude vs. bearing window demands. The paper described parallel implementation of
and bearing vs. time window [3]. The color bar shows the array signal processing functions onto DSPs and its results
signal intensity of different targets and background noise. The showed efficient utilization of processors and significantly
color in dark red represents the largest signal strength or SNR.
reduced execution times. This signal processing architecture
This display shows the possible incoming targets and their and its requirements for receive processing of sensor arrays
movement in time. This display has an audio output control will facilitate other system engineers in developing similar
that permits the operator to listen to the target noise from a systems.
particular direction.
Fig. 12 below shows a high resolution signal analysis
display for narrowband detection. This display shows
frequencies on the x-axis and time on the y-axis [3]. The color REFERENCES
scheme is based on grey-scale allocation. The color in white [1] Qihu Li, Digital Sonar Design in Underwater Acoustics, Zhejiang
shows the intensity of target radiated frequencies and other University Press, Hangzhou, 2012
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its machinery noise, engine noise and propeller noise etc. Configurations: Theory and Algorithm, Helsinki University of
Technology, Signal Processing Laboratory, 2007
[3] Moura, Filho and Seixas, Advances in Sonar Technology, ISBN 978-3-
902613-48-6, pp. 232, 2009, I-Tech, Vienna, Austria
[4] Umar Hamid, Ali abbas, “Signal Processing Requirements and System
Design for Sensor Arrays using COTS Components” , IEEE Proceedings
of 11th Frontiers of Information Technology, 2013
[5] Q. Li, W. Li and W. Zhao, “A Simplified Zoom FFT Algorithm in
Digital Sonar”, Chinese Journal of Acoustics, Vol 18 (2), 97-104, 1999
[6] Quad ADSP-TS101S DSP Tiger-PCI Board Data Sheet
Information availibale at www.bittware.com
[7] Audio PMC+ DAQ Board Data Sheet
Information availibale at www.bittware.com
[8] Indsutrial Grade Computer Chassis with PCI Backplane Data Sheet
Information availibale at www.forcecomputers.com
[9] ADSP-TS101S DSP Data Sheet
Information availibale at www.digchip.com

Figure 11 Bearing-Time Waterfall

Figure 12 Frequency-Time Waterfall

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