Digital Computer Fundamentals Module 3

COMBINATIONAL CIRCUITS

The digital system consists of two types of circuits, namely

(i) Combinational circuits
(ii) Sequential circuits

Combinational circuit consists of logic gates whose output at any time is determined
from the present combination of inputs. The logic gate is the most basic building block of
combinational logic. The logical function performed by a combinational circuit is fully
defined by a set of Boolean expressions.

Sequential logic circuit comprises both logic gates and the state of storage elements such
as flip-flops. As a consequence, the output of a sequential circuit depends not only on
present value of inputs but also on the past state of inputs.

In this module, design of various simple combinational circuits is discussed. A

combinational circuit consists of input variables, logic gates, and output variables. The
logic gates accept signals from inputs and output signals are generated according to the
logic circuits employed in it. Binary information from the given data transforms to desired
output data in this process. Both input and output are obviously the binary signals, i.e.,
both the input and output signals are of two possible states, logic 1 and logic 0.

For n number of input variables to a combinational circuit, 2n possible combinations of

binary input states are possible. For each possible combination, there is one and only one
possible output combination. A combinational logic circuit can be described by m Boolean
functions and each output can be expressed in terms of n input variables.

DESIGN PROCEDURE: Any combinational circuit can be designed by the following

steps of design procedure:
1. The problem is stated.
2. Identify the input and output variables.
3. The input and output variables are assigned letter symbols.
4. Construction of a truth table to meet input -output requirements.
5. Writing Boolean expressions for various output variables in terms of input
variables.
6. The simplified Boolean expression is obtained by any method of minimization—
algebraic method, Karnaugh map method, or tabulation method.
7. A logic diagram is realized from the simplified Boolean expression using logic
gates.

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The following guidelines should be followed while choosing the preferred form for
hardware implementation:
1. The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs.
2. There should be a minimum number of interconnections.
3. Limitation on the driving capability of the gates should not be ignored.

To understand the design procedure for the design of combinational circuits, let us do
an example.

Example: Design a logic circuit that can convert a 4 bit binary number to its equivalent
gray code.

Solution:
We know that a 4 bit binary number is the input and a 4 bit gray code is the output.
The four bits of the binary number can be named as B3, B2, B1 and B0 from MSB to LSB.
Similarly, the four bits of the output gray code can be named as G3, G2, G1 and G0 from
MSB to LSB.

The truth table of the required logic circuit (binary to gray-code converter) can be
drawn as shown below.

Now, we have to derive expressions for each output variable, i.e., G3, G2, G1 and G0.

G3 = ∑m(8, 9, 10, 11, 12, 13, 14, 15)

G2 = ∑m(4, 5, 6, 7, 8, 9, 10, 11)

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G1 = ∑m(2, 3, 4, 5, 10, 11, 12, 13)

G0 = ∑m(1,2, 5, 6, 9, 10, 13, 14)

Reducing these expressions for G3, G2, G1 and G0 using K-map, we get:

Now, these expressions can be implemented using EX-OR gates.

So, the logic circuit for converting a 4 bit binary number to equivalent 4 bit gray code can
be drawn as:

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Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits. It has two
inputs that represent the two bits to be added and two outputs, with one producing the
SUM output and the other producing the CARRY.

The truth table of a half-adder, showing all possible input combinations and the
corresponding outputs are shown below.

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K-map simplification for carry and sum:

The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Sum, S = A’B+ AB’= A B
Carry, C = A . B

The first one representing the SUM output is that of an EX-OR gate, the second one
representing the CARRY output is that of an AND gate.

The logic diagram of the half adder is,

Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of 3 inputs and 2 outputs. Two of the input variables, represent the significant
bits to be added. The third input represents the carry from previous lower significant
position. The block diagram of full adder is given by,

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The full adder circuit overcomes the limitation of the half-adder, which can be used to
add two bits only. As there are three input variables, eight different input combinations
are possible. The truth table is shown below,

To derive the simplified Boolean expression from the truth table, the Karnaugh map
method is adopted as,

The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry, Cout = AB+ ACin + BCin .

The logic diagram for the above functions is shown as,

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The logic diagram of the full adder can also be implemented with two half- adders and
one OR gate. The S output from the second half adder is the exclusive-OR of Cin and the
output of the first half-adder:

Sum = A‘BC‘in + AB‘C‘in + ABCin + A‘B‘Cin

= C‘in (A‘B+AB‘) + Cin (AB+A‘B‘)
= C‘in (A‘B+AB‘) + Cin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= Cin XOR (A‘B+AB‘)
= Cin XOR (A XOR B) [x XOR y = x‘y+ xy‘]

and the carry output is:

Carry, Cout = AB+ ACin+ BCin.

= AB+ ACin+ BCin (A +A‘)
= ABCin+ AB+ ACin+ A‘BCin
= AB (Cin+1) + ACin+ A‘BCin
= AB+ ACin+ A‘BCin [Cin+1= 1]
= AB+ ACin (B+B‘) + A‘BCin
= ABCin+ AB+ A‘BCin+ AB‘Cin
= AB (Cin+1) + A‘BCin+ AB‘Cin
= AB+ A‘BCin+ AB‘Cin [Cin+1= 1]
= AB+ Cin (A’B+AB’)

(Implementation of full adder using two half adders and an OR gate)

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Binary Adder (Parallel Adder):

The 4-bit binary adder using full adder circuits is capable of adding two 4-bit numbers
resulting in a 4-bit sum and a carry output as shown in figure below.

(4 bit binary parallel adder)

Since all the bits of augend and addend are fed into the adder circuits simultaneously and
the additions in each position are taking place at the same time, this circuit is known as
parallel adder.

Let the 4-bit words to be added be represented by, A3A2A1A0 = 1111 and B3B2B1B0= 0011.

The bits are added with full adders, starting from the least significant position, to form
the sum it and carry bit. The input carry C0 in the least significant position must be 0. The
carry output of the lower order stage is connected to the carry input of the next higher
order stage. Hence this type of adder is called ripple-carry adder.

In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in sum S0 and
carry C1. This carry C1 becomes the carry input to the second stage. Similarly in the second
stage, A1, B1 and C1 are added resulting in sum S1 and carry C2, in the third stage, A2, B2
and C2 are added resulting in sum S2 and carry C3, in the third stage, A3, B3 and C3 are
added resulting in sum S3 and C4, which is the output carry. Thus the circuit results in a
sum (S3S2S1S0) and a carry output (Cout).

Binary Subtractor (Parallel Subtractor):

The subtraction of unsigned binary numbers can be done most conveniently by means of
complements. The subtraction A-B can be done by taking the 2‘s complement of B and
adding it to A. The 2‘s complement can be obtained by taking the 1‘s complement and
adding 1 to the least significant pair of bits. The 1‘s complement can be implemented with
inverters and a 1 can be added to the sum through the input carry.

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The circuit for subtracting A-B consists of an adder with inverters placed between each
data input B and the corresponding input of the full adder. The input carry C0 must be
equal to 1 when performing subtraction. The operation thus performed becomes A, plus
the 1‘s complement of B, plus1. This is equal to A plus the 2‘s complement of B.

(4 bit binary parallel subtractor)

Parallel Adder/ Subtractor:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. This is done by including an exclusive-OR gate with each full
adder. A 4-bit adder Subtractor circuit is shown below.

(4 bit binary adder subtractor)

The mode input M controls the operation. When M= 0, the circuit is an adder and when
M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives input M and one
of the inputs of B. When M=0, we have B 0= B. The full adders receive the value of B, the
input carry is 0, and the circuit performs A plus B. When M=1, we have B 1= B‘ and C0=1.
The B inputs are all complemented and a 1 is added through the input carry. The circuit
performs the operation A plus the 2‘s complement of B.

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BCD Adder:
A BCD adder is a circuit that adds two BCD numbers and produces a sum also in BCD.
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 9+9+1 = 19. The adder will form the sum in binary and produce a
result that ranges from 0 through 19.

When the binary sum is equal to or less than 1001, it is identical to the corresponding BCD
number, and therefore no conversion is needed. When the binary sum is greater than 9
(1001), we obtain a non- valid BCD representation. The addition of binary 6 (0110) to the
binary sum converts it to the correct BCD representation and also produces an output
carry as required.

Therefore, to implement BCD adder we require:

• 4-bit binary adder for initial addition
• Logic circuit to detect sum greater than 9 and
• One more 4-bit adder to add 01102 in the sum if the sum is greater than 9 or carry
is 1.

The logic circuit to detect sum greater than 9 can be determined by simplifying the
Boolean expression of the truth table shown below.

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(BCD Adder – Block Diagram)

The two decimal digits, together with the input carry, are first added in the top 4- bit
binary adder to provide the binary sum. When the output carry is equal to zero and the
binary sum is less or equal to 1001, nothing is added to the binary sum. When it is equal
to one or binary sum is greater than 1001, binary 0110 is added to the binary sum through
the bottom 4-bit adder. The output carry generated from the bottom adder can be ignored,
since it supplies information already available at the output carry terminal. The output
carry from one stage must be connected to the input carry of the next higher-order stage.

BINARY MULTIPLIER:
Multiplication of binary numbers is performed in the same way as in decimal numbers.
The multiplicand is multiplied by each bit of the multiplier starting from the least
significant bit. Each such multiplication forms a partial product. Such partial products are
shifted one position to the left. The final product is obtained from the sum of partial
products.

Consider the multiplication of two 2-bit numbers. The multiplicand bits are B1 and B0, the
multiplier bits are A1 and A0, and the product is C3, C2, C1 and C0. The first partial product
is formed by multiplying A0 by B1B0. The multiplication of two bits such as A0 and B0
produces a 1 if both bits are 1; otherwise, it produces a 0. This is identical to an AND
operation. Therefore, the partial product can be implemented with AND gates as shown
in the diagram below.

The second partial product is formed by multiplying A1 by B1B0 and shifted one position
to the left. The two partial products are added with two half adder (HA) circuits.

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(2 bit by 2 bit binary multiplier)

MAGNITUDE COMPARATOR:
A magnitude comparator is a combinational circuit that compares two given numbers (A
and B) and determines whether one is equal to, less than or greater than the other. The
output is in the form of three binary variables representing the conditions A = B, A>B and
A<B, if A and B are the two numbers being compared.

2-bit Magnitude Comparator:

The truth table of 2-bit comparator is given in table below:

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Expressions are found out for A<B, A=B and A>B. Now the logic circuit of 2 bit magnitude
comparator can be drawn as shown below.

DECODERS:
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines. The general structure of decoder circuit is:

The encoded information is presented as n inputs producing 2n possible outputs. The 2n

output values are from 0 through 2n-1. A decoder is provided with enable inputs to
activate decoded output based on data inputs.

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2 to 4 line decoder (Binary decoder):

A binary decoder is used when it is necessary to activate exactly one of 2n outputs based
on an n-bit input value.

Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables.

As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs (Y 0 – Y3),
is active for a given input.
The output Y0 is active, ie., Y0= 1 when inputs A= B= 0, Y1 is active when inputs, A= 0 and
B= 1, Y2 is active, when input A= 1 and B= 0, Y3 is active, when inputs A= B= 1.

Similarly we can construct 3 to 8 line decoder, 4 to 16 line decoder etc.

Applications of decoders:
1. Decoders are used in counter system.
2. They are used in analog to digital converter.
3. Decoder outputs can be used to drive a display system.

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ENCODERS:
An encoder is a digital circuit that performs the inverse operation of a decoder. Hence,
the opposite of the decoding process is called encoding. An encoder is a combinational
circuit that converts binary information from 2n input lines to a maximum of n unique
output lines.

The general structure of encoder circuit is:

It has 2n input lines, only one of which is active at any time and n output lines. It encodes
one of the active inputs to a coded binary output with n bits. In an encoder, the number
of outputs is less than the number of inputs.

Octal-to-Binary (8 to 3 line) Encoder:

It has eight inputs (one for each of the octal digits) and the three outputs that generate the
corresponding binary number. It is assumed that only one input has a value of 1 at any
given time.

The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table. Output C is equal to 1, when the input octal digit is 1 or 3 or 5 or 7.
Output B is 1 for octal digits 2, 3, 6, or 7 and the output A is 1 for digits 4, 5, 6 or 7. These
conditions can be expressed by the following output Boolean functions:

C = D1+ D3+ D5+ D7

B = D2+ D3+ D6+ D7
A = D4+ D5+ D6+ D7

The encoder can be implemented with three OR gates.

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Priority Encoder:
The encoder described above has the limitation that only one input can be active at any
given time. If two inputs are active simultaneously, the output produces an undefined
combination.

For eg., if D3 and D6 are 1 simultaneously, the output of the encoder may be 111. This does
not represent either D6 or D3. To resolve this problem, encoder circuits must establish an
input priority to ensure that only one input is encoded. If we establish a higher priority
for inputs with higher subscript numbers and if D3 and D6 are 1 at the same time, the
output will be 110 because D6 has higher priority than D3.

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if two or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.

In addition to the two outputs x and y, the circuit has a third output, V (valid bit indicator).
It is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid
input and V is equal to 0.

Truth table:

The higher the subscript number, higher the priority of the input. Input D3, has the highest
priority. So, regardless of the values of the other inputs, when D3 is 1, the output for xy is
11.
D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The output for D1
is generated only if higher priority inputs are 0, and so on down the priority levels.

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K-Map simplification:

X = D3+D2 y = D3+D1D2’

V = D0+D1+D2+D3

Thus, the priority encoder can be implemented as:

D3 D2 D1 D0

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MULTIPLEXER: (Data Selector):

A multiplexer or MUX, is a combinational circuit with more than one input line, one
output line and more than one selection line. A multiplexer selects binary information
present from one of many input lines, depending upon the logic status of the selection
inputs, and routes it to the output line. Normally, there are 2n input lines and n selection
lines whose bit combinations determine which input is selected. The multiplexer is often
labelled as MUX in block diagrams.

A multiplexer is also called a data selector, since it selects one of many inputs and steers
the binary information to the output line.

(Block diagram of a Multiplexer)

2-to-1- line Multiplexer:

A 2 to 1 line MUX has two data input lines, one output line and one selection line, S. It
acts like an electronic switch that selects one of the two sources.

When S= 0, the upper AND gate is enabled and I0 has a path to the output. When S=1, the
lower AND gate is enabled and I1 has a path to the output.

We can write the expression for MUX output, Y:

Y = S’I0 + SI1

Applications of Multiplexers:
The multiplexer is a very useful logic circuit and has various ranges of applications in data
communication. Signal routing and data communication are the important applications
of a multiplexer. It is used for connecting two or more sources to guide to a single
destination among computer units and it is useful for constructing a common bus system.
One of the general properties of a multiplexer is that Boolean functions can be
implemented by this device.

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