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Fundamentals of Modern VLSI Devices
Third Edition
A thoroughly updated third edition of a classic and widely adopted text, perfect for
practical transistor design and in the classroom. Covering a variety of recent develop-
ments, the internationally renowned authors discuss in detail the basic properties and
designs of modern VLSI devices, as well as factors affecting performance. Containing
around 25% new material, coverage has been expanded to include high-k gate
dielectrics, metal gate technology, strained silicon mobility, non-GCA (Gradual
Channel Approximation) modeling of MOSFETs, short-channel FinFETS, and sym-
metric lateral bipolar transistors on SOI. Chapters have been reorganized to integrate
the appendices into the main text to enable a smoother learning experience, and
numerous additional end-of-chapter homework exercises (+30%) are included to
engage students with real-world problems and test their understanding. A perfect text
for senior undergraduate and graduate students taking advanced semiconductor
devices courses, and for practicing silicon device professionals in the semiconductor
industry.
YUAN TAUR
University of California, San Diego
TAK H . N ING
IBM T. J. Watson Research Center (retired)
University Printing House, Cambridge CB2 8BS, United Kingdom
One Liberty Plaza, 20th Floor, New York, NY 10006, USA
477 Williamstown Road, Port Melbourne, VIC 3207, Australia
314–321, 3rd Floor, Plot 3, Splendor Forum, Jasola District Centre, New Delhi – 110025, India
103 Penang Road, #05–06/07, Visioncrest Commercial, Singapore 238467
www.cambridge.org
Information on this title: www.cambridge.org/highereducation/isbn/9781108480024
DOI: 10.1017/9781108847087
© Cambridge University Press 1998, 2009, 2022
This publication is in copyright. Subject to statutory exception
and to the provisions of relevant collective licensing agreements,
no reproduction of any part may take place without the written
permission of Cambridge University Press.
First published 1998
Second edition 2009
First paperback edition 2013
Eighth printing 2020
Third edition 2022
Printed in the United Kingdom by TJ Books Limited, Padstow, Cornwall
A catalogue record for this publication is available from the British Library.
Library of Congress Cataloging-in-Publication Data
Names: Taur, Yuan, 1946–, author. | Ning, Tak H., 1943– author.
Title: Fundamentals of modern VLSI devices / Yuan Taur, University of California, San Diego,
Tak H. Ning, IBM Fellow (retired).
Description: Third edition. | United Kingdom ; New York : Cambridge University Press, 2022. |
Includes bibliographical references and index.
Identifiers: LCCN 2021029073 (print) | LCCN 2021029074 (ebook) | ISBN 9781108480024 (hardback) |
ISBN 9781108847087 (epub)
Subjects: LCSH: Metal oxide semiconductors, Complementary. | Bipolar transistors. | Integrated circuits–
Very large scale integration. | BISAC: TECHNOLOGY & ENGINEERING / Electronics /
Optoelectronics
Classification: LCC TK7871.99.M44 T38 2022 (print) | LCC TK7871.99.M44 (ebook) |
DDC 621.39/5–dc23
LC record available at https://lccn.loc.gov/2021029073
LC ebook record available at https://lccn.loc.gov/2021029074
ISBN 978-1-108-48002-4 Hardback
Additional resources for this publication at www.cambridge.org/taur3ed
Cambridge University Press has no responsibility for the persistence or accuracy
of URLs for external or third-party internet websites referred to in this publication
and does not guarantee that any content on such websites is, or will remain,
accurate or appropriate.
Contents
1 Introduction 1
1.1 Evolution of VLSI Device Technology 1
1.1.1 Historical Perspective 1
1.1.2 Recent Developments 3
1.2 Scope and Brief Description of the Book 5
v
vi Contents
4 MOS Capacitors 99
4.1 Energy Band Diagram of an MOS System 99
4.1.1 Free Electron Level, Work Function, and Flatband Voltage 99
4.1.2 Gate Voltage, Surface Potential, and Charge in Silicon 102
4.1.3 Accumulation, Depletion, and Inversion 103
4.2 Electrostatic Potential and Charge Distribution in Silicon 106
4.2.1 Solving Poisson’s Equation 106
4.2.2 Surface Potential and Charge Density as a Function of Gate
Voltage 112
4.3 Capacitance–Voltage Characteristics of MOS Capacitors 114
4.3.1 Measurement Setup 114
4.3.2 Capacitance Components in MOS 114
4.3.3 C–V Characteristics in Different Bias Regions 115
4.3.4 Split C–V Measurement 119
4.3.5 Polysilicon Gate: Work Function and Depletion Effects 121
4.3.6 MOS under Nonequilibrium 125
4.4 Quantum Mechanical Effects in MOS 129
4.4.1 Coupled Poisson–Schrodinger’s Equations 129
4.4.2 Quantum Effect on Inversion-Layer Depth 129
Contents vii
References 565
Index 587
Preface to the Third Edition
It has been twenty-four years since the first edition of this book was published, thirteen
years since the second edition. Both editions have been translated into Japanese. The
second edition has also been translated into Chinese. During this time period, the
VLSI integrated-circuit industry marches on. The minimum feature size has shrunk by
more than 10 to now reaching <10 nm. The transistor count has well exceeded ten
billion in the densest populated IC chips. New technology thrust areas include double-
gate MOSFETs (known as FinFETs), thin-film silicon-on-insulator devices (ET-SOI),
and 3-D integration in nonvolatile memory chips. Meanwhile, SOI wafers suitable for
partially depleted SOI CMOS have found new applications in the integration of
npn and pnp lateral bipolar, offering the interesting possibility of bipolar as
a complement to CMOS for VLSI.
The purpose of writing the third edition is to update the book with additional
material developed after the completion of the second edition. Key topics added
include high-κ gate dielectrics, metal gate technology, strained silicon mobility,
non-GCA (Gradual Channel Approximation) modeling of MOSFETs, and lateral
bipolar transistors on SOI. Furthermore, the chapters of the book have been reorgan-
ized to consolidate the discussions of the various subjects to the main chapters with
no appendices.
We would like to take this opportunity to thank all the friends and colleagues who
gave us encouragement and valuable suggestions for improvement of the book; in
particular, Professor Sorin Cristoloveanu of the University of Grenoble Alpes and Dr.
Kangguo Cheng of IBM on SOI device technology, and Professor Scott Thompson of
the University of Florida on strained silicon mobility.
Tak Ning would like to thank many of his colleagues at IBM, particularly Dr. Jin
Cai (now at TSMC), Dr. Jeng-Bang Yau, and Dr. Ghavam Shahidi for their contribu-
tions to the SOI lateral bipolar project. Yuan Taur would like to thank many of his
students at the University of California, San Diego, in particular Chuyang Hong, Qian
Xie, and Bo Yu, for their help with the completion of the third edition. He would also
like to thank Katie and Ko Taur for their love and support during the course of
the work.
xiii
Preface to the Second Edition
Since the publication of the first edition of Fundamentals of Modern VLSI Devices by
Cambridge University Press in 1998, we received much praise and many encouraging
reviews on the book. It has been adopted as a textbook for first-year graduate courses
on microelectronics in many major universities in the United States and worldwide.
The first edition was translated into Japanese by a team led by Professor Shibahara of
Hiroshima University in 2002.
During the past ten years, the evolution and scaling of VLSI (very-large-scale-
integration) technology has continued. Now, sixty years after the first invention of the
transistor, the number of transistors per chip for both microprocessors and DRAM
(dynamic random access memory) has increased to over one billion, and the highest
clock frequency of microprocessors has reached 5 GHz. In 2007, the worldwide IC
(integrated circuits) sales grew to $250 billion. In 2008, the IC industry reached the
45-nm generation, meaning that the leading-edge IC products employ a minimum
lithography feature size of 45 nm. As bulk CMOS (complementary metal–oxide–
semiconductor field-effect transistor) technologies are scaled to dimensions below
100 nm, the very factor that makes CMOS technology the technology of choice for
digital VLSI circuits, namely, its low standby power, can no longer be taken for
granted. Not only has the off-state current gone up with the power supply voltage
down scaled to the 1V level, the gate leakage has also increased exponentially from
quantum mechanical tunneling through gate oxides only a few atomic layers thick.
Power management, both active and standby, has become a key challenge to con-
tinued increase of clock frequency and transistor count in microprocessors. New
materials and device structures are being explored to replace conventional bulk
CMOS in order to extend scaling to 10 nm.
The purpose of writing the second edition is to update the book with additional
material developed after the completion of the first edition. Key new material added
includes MOSFET scale length theory and high-field transport model, and the section
on SiGe-base bipolar devices has been greatly expanded. We have also expanded the
discussions on basic device physics and circuits to include metal–silicon contacts,
noise margin of CMOS circuits, and figures of merit for RF applications. Furthermore,
two new chapters are added to the second edition. Chapter 9 is on memory devices and
covers the fundamentals of read and write operations of commonly used SRAM,
DRAM, and nonvolatile memory arrays. Chapter 10 is on silicon-on-insulator (SOI)
devices, including advanced devices of future potential.
xv
xvi Preface to the Second Edition
We would like to take this opportunity to thank all the friends and colleagues who
gave us encouragement and valuable suggestions for improvement of the book. In
particular, Professor Mark Lundstrom of Purdue University, who adopted the first
edition early on, and Dr. Constantin Bulucea of the National Semiconductor
Corporation, who suggested the treatment on diffusion capacitance. Thanks also go
to Professor James Meindl of the Georgia Institute of Technology, Professor Peter
Asbeck of the University of California, San Diego, and Professor Jerry Fossum of the
University of Florida for their support of the book.
We would like to thank many of our colleagues at IBM, particularly in the areas of
advanced silicon-device research and development, for their direct or indirect contri-
butions. Yuan Taur would like to thank many of his students at the University of
California, San Diego, in particular Jooyoung Song and Bo Yu, for their help with the
completion of the second edition. He would also like to thank Katie Kahng for her
love, support, and patience during the course of the work.
We would like to give special thanks to our families for their support and under-
standing during this seemingly endless task.
Preface to the First Edition
It has been fifty years since the invention of the bipolar transistor, more than forty
years since the invention of integrated-circuit (IC) technology, and more than thirty-
five years since the invention of the MOSFET. During this time, there has been
tremendous and steady progress in the development of IC technology with a rapid
expansion of the IC industry. One distinct characteristic in the evolution of IC
technology is that the physical feature sizes of the transistors are reduced continually
over time as the lithography technologies used to define these features become
available. For almost thirty years now, the minimum lithography feature size used
in IC manufacturing has been reduced at a rate of 0.7 every three years. In 1997, the
leading-edge IC products have a minimum feature size of 0.25 μm.
The basic operating principles of large and small transistors are the same. However,
the relative importance of the various device parameters and performance factors for
transistors of the 1 μm and smaller generations is quite different from those for
transistors of larger-dimension generations. For example, in the case of CMOS, the
power-supply voltage was lowered from the standard 5 V, starting with the 0.6 to 0.8
μm generation. Since then CMOS power supply voltage has been lowered in steps
once every few years as the device physical dimensions are reduced. At the same time,
many physical phenomena, such as short-channel effect and velocity saturation, which
are negligible in large-dimension MOSFETs, are becoming more and more important
in determining the behavior of MOSFETs of deep-submicron dimensions. In the case
of bipolar devices, breakdown voltage and base-widening effects are limiting their
performance, and power dissipation is limiting their level of integration on a chip.
Also, the advent of SiGe-base bipolar technology has extended the frequency capabil-
ity of small-dimension bipolar transistors into the range previously reserved for GaAs
and other compound-semiconductor devices.
The purpose of this book is to bring together the device fundamentals that govern
the behavior of CMOS and bipolar transistors into a single text, with emphasis on
those parameters and performance factors that are particularly important for VLSI
(very-large-scale-integration) devices of deep-submicron dimensions. The book starts
with a comprehensive review of the properties of the silicon material, and the basic
physics of p–n junctions and MOS capacitors, as they relate to the fundamental
principles of MOSFET and bipolar transistors. From there, the basic operation of
MOSFET and bipolar devices, and their design and optimization for VLSI applica-
tions are developed. A great deal of the volume is devoted to in-depth discussions of
xvii
xviii Preface to the First Edition
the intricate interdependence and subtle tradeoffs of the various device parameters
pertaining to circuit performance and manufacturability. The effects which are par-
ticularly important in small-dimension devices, e.g., quantization of the two-
dimensional surface inversion layer in a MOSFET device and the heavy-doping effect
in the intrinsic base of a bipolar transistor, are covered in detail. Also included in this
book are extensive discussions on scaling and limitations to scaling of MOSFET and
bipolar devices.
This book is suitable for use as a textbook by senior undergraduate or graduate
students in electrical engineering and microelectronics. The necessary background
assumed is an introductory understanding of solid-state physics and semiconductor
physics. For practicing engineers and scientists actively involved in research and
development in the IC industry, this book serves as a reference in providing a body
of knowledge in modern VLSI devices for them to stay up to date in this field.
VLSI devices are too huge a subject area to cover thoroughly in one book. We have
chosen to cover only the fundamentals necessary for discussing the design and
optimization of the state-of-the-art CMOS and bipolar devices in the sub-0.5-μm
regime. Even then, the specific topics covered in this book are based on our own
experience of what the most important device parameters and performance factors are
in modern VLSI devices.
Many people have contributed directly and indirectly to the topics covered in this
book. We have benefited enormously from the years of collaboration and interaction
we had with our colleagues at IBM, particularly in the areas of advanced silicon-
device research and development. These include Douglas Buchanan, Hu Chao, T. C.
Chen, Wei Chen, Kent Chuang, Peter Cook, Emmanuel Crabbé, John Cressler, Bijan
Davari, Robert Dennard, Max Fischetti, David Frank, Charles Hsu, Genda Hu,
Randall Isaac, Khalid Ismail, G. P. Li, Shih-Hsien Lo, Yuh-Jier Mii, Edward
Nowak, George Sai-Halasz, Stanley Schuster, Paul Solomon, Hans Stork, Jack Sun,
Denny Tang, Lewis Terman, Clement Wann, James Warnock, Siegfried Wiedmann,
Philip Wong, Matthew Wordeman, Ben Wu, and Hwa Yu.
We would like to acknowledge the secretarial support of Barbara Grady and the
support of our management at IBM Thomas J. Watson Research Center where this
book was written. Finally, we would like to give special thanks to our families –
Teresa, Adrienne, and Brenda Ning, and Betty, Ying, and Hsuan Taur – for their
support and understanding during this seemingly endless task.
Physical Constants and Unit Conversions
Angstrom Å 1Å ¼ 108 cm
Nanometer nm 1 nm ¼ 107 cm
Micrometer (micron) μm 1 μm ¼ 104 cm
Millimeter mm 1 mm ¼ 0.1 cm
Meter m 1 m ¼ 102 cm
Electron-volt eV 1eV ¼ 1.6 1019 J
A word of caution about the length units: Strictly speaking, MKS units should be used
for all the equations in the book. As a matter of convention, electronics engineers often
work with centimeters as the unit of length. While some equations work with lengths
in either meters or centimeters, not all of them do. It is prudent always to check for
unit consistency when doing calculations. It may be necessary to convert the length
unit to meters before plugging into the equations.
xix
Symbols
A Area cm2
AE Emitter area cm2
α Common-base current gain None
α0 Static common-base current gain None
αF Forward common-base current gain in the Ebers–Moll model None
αR Reverse common-base current gain in the Ebers–Moll model None
αT Base transport factor None
αn Electron-initiated rate of electron–hole pair generation per unit cm1
distance
αp Hole-initiated rate of electron–hole pair generation per unit distance cm1
BV Breakdown voltage V
BVCBO Collector–base junction breakdown voltage with emitter open circuit V
BVCEO Collector–emitter breakdown voltage with base open circuit V
BVEBO Emitter–base junction breakdown voltage with collector open circuit V
β Current gain None
β0 Static common-emitter current gain None
βF Forward common-emitter current gain in the Ebers–Moll model None
βR Reverse common-emitter current gain in the Ebers–Moll model None
c Velocity of light in vacuum (= 3 1010 cm/s) cm/s
C Capacitance F
Cd Depletion-layer capacitance per unit area F/cm2
Cd MOS gate depletion-layer capacitance per unit area F/cm2
CdBC Base–collector diode depletion-layer capacitance per unit area F/cm2
CdBC,tot Total base–collector diode depletion-layer capacitance F
CdBE Base–emitter diode depletion-layer capacitance per unit area F/cm2
CdBE,tot Total base–emitter diode depletion-layer capacitance F
Cdm Maximum MOS gate depletion capacitance per unit area F/cm2
CD Diffusion capacitance F
CD MOS gate depletion-layer capacitance F
CDn Diffusion capacitance due to excess electrons F
CDp Diffusion capacitance due to excess holes F
CDE Emitter diffusion capacitance F
Cfb MOS capacitance at flat band per unit area F/cm2
CFC Capacitance between the floating gate and the control gate of a F
MOSFET nonvolatile memory device
Cg Intrinsic gate capacitance per unit area F/cm2
CG Total gate capacitance of MOSFET F
Cinv MOS capacitance per unit area in the inversion region F/cm2
Ci Inversion-layer capacitance per unit area F/cm2
xx
List of Symbols xxi
(cont.)
(cont.)
(cont.)
(cont.)
(cont.)
(cont.)
(cont.)
Since the invention of the bipolar transistor in 1947, there has been an unprecedented
growth of the semiconductor industry, with an enormous impact on the way people
work and live. In the last forty years or so, by far the strongest growth area of the
semiconductor industry has been in silicon very-large-scale-integration (VLSI) tech-
nology. The sustained growth in VLSI technology is fueled by the continued shrink-
ing of transistors to ever smaller dimensions. The benefits of miniaturization – higher
packing densities, higher circuit speeds, and lower power dissipation – have been key
in the evolutionary progress leading to today’s computers, wireless units, and com-
munication systems that offer superior performance, dramatically reduced cost per
function, and much reduced physical size, in comparison with their predecessors. On
the economic side, the integrated-circuit (IC) business has grown worldwide in sales
from $1 billion in 1970 to $20 billion in 1984 and has reached $439 billion in 2020.
The electronics industry is now among the largest industries in terms of output as well
as employment in many nations. The importance of microelectronics in economic,
social, and even political development throughout the world will no doubt continue to
ascend. The large worldwide investment in VLSI technology constitutes a formidable
driving force that will all but guarantee the continued progress in IC integration
density and speed, for as long as physical principles will allow.
1
2 1 Introduction
One-transistor
First bipolar DRAM cell
transistor invented
(1947) (1968)
First
MOSFET
(1960) VLSI era
Figure 1.1 A brief chronology of the major milestones in the development of VLSI
of vertical bipolar circuits has severely limited their integration level, to about 104
circuits1 per chip. This integration level is very low by today’s VLSI standard.
The idea of modulating the surface conductance of a semiconductor by the appli-
cation of an electric field was first envisioned in 1930. However, early attempts to
fabricate a surface-field-controlled device were not successful because of the presence
of large densities of surface states which effectively shielded the surface potential
from the influence of an external field. The first MOSFET on a silicon substrate using
SiO2 as the gate insulator was fabricated in 1960 (Kahng and Atalla, 1960). During the
1960s and 1970s, n-channel and p-channel MOSFETs were widely used, along with
bipolar transistors, for implementing circuit functions on a silicon chip. Although the
MOSFET devices were slow compared to the bipolar devices, they had a higher layout
density and were relatively simple to fabricate; the simplest MOSFET chip could be
made using only four masks and a single doping step. However, just like vertical
bipolar circuits, single-polarity MOSFET circuits suffered from large standby power
dissipation, hence were limited in the level of integration on a chip.
The major breakthrough in the level of integration came in 1963 with the invention
of CMOS (complementary MOS) (Wanlass and Sah, 1963), in which n-channel and p-
channel MOSFETs are constructed side by side on the same substrate. A CMOS
circuit typically consists of an n-channel MOSFET and a p-channel MOSFET con-
nected in series between the power-supply terminals, so that there is negligible
standby power dissipation. Significant power is dissipated only during switching of
the circuit (i.e., only when the circuits are active). By cleverly designing the “switch
activities” of the circuits on a chip to minimize active power dissipation, engineers
have been able to integrate billions of CMOS transistors on a single chip and still have
the chip readily air-coolable. Until the minimum feature size of lithography reached
180 nm, the integration level of CMOS was not limited by chip-level power
1
ECL circuits, discussed in Section 11.2.
1.1 Evolution of VLSI Device Technology 3
Immersion lithography has been adopted for volume IC manufacturing (Lin, 2004).
Immersion lithography is a photolithography resolution enhancement technique
where the usual gap between the final lens and the wafer surface is replaced with a
liquid medium having a refractive index greater than one. The resolution
enhancement is equal to the refractive index of the liquid used. With immersion,
deep ultraviolet (DUV) lithography systems remain the work horse for
semiconductor manufacturing today.
4 1 Introduction
1E+12 3
FLASH 256Gb
1E+11
CMOS
16Gb 8Gb 1
1E+10
1E+9
0.3
5GHz
1E+8
Figure 1.2 Trends in lithographic feature size, number of transistors per chip for DRAM and
MPU, and number of memory bits per chip for Flash. The transistor count for DRAM is
computed as 1.5-times the number of bits on the chip to account for the peripheral circuits. Data
points represent announced leading-edge products
Driven by the need for low-power and light-weight data storage in battery-operated
personal systems, NAND flash (the highest density version of the electrically
programmable and erasable nonvolatile memory) development has been on an
exceptionally steep trajectory since the mid-1990s. In the past decade or so, NAND
flash has overtaken DRAM as the IC chip with the highest component count, as
shown in Figure 1.2 (Kim, 2008). Since then, the combination of 3D NAND
process technology, where upwards of 100+ layers of NAND flash memory
cells are stacked on top of another to form a three-dimensional IC chip, and multi-
bit-per-cell design has dramatically increased the chip-level bit density of
NAND flash.
For a long time, a common practice in designing a scaled CMOS device was to
allow its off current to increase, by reducing the device threshold voltage, in
order to increase the on current to achieve the targeted performance of the scaled
device. As a result, the off current of scaled CMOS devices had been increasing
from one generation to the next. By the time scaling reached the 65 nm node, the
off current of scaled CMOS device had reached 100 nA/μm, the maximum level
acceptable to designers of high-end microprocessors. Since then, high-
performance CMOS devices have been designed with a nominal off current of
100 nA/μm (Kuhn et al., 2012). Capping the tradeoff between on current and off
current in designing scaled CMOS devices severely limits the speed (clock
frequency) of microprocessors. Today, the highest speed microprocessors run at
5.2 GHz (Berry et al., 2020), practically the same as those in 2009 (see
Figure 1.2).
1.2 Scope and Brief Description of the Book 5
Without the ability to increase the device off current, CMOS designers turned to
device structures having fully depleted device body, which enables the subthreshold
swing of the device to reach the ideal 60 mV/decade at room temperature. Today,
FinFET CMOS, where the depleted device body is shaped like a fin, planar ETSOI
(extremely thin silicon-on-insulator) CMOS, which is basically fully depleted SOI
CMOS, as well as traditional planar bulk CMOS are in volume manufacturing.
Partially depleted (PD) planar SOI CMOS ran its course over a span of about fifteen
years, with the first PD SOI CMOS microprocessor fabricated in the 220 nm node
in 1999 (Shahidi et al., 1999), and the last in the 22 nm node in 2015 (Freeman
et al., 2015). PD SOI CMOS is judged not scalable to smaller dimensions.
However, SOI wafers suitable for PD SOI CMOS have found new applications in
complementary (integration of n p n and p n p) lateral bipolar (Cai et al.,
2011), offering interesting possibilities in bipolar for VLSI.
In writing this book, it is our goal to address the factors governing the performance of
modern VLSI devices in depth. This is carried out by first discussing the device
physics that goes into the design of individual device parameters, and then discussing
the effects of these parameters on the performance of small-dimension modern
transistors at the basic circuit level. A substantial part of the book is devoted to in-
depth discussions on the interdependency among the device parameters and the subtle
tradeoffs in the design of modern CMOS and bipolar transistors.
This book contains sufficient background tutorials to be used as a textbook for
students taking a graduate or advanced undergraduate course in microelectronics. The
prerequisite is one semester of either solid-state physics or semiconductor physics. For
the practicing engineer, this book provides an extensive source of reference material
that covers the fundamentals of CMOS and bipolar technologies, devices, and circuits.
It should be useful to VLSI process engineers and circuit designers interested in
learning basic device principles, and to device design or characterization engineers
who desire more in-depth knowledge in their specialized areas.
New topics and materials in the third edition include an expanded chapter on ETSOI
and FinFETs, non-GCA (Gradual Channel Approximation) model for MOSFETs, and
the relatively recent development of symmetric lateral bipolar transistors on SOI. Also
added are sections on high-κ gate dielectrics, metal gates, strain effect on mobility, and
interface–state models. Much of the materials in the second edition have been restruc-
tured by consolidating all the appendices into the main chapters for a more focused
coverage of the various subjects. Here is a brief description of each chapter.
Starting with the energy bands in silicon, Chapter 2 introduces the basic concepts of
Fermi level, carrier concentration, drift and diffusion current transport, and Poisson’s
equation. Also addressed in this chapter are generation and recombination, minority
carrier lifetime, and current continuity equation.
limit of a MOSFET. Next considered are the major device design issues in a CMOS
technology: choice of threshold voltage based on the off-current requirement and on-
current performance, power supply voltage, design of nonuniform channel doping,
and discrete dopant effects on threshold voltage. The last section discusses high-field
effects in a short-channel MOSFET.
derive the current equations for a bipolar transistor. From these current equations,
other important device parameters and phenomena, such as current gain, early voltage,
base widening, and diffusion capacitance, are examined. The basic equivalent-circuit
models relating the device parameters to circuit parameters are developed. These
equivalent-circuit models form the starting point for discussing the performance of a
bipolar transistor in circuit applications.
This chapter reviews the basic concepts of semiconductor device physics. It covers
energy bands in silicon, Fermi level, n-type and p-type silicon, electrostatic potential,
drift and diffusion current transport, and basic equations governing VLSI device
operation. These will serve as the basis for understanding more advanced device
concepts discussed in the rest of the book.
The starting material used in the fabrication of VLSI devices is silicon in the crystalline
form. The silicon wafers are cut parallel to either the <111> or <100> planes (Sze, 1981),
with <100> material being the most commonly used. This is largely due to the fact that
<100> wafers, during processing, produce the lowest charges at the oxide–silicon
interface as well as higher mobility (Balk et al., 1965). In a silicon crystal each atom has
four valence electrons to share with its four nearest neighboring atoms. The valence
electrons are shared in a paired configuration called a covalent bond. The most important
result of the application of quantum mechanics to the description of electrons in a solid
is that the allowed energy levels of electrons are grouped into bands (Kittel, 1976). The
bands are separated by regions of energy that the electrons in the solid cannot possess:
forbidden gaps. The highest energy band that is completely filled by electrons at 0 K is
called the valence band. The next highest energy band, separated by a forbidden gap from
the valence band, is called the conduction band, as shown in Figure 2.1.
9
10 2 Basic Device Physics
band. This allows limited conduction to take place from the motion of both the
electrons in the conduction band and the holes in the valence band. In contrast, an
insulator has a much larger forbidden gap of at least several electron volts, making
room-temperature conduction virtually nonexistent. Metals, on the contrary, have
partially filled conduction bands even at absolute zero temperature, so that the
electrons can easily move into states of higher energy in response to an applied
electric field. This makes them good conductors at any temperature.
As shown in Figure 2.1, the energy of the electrons in the conduction band increases
upward, while the energy of the holes in the valence band increases downward. The
bottom of the conduction band is designated E c , and the top of the valence band Ev .
Their separation, or the bandgap, is Eg ¼ E c E v . For silicon, E g is 1.12 eV at room
temperature or 300 K. The bandgap decreases slightly as the temperature increases, with
a temperature coefficient of dE g =dT 2:73 104 eV=K for silicon near 300 K.
Other important physical parameters of silicon and silicon dioxide are listed in Table 2.1
(Green, 1990).
Property Si SiO2
where dpx dpy dpz is the volume in the momentum space within which the electron
energy lies between E and E þ dE, g is the number of equivalent minima in the
conduction band, and the factor of two arises from the two possible directions of
electron spin. The conduction band of silicon has a sixfold degeneracy, so g ¼ 6. Note
that MKS units are used here (e.g., length must be in meters, not centimeters).
If the electron kinetic energy is not too high, one can consider the energy–
momentum relationship near the conduction-band minima as being parabolic and
write
p2x p2y p2
E Ec ¼ þ þ z , (2.2)
2mx 2my 2my
where E Ec is the electron kinetic energy, and mx , my , mz are the effective masses.
The constant energy surface in momentum space is an ellipsoid with the lengths of the
symmetry axes proportional to the square roots of mx , my , and mz . For the silicon
conduction band in the <100> direction, two of the effective masses are the
transverse mass mt ¼ 0:19m0 , and the third is the longitudinal mass ml ¼ 0:92m0 ,
where m0 is the free electron mass. The volume of the ellipsoid given by Eq. (2.2)
in momentum space is ð4π=3Þð8mx my mz Þ1=2 ðE Ec Þ3=2 . Therefore, the volume
dpx dpy dpz within which the electron energy lies between E and E þ dE is
4πð2mx my mz Þ1=2 ðE E c Þ1=2 dE. Thus, Eq. (2.1) becomes
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi
8πg 2mx my mz pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 8πg 2m2t ml pffiffiffiffiffiffiffiffiffiffiffiffiffiffi
N ðE ÞdE ¼ E E c dE ¼ E E c dE: (2.3)
h3 h3
12 2 Basic Device Physics
Figure 2.2 Schematic plots of density of states, Fermi–Dirac distribution function, and their
products versus electron energy in a band diagram (after Sze, 1981)
The 3-D electron density of states in an energy diagram is then a parabolic function
with its downward apex at the conduction-band edge, and vice versa for the hole
density of states in the valence band. These are shown schematically in Figure 2.2
(Sze, 1981).
and
Equation (2.6) should be interpreted as stating that the probability of finding a hole
(i.e., an empty state not occupied by an electron) at an energy E < Ef is eðEf EÞ=kT .
The last two equations follow directly from Maxwell–Boltzmann statistics for clas-
sical particles, which are good approximations to Fermi–Dirac statistics when the
energy is at least several kT away from E f .
Fermi level plays an essential role in characterizing the equilibrium state of a
system. Consider two electronic systems brought into contact with Fermi levels E f 1
and E f 2 , and corresponding distribution functions f D1 ðEÞ and f D2 ðEÞ. If Ef 1 > E f 2 ,
then f D1 ðEÞ > f D2 ðE Þ, which means that at every energy E where electronic states
are available in both systems, a larger fraction of the states in system 1 are occupied
by electrons than those in system 2. Equivalently, a larger fraction of the states in
system 2 are empty than those in system 1 at energies where electronic states exist.
Since the two systems in contact are free to exchange electrons, there is a higher
probability for the electrons in system 1 to redistribute to system 2 than vice versa.
This leads to a net electron transport from system 1 to system 2, i.e., current flows
(defined in terms of positive charges) from system 2 to system 1. If there are no
power sources connected to the systems to sustain the Fermi level imbalance,
eventually the two systems will come to an equilibrium and E f 1 ¼ E f 2 . No further
net electron flow takes place once the same fractions of the electronic states in the
two systems are occupied at every energy E. Note that this conclusion is reached
regardless of the specific density of states in each of the two systems. For example,
the two systems can be two metals, a metal and a semiconductor, or two semicon-
ductors of different doping or different composition. When two systems are in
thermal equilibrium with no current flow between them, their Fermi levels must
be equal. A direct extension is that, for a continuous region of metals and/or
semiconductors in contact, the Fermi level at thermal equilibrium is flat, i.e.,
spatially constant, throughout the region. The role of Fermi level at the contacts
when there is an applied voltage driving a steady-state current is further discussed in
Section 2.4.2.
Here the upper limit of integration is taken as infinity because the top of the
conduction band is far above Ec . Both the product N ðE ÞfD ðE Þ and n, p are shown
schematically in Figure 2.2. Equation (2.7) with the full Fermi–Dirac distribution
function, Eq. (2.4), is discussed in Section 2.2.3. For nondegenerate silicon with a
Fermi level at least 3kT/q below E c , the Fermi–Dirac distribution function can be
approximated by the Maxwell–Boltzmann distribution, Eq. (2.5). Equation (2.7) then
becomes
pffiffiffiffiffiffiffiffiffiffiffiffiffi Z
8πg 2m2t ml ∞ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðEEf Þ=kT
n¼ E Ec e dE: (2.8)
h3 Ec
With a change of variable, the integral can be expressed in the form of a gamma
function, Γð3=2Þ, which equals π 1=2 =2. The electron concentration in the conduction
band is then
where N v is the effective density of states of the valence band, which depends on
the hole effective mass and the valence band degeneracy. Both N c and N v are
proportional to T 3=2 . Their values at room temperature are listed in Table 2.1
(Green, 1990).
For an intrinsic silicon, n ¼ p, since for every electron excited into the conduction
band, a vacancy or hole is left behind in the valence band. The Fermi level for intrinsic
silicon, or the intrinsic Fermi level, E i , is then obtained by equating Eqs. (2.9) and
(2.11) and solving for E f :
Ec þ E v kT Nc
Ei ¼ Ef ¼ ln : (2.12)
2 2 Nv
By substituting Eq. (2.12) for E f in Eq. (2.9) or Eq. (2.11), the intrinsic carrier
concentration, ni ¼ n ¼ p is obtained:
pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
ni ¼ N c N v eðEc Ev Þ=2kT ¼ N c N v eEg =2kT : (2.13)
Since the thermal energy, kT, is much smaller than the silicon bandgap, E g , and
ln ½N c =N v is not a large number, the intrinsic Fermi level is very close to the
midpoint between the conduction band and the valence band. In fact, E i is some-
times referred to as the midgap energy level, since the error in assuming E i to be
ðEc þ E v Þ=2 is only about 0.3 kT. The intrinsic carrier concentration, ni, at room
2.2 n-Type and p-Type Silicon 15
temperature is 1:0 1010 cm3 , as given in Table 2.1. This is very small compared
with the atomic density of silicon.
Equations (2.9) and (2.11) can be rewritten in terms of ni and Ei :
These equations give the equilibrium electron and hole densities for any Fermi level
position (not too close to the band edges) relative to the intrinsic Fermi level at the
midgap. In Section 2.2, we will show how the Fermi level varies with the type and
concentration of impurity atoms in silicon. Since any change in Ef causes reciprocal
changes in n and p, a useful, general relationship is that the product
pn ¼ n2i (2.16)
Figure 2.3 Three basic bond pictures of silicon: (a) intrinsic Si with no impurities, (b) n-type
silicon with donor (phosphorus), (c) p-type silicon with acceptor (boron) (after Sze, 1981)
Figure 2.4 Energy-band diagram representation of (a) donor level E d and Fermi level E f in n-type
silicon, (b) acceptor level Ea and Fermi level E f in p-type silicon
free-moving hole that contributes to electrical conduction. These impurities are called
acceptors; they become negatively charged when ionized. Silicon material doped with
column-III impurities or acceptors is called p-type silicon, and its electrical conduct-
ivity is dominated by holes in the valence band. It should be noted that impurity atoms
must be in a substitutional site (as opposed to interstitial) in silicon in order to be
electrically active.
In terms of the energy-band diagrams in Figure 2.4, donors add allowed electron
states in the bandgap close to the conduction-band edge, while acceptors add allowed
states just above the valence-band edge. Donor levels contain positive charge when
ionized (emptied). Acceptor levels contain negative charge when ionized (filled). The
2.2 n-Type and p-Type Silicon 17
Figure 2.5 Donor and acceptor levels of various impurities in silicon. Numbers next to the level
indicate ionization energies E c Ed (donors) or Ea E v (acceptors) in electron volts (after Sze,
1981)
n ¼ Nþ
d þ p, (2.17)
where N þ
d is the density of ionized donors given by
!
1
Nþ
d ¼ N d ½1 fD ðE d Þ ¼ N d 1 , (2.18)
1 þ 12 eðEd Ef Þ=kT
since the probability that a donor state is occupied by an electron (i.e., in the neutral
state) is fD ðEd Þ. The factor 12 in the denominator of fD ðE d Þ arises from the spin
degeneracy (up or down) of the available electronic states associated with an ionized
18 2 Basic Device Physics
Figure 2.6 Solid solubility of various elements in silicon as a function of temperature (after
Trumbore, 1960)
donor level1 (Ghandhi, 1968). In other words, while a neutral donor atom has only one
electron to lose, a positively charged donor atom can recapture an electron in one of its
two possible states. Substituting Eqs. (2.9) and (2.11) for n and p in Eq. (2.17) obtains
Nd
N c eðEc Ef Þ=kT ¼ þ N v eðEf Ev Þ=kT , (2.19)
1 þ 2eðEd Ef Þ=kT
which is an algebraic equation that can be solved for Ef . In n-type silicon, electrons
are the majority current carriers, while holes are the minority current carriers, which
means that the second term on the right-hand side (RHS) of Eq. (2.19) can be
neglected. For shallow donor impurities with low-to-moderate concentration at room
temperature, ðN d =N c Þ exp½ðE c E d Þ=kT 1, a good approximate solution for E f is
1
Detailed study showed that there is no other degeneracy with the electronic ground state in a donor except
for the spin (Ning and Sah, 1971).
2.2 n-Type and p-Type Silicon 19
Nc
E c E f ¼ kT ln : (2.20)
Nd
In this case, the Fermi level is at least a few kT below E d and essentially all the donor
levels are empty (ionized), i.e., n ¼ N þ d ¼ Nd.
It was shown in Eq. (2.16) that, in equilibrium, the product of majority and
minority carrier densities equals n2i , independent of the dopant type and Fermi level
position. The minority hole density in n-type silicon is then given by
p ¼ n2i =N d : (2.21)
Likewise, for p-type silicon with a shallow acceptor concentration, N a , the Fermi level
is given by
Nv
E f Ev ¼ kT ln , (2.22)
Na
n ¼ n2i =N a : (2.23)
Figure 2.7 plots the Fermi level position in the energy gap versus temperature for a
wide range of impurity concentration (Grove, 1967). The slight variation of the silicon
bandgap with temperature is also incorporated in the figure. It is seen that as the
temperature increases, the Fermi level approaches the intrinsic value near midgap.
When the intrinsic carrier concentration becomes larger than the doping concentration,
Figure 2.7 The Fermi level in silicon as a function of temperature for various levels of impurity
concentration (after Grove, 1967)
20 2 Basic Device Physics
for p-type silicon. In other words, the distance between the Fermi level and the
intrinsic Fermi level near the midgap is a logarithmic function of doping concen-
tration. These expressions will be used extensively throughout the book.
This integral cannot be carried out analytically. In terms of the Fermi–Dirac integral
defined by
Z ∞ pffiffiffi
y
F 1=2 ðuÞ dy, (2.27)
0 1þe
yu
100
eu
2
10
1
F1/2(u)
0.1
0.01
0.001
0.0001
–10 –5 0 5 10
u
Figure 2.8 Fermi–Dirac integral of the order ½. The dotted line depicts Boltzmann approximation
valid for u << 1
where the effective density of states N c is given by Eq. (2.10). A numerical plot of the
Fermi–Dirac integral is shown in Figure 2.8. Its asymptotic approximations are
(Blakemore, 1982)
8 pffiffiffi
>
> π u
< e for u 1
2
F 1=2 ðuÞ (2.29)
>
>
: 2 u3=2 for u 1
3
. Ec Ef
Note that in the non-degenerate limit where kT, Eq. (2.28) is reduced to
Eq. (2.9).
Another effect with heavily doped silicon is bandgap narrowing. When the
impurity concentration is higher than 1017 cm3 , the donor (or acceptor) levels start
to broaden into bands. This results in an effective decrease in the ionization energy
until finally the impurity band merges with the conduction (or valence) band and the
ionization energy becomes zero. Bandgap narrowing has a nonnegligible effect in
bipolar devices and is discussed in more detail in Section 9.1.1.2.
Carrier transport which gives rise to current flow in silicon is driven by two different
mechanisms: (a) the drift of carriers, caused by the presence of an electric field, and (b)
the diffusion of carriers, caused by an electron or hole concentration gradient in
silicon. They are discussed in this section.
22 2 Basic Device Physics
vd ¼ qE τ=m∗ : (2.30)
τ is related to the mean free path l, the average distance carriers travel between
collisions, through τ ¼ l=vth . Typically, l 10 nm, τ 0:1 ps. This establishes that,
at low electric fields, the drift velocity vd is proportional to the electric field strength E
with a proportionality constant μ, defined as the mobility, i.e.,
vd ¼ μE , (2.31)
with
qτ ql
μ¼ ¼ : (2.32)
m∗ m∗ vth
Electron and hole mobilities in silicon at low impurity concentrations are listed in
Table 2.1. The electron mobility is approximately three times the hole mobility, since
the effective mass of electrons in the conduction band is much lighter than that of
holes in the valence band.
Figure 2.9 plots the electron and hole mobilities at room temperature versus n-type
or p-type doping concentration. At low impurity levels, the mobilities are mainly
limited by carrier collisions with the silicon lattice or acoustic phonons (Kittel, 1976).
As the doping concentration increases beyond 1015 1016 =cm3 , collisions with the
charged (ionized) impurity atoms through Coulomb interaction become more and
more important and the mobilities decrease. In general, one can use Matthiessen’s rule
to include different contributions to the mobility:
1 1 1
¼ þ þ , (2.33)
μ μL μI
The fiery breath of our intelligence is gathered, as are the matter and
the humours of our organism, into the inexhaustible reservoir which
produced them, as one day the earth and the heavens will be
gathered thither also. All must be engulfed in one whole, must lose
itself in one forgetfulness. When man has reached the term of his
fate, he faints into the one power which forms and leads the
universe, just as the tired stars will be extinguished in it, when their
days shall be accomplished. Resistance to the supreme law is vain
and painful; rebellion against the irresistible order of things is
impious. The great virtue taught by Stoicism is that of submission to
the fatality which guides the world, of joyous acceptance of the
inevitable. Philosophic literature and the epitaphs present to us,
repeatedly and in a thousand forms, the idea that we cannot strive
against omnipotent necessity, that the rule of this rigid master must
be borne without tears or recriminations. The wise man, who
destroys within himself desire of any happenings, enjoys even during
this existence divine calm in the midst of tribulations, but those
whom the vicissitudes of life drive or attract, who let illusions seduce
or grieve them, will at last obtain remission of their troubles when
they reach the tranquil haven of death. This thought is expressed by
a distich which often recurs on tombs, in Greek and in Latin. “I have
fled, escaped. Farewell, Hope and Fortune. I have nothing more to do
with you. Make others your sport.”[47]
Stoic determinism found support in the astrology which originated
in Babylonia and was transplanted to Egypt, and which spread in the
Graeco-Latin world from the second century B. C. onwards,
propagating its mechanical and fatalistic conception of the universe.
According to this pseudo-science, all physical phenomena depended
absolutely, like the character and acts of men, on the revolutions of
the celestial bodies. Thus all the forces of nature and the very energy
of intelligence acted in accordance with an inflexible necessity.
Hence worship had no object and prayer no effect. In this way the
sidereal divination, which had grown up in the temples of the East,
ended in Greece, among certain of its adepts, in a negation of the
very basis of religion.[48] It is noteworthy that in the writings left to us
there is hardly an allusion to the immortality of the soul. When they
speak of what comes after death there is question only of funerals
and posthumous glory. We never find in them a promise to the
unfortunate, weighed down by misadventure and infirmities, of
consolation or compensation in the Beyond. The systematic astrology
of the Greeks limits its horizon to this world, although traces of the
belief in Hades subsist in its vocabulary and its predictions and
although this same astral divination inspired in the mysteries certain
eschatological theories, as we shall see later.[49]
Ethnology has proved that among all peoples the belief that the
dead continue to live in the tomb has reigned, and sometimes still
reigns. The primitive man, disconcerted by death, cannot persuade
himself that the being who moved, felt, willed, as he does, can be
suddenly deprived of all his faculties. The most ancient and the
crudest idea is that the corpse itself keeps some obscure
sensitiveness which it cannot manifest. It is imagined to be in a state
like sleep. The vital energy which animated the body is still attached
to it and cannot exist without it. This belief was so powerful in Egypt
that it inspired a whole section of the funeral ritual and called forth
the infinite care that was taken to preserve mummies. Even in the
West it survived vaguely, and traces of it might still be discovered
today. Lucretius combats this invincible illusion of men who, even
while they affirm that death extinguishes all feeling, keep a secret
uneasiness as to the suffering which their mortal remains may
undergo and are frightened by the idea that their bodies may be
eaten by worms or carnivorous animals. They cannot separate
themselves from this prone body, which they believe is still their self.
Why, continues the poet, would it be more painful to be the prey of
wild beasts than to be burnt by the flame of the pyre, to freeze lying
on the icy slab of the grave or to be crushed by the weight of heaped-
up earth?[102] This very fear that the earth may weigh heavily on those
who are deposited in the grave shows itself among many peoples who