Chapter 6

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 6 <1>
Ravi’s birds eye view: Progress from both sides of the chunnel

First 4 weeks of course:

basic circuit elements

Week 5 onwards: Assembly

Language Programming

Chapter 6 <2>
 Chapter 6 :: Topics
• Introduction
• Assembly Language
• Machine Language
• Programming
• Addressing Modes
• Lights, Camera, Action: Compiling,
Assembling, & Loading
• Odds and Ends

Chapter 6 <3>
 Introduction
• Jumping up a few levels Application
Software
programs

of abstraction Operating
Systems
device drivers

• Architecture: Architecture
instructions
registers

programmer’s view of Micro-

architecture
datapaths
controllers
computer adders
Logic
– Defined by instructions & memories

Digital AND gates

operand locations Circuits NOT gates

• Microarchitecture: how Analog

Circuits
amplifiers
filters

to implement an Devices
transistors
diodes
architecture in hardware Physics electrons
(covered in Chapter 7)
Chapter 6 <4>
 Assembly Language
• Instructions: commands in a computer’s
language
– Assembly language: human-readable format of
instructions
– Machine language: computer-readable format
(1’s and 0’s)
• MIPS architecture:
– Developed by John Hennessy and his colleagues at
Stanford and in the 1980’s.
– Used in many commercial systems, including
Silicon Graphics, Nintendo, and Cisco

Once you’ve learned one architecture, it’s easy to learn others

Chapter 6 <5>
 John Hennessy
• President of Stanford University
• Professor of Electrical Engineering
and Computer Science at Stanford
since 1977
• Coinvented the Reduced
Instruction Set Computer (RISC)
with David Patterson
• Developed the MIPS architecture at
Stanford in 1984 and cofounded
MIPS Computer Systems
• As of 2004, over 300 million MIPS
microprocessors have been sold

Chapter 6 <6>
 Ravi Rao added: from zybooks

2.1 Programmable processor concept

Chapter 6 <7>
Ravi Rao added (FYI)

Both from Wikipedia

CPU and memory are distinct

Human brain architecture:

Decentralized. No specific region is the CPU or memory.

Chapter 6 <8>
Server in Dr. Rao’s office

Memory

CPU is under this fan (heat sink)

Chapter 6 <9>
 (Ravi Rao added) Google Server Farm

Douglas county

Chapter 6 <10>
 Architecture Design Principles
Underlying design principles, as articulated by
Hennessy and Patterson:
1.Simplicity favors regularity
2.Make the common case fast
3.Smaller is faster
4.Good design demands good compromises

Chapter 6 <11>
 Instructions: Addition

C Code MIPS assembly code

a = b + c; add a, b, c

• add: mnemonic indicates operation to perform

• b, c: source operands (on which the operation is
performed)
• a: destination operand (to which the result is written)

Chapter 6 <12>
 Instructions: Subtraction
• Similar to addition - only mnemonic changes

C Code MIPS assembly code

a = b - c; sub a, b, c

• sub: mnemonic
• b, c: source operands
• a: destination operand

Chapter 6 <13>
Design Principle 1
Simplicity favors regularity
• Consistent instruction format
• Same number of operands (two sources and
one destination)
• Easier to encode and handle in hardware

Chapter 6 <14>
 Multiple Instructions
• More complex code is handled by multiple
MIPS instructions.
C Code MIPS assembly code
a = b + c - d; add t, b, c # t = b + c
sub a, t, d # a = t - d

Chapter 6 <15>
Design Principle 2
Make the common case fast
• MIPS includes only simple, commonly used instructions
• Hardware to decode and execute instructions can be
simple, small, and fast
• More complex instructions (that are less common)
performed using multiple simple instructions
• MIPS is a reduced instruction set computer (RISC), with
a small number of simple instructions
• Other architectures, such as Intel’s x86, are complex
instruction set computers (CISC)

Chapter 6 <16>
 Operands
• Operand location: physical location in
computer
– Registers
– Memory
– Constants (also called immediates)

Chapter 6 <17>
 Operands: Registers
• MIPS has 32 32-bit registers
• Registers are faster than memory
• MIPS called “32-bit architecture” because
it operates on 32-bit data

Chapter 6 <18>
Design Principle 3
Smaller is Faster
• MIPS includes only a small number of
registers

Chapter 6 <19>
MIPS Register Set
Name Register Number Usage
$0 0 the constant value 0
$at 1 assembler temporary
$v0-$v1 2-3 Function return values
$a0-$a3 4-7 Function arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved variables
$t8-$t9 24-25 more temporaries
$k0-$k1 26-27 OS temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 Function return address

Chapter 6 <20>
 Operands: Registers
• Registers:
– $ before name
– Example: $0, “register zero”, “dollar zero”
• Registers used for specific purposes:
• $0 always holds the constant value 0.
• the saved registers, $s0-$s7, used to hold
variables
• the temporary registers, $t0 - $t9, used to
hold intermediate values during a larger
computation
• Discuss others later

Chapter 6 <21>
 Dr. Rao’s note:
• These slides and the text-book use registers
named $t0, $t1, $t2 etc. and also $s0, $s1, $s2
etc. This is the original and complete MIPS
architecture and instruction set.
• MIPSzy is a subset of the original MIPS. Hence
it uses only registers named $t0, $t1, $t2 etc.
• When you write code in the MIPS ZyBooks
simulator (section 3.10), you cannot use $s0, $s1,
$s2 etc.
• The code in these slides will work with a full
MIPS processor. Hence they are retained for
instructional purposes.
Chapter 6 <22>
 Instructions with Registers
• Revisit add instruction

C Code MIPS assembly code

# $s0 = a, $s1 = b, $s2 = c
a = b + c add $s0, $s1, $s2

Chapter 6 <23>
 Operands: Memory
• Too much data to fit in only 32 registers
• Store more data in memory
• Memory is large, but slow
• Commonly used variables kept in registers

Chapter 6 <24>
 Word-Addressable Memory
• Each 32-bit data word has a unique
address
Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

Note: MIPS uses byte-addressable memory, which we’ll talk about next.

Chapter 6 <25>
Ravi Rao addition:

What is the importance of zero?

Why bother?

Chapter 6 <26>
 Ravi Rao addition:
https://en.wikipedia.org/wiki/0
The number 0 fulfills a central role in mathematics as the additive identity of
the integers, real numbers, and many other algebraic structures.
India and Southeast Asia
Pingala (c. 3rd/2nd century BC[24]), a Sanskrit prosody scholar,[25] used binary
numbers in the form of short and long syllables (the latter equal in length to two
short syllables), a notation similar to Morse code.[26] Pingala used
the Sanskrit word śūnya explicitly to refer to zero.[27]
The number zero appeared in the Bakhshali manuscript, which appears to be a
training manual for Buddhist monks. Recent carbon dating showed that the oldest
pages are between 224 and 383 AD which would make it the oldest recorded
example of a zero.[28]
Aryabhatta: Place value system and zero
The place-value system, first seen in the 3rd-century Bakhshali Manuscript, was
clearly in place in his work. While he did not use a symbol for zero, the French
mathematician Georges Ifrah argues that knowledge of zero was implicit in
Aryabhata's place-value system as a place holder for the powers of ten
with null coefficients.[14]

Chapter 6 <27>
 Reading Word-Addressable Memory
• Memory read called load
• Mnemonic: load word (lw)
• Format:
lw $s0, 5($t1)
• Address calculation:
– add base address ($t1) to the offset (5)
– address = ($t1 + 5)
• Result:
– $s0 holds the value at address ($t1 + 5)

Any register may be used as base address

Chapter 6 <28>
 Reading Word-Addressable Memory
• Example: read a word of data at memory
address 1 into $s3
– address = ($0 + 1) = 1
– $s3 = 0xF2F1AC07 after load
Assembly code
lw $s3, 1($0) # read memory word 1 into $s3

Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0
Chapter 6 <29>
 Writing Word-Addressable Memory
• Memory write are called store
• Mnemonic: store word (sw)

Chapter 6 <30>
 Writing Word-Addressable Memory
• Example: Write (store) the value in $t4
into memory address 7
– add the base address ($0) to the offset (0x7)
– address: ($0 + 0x7) = 7
Offset can be written in decimal (default) or hexadecimal
Assembly code
sw $t4, 0x7($0) # write the value in $t4
# to memory word 7
Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0
Chapter 6 <31>
 Byte-Addressable Memory
• Each data byte has unique address
• Load/store words or single bytes: load byte (lb) and
store byte (sb)
• 32-bit word = 4 bytes, so word address increments by 4

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes

Chapter 6 <32>
 Reading Byte-Addressable Memory
• The address of a memory word must now
be multiplied by 4. For example,
– the address of memory word 2 is 2 × 4 = 8
– the address of memory word 10 is 10 × 4 = 40
(0x28)
• MIPS is byte-addressed, not word-
addressed

Chapter 6 <33>
 Reading Byte-Addressable Memory
• Example: Load a word of data at memory
address 4 into $s3.
• $s3 holds the value 0xF2F1AC07 after
load
MIPS assembly code
lw $s3, 4($0) # read word at address 4 into $s3

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes
Chapter 6 <34>
 Writing Byte-Addressable Memory
• Example: stores the value held in $t7
into memory address 0x2C (44)

MIPS assembly code

sw $t7, 44($0) # write $t7 into address 44

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes

Chapter 6 <35>
Design Principle 4
Good design demands good compromises
• Multiple instruction formats allow flexibility
- add, sub: use 3 register operands
- lw, sw: use 2 register operands and a constant
• Number of instruction formats kept small
- to adhere to design principles 1 and 3
(simplicity favors regularity and smaller is
faster).

Chapter 6 <36>
 Operands: Constants/Immediates
• lw and sw use constants or immediates
• immediately available from instruction
• 16-bit two’s complement number
• addi: add immediate
• Subtract immediate (subi) necessary?

C Code MIPS assembly code

# $s0 = a, $s1 = b
a = a + 4; addi $s0, $s0, 4
b = a – 12; addi $s1, $s0, -12

Chapter 6 <37>
 Ravi Rao added
A very simple architecture can perform complex computations:
this is explored via the concept of a Turing machine

https://en.wikipedia.org/wiki/Turing_machine
A Turing machine is a mathematical model of computation that
defines an abstract machine[1] which manipulates symbols on a
strip of tape according to a table of rules.[2] Despite the model's
simplicity, given any computer algorithm, a Turing machine can be
constructed that is capable of simulating that algorithm's logic.[3]

http://web.cecs.pdx.edu/~black/CS311/Lecture%20Notes/Lecture%2011.pdf
Chapter 6 <38>
 Ravi Rao added: Immersive in-classroom coding
Before you start writing code, remember to do the following:

1. Draw a flowchart.
2. Every line of code must be preceded by a comment (use the ‘#’ character)
3. Describe in plain English what you want the line of code to do.
4. Be extremely precise. Do not say
# store register in memory.
This is not precise enough. Which register are you talking about? Which memory
location or address should the content of this register be stored in?

4. Be sure to understand the instruction you are using. Find out how many operands
are required for the instruction. You may look up the instruction format in one of the
following locations:
i) Harris_Harris_Digital_Design_and_Computer_Architecture_Appendix_Only.pdf
(uploaded to webcampus).
ii) MIPS_Instruction_Reference.pdf (uploaded to webcampus)
iii) zyBooks

5. Be patient. All this is going to take time.

Chapter 6 <39>
 Branching
• Execute instructions out of sequence
• Types of branches:
– Conditional
• branch if equal (beq)
• branch if not equal (bne)
– Unconditional
• jump (j)
• jump register (jr)
• jump and link (jal)

Chapter 6 <40>
Review: The Stored Program
Assembly Code Machine Code
lw $t2, 32($0) 0x8C0A0020
add $s0, $s1, $s2 0x02328020
addi $t0, $s3, -12 0x2268FFF4
sub $t0, $t3, $t5 0x016D4022

Stored Program
Address Instructions

0040000C 0 1 6 D 4 0 2 2
00400008 2 2 6 8 F F F 4
00400004 0 2 3 2 8 0 2 0
00400000 8 C0 A0 0 2 0 PC

Main Memory
Chapter 6 <41>
 Conditional Branching (beq)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1, $s1, 2 # $s1 = 1 << 2 = 4
beq $s0, $s1, target # branch is taken
addi $s1, $s1, 1 # not executed
sub $s1, $s1, $s0 # not executed

target: # label
add $s1, $s1, $s0 # $s1 = 4 + 4 = 8

Labels indicate instruction location. They can’t be reserved words and

must be followed by colon (:)

Chapter 6 <42>
The Branch Not Taken (bne)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1, $s1, 2 # $s1 = 1 << 2 = 4
bne $s0, $s1, target # branch not taken
addi $s1, $s1, 1 # $s1 = 4 + 1 = 5
sub $s1, $s1, $s0 # $s1 = 5 – 4 = 1

target:
add $s1, $s1, $s0 # $s1 = 1 + 4 = 5

Chapter 6 <43>
 Unconditional Branching (j)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 4
addi $s1, $0, 1 # $s1 = 1
j target # jump to target
sra $s1, $s1, 2 # not executed
addi $s1, $s1, 1 # not executed
sub $s1, $s1, $s0 # not executed
Ravi note: sra = shift right arithmetic
target:
add $s1, $s1, $s0 # $s1 = 1 + 4 = 5

Hugely important:
Always indent your code as shown, but do not indent the
labels (e.g. “target”)

Chapter 6 <44>
Unconditional Branching (jr)
# MIPS assembly
0x00002000 addi $s0, $0, 0x2010
0x00002004 jr $s0
0x00002008 addi $s1, $0, 1
0x0000200C sra $s1, $s1, 2
0x00002010 lw $s3, 44($s1)

jr is an R-type instruction.

Chapter 6 <45>
 High-Level Code Constructs
• if statements
• if/else statements
• for loops

Chapter 6 <46>
 If Statement

C Code MIPS assembly code

# $s0 = f, $s1 = g, $s2 = h
# $s3 = i, $s4 = j
if (i == j)
f = g + h;

f = f – i;

Chapter 6 <47>
 If Statement

C Code MIPS assembly code

# $s0 = f, $s1 = g, $s2 = h
# $s3 = i, $s4 = j
if (i == j) bne $s3, $s4, L1
f = g + h; add $s0, $s1, $s2

f = f – i; L1: sub $s0, $s0, $s3

Assembly tests opposite case (i != j) of high-level code (i == j)

Chapter 6 <48>
 Ravi inserted: Flowchart bne $s3, $s4, L1
Yes
I == J ? No I != J ?
This means I ==J
f=g+h No f=g+h

Yes

f=f-i f=f-i
C Code MIPS assembly code
if (i == j) # $s0 = f, $s1 = g, $s2 = h
f = g + h; # $s3 = i, $s4 = j
bne $s3, $s4, L1
f = f – i; add $s0, $s1, $s2

L1: sub $s0, $s0, $s3

 If/Else Statement

C Code MIPS assembly code

if (i == j)
f = g + h;
else
f = f – i;

Chapter 6 <50>
 If/Else Statement

C Code MIPS assembly code

# $s0 = f, $s1 = g, $s2 = h
# $s3 = i, $s4 = j
if (i == j) bne $s3, $s4, L1
f = g + h; add $s0, $s1, $s2
else j done
f = f – i; L1: sub $s0, $s0, $s3
done:

Ravi qs: Why do we have a jump

instruction, “j done?”

Chapter 6 <51>
 Ravi: Immersive coding: If/Else Statement

Run zyBooks MIPS simulator in section 3.10

C Code Use the li (load immediate) operation to
create the following values:
f = 10, g = 20, h = 30 (all decimal)
if (i == j) i = 5, j = 5.
f = g + h;
else MIPS assembly code
f = f – i; # $s0 = f, $s1 = g, $s2 = h
# $s3 = i, $s4 = j
bne $s3, $s4, L1
add $s0, $s1, $s2
j done
L1: sub $s0, $s0, $s3
done:
Run this code by single stepping through it.

Then change j to 6 and re-run the code. What do you see?

Chapter 6 <52>
 For Loops
for (initialization; condition; loop operation)
statement

• initialization: executes before the loop begins

• condition: is tested at the beginning of each iteration
• loop operation: executes at the end of each iteration
• statement: executes each time the condition is met

Chapter 6 <53>
 For Loops

High-level code MIPS assembly code

// add the numbers from 0 to 9 # $s0 = i, $s1 = sum
int sum = 0;
int i;

for (i=0; i!=10; i = i+1) {

sum = sum + i;
}

Chapter 6 <54>
 For Loops

C Code MIPS assembly code

// add the numbers from 0 to 9
int sum = 0;
int i;

for (i=0; i!=10; i = i+1) {

sum = sum + i;
}

Chapter 6 <55>
 For Loops

C Code MIPS assembly code

// add the numbers from 0 to 9 # $s0 = i, $s1 = sum
int sum = 0; addi $s1, $0, 0
int i; add $s0, $0, $0
addi $t0, $0, 10
for (i=0; i!=10; i = i+1) { for: beq $s0, $t0, done
sum = sum + i; add $s1, $s1, $s0
} addi $s0, $s0, 1
j for
done:

Chapter 6 <56>
 Less Than Comparison

C Code MIPS assembly code

// add the powers of 2 from 1
// to 100
int sum = 0;
int i;

for (i=1; i < 101; i = i*2) {

sum = sum + i;
}

Chapter 6 <57>
 Less Than Comparison

C Code MIPS assembly code

// add the powers of 2 from 1 # $s0 = i, $s1 = sum
// to 100 addi $s1, $0, 0
int sum = 0; addi $s0, $0, 1
int i; addi $t0, $0, 101
loop: slt $t1, $s0, $t0
for (i=1; i < 101; i = i*2) { beq $t1, $0, done
sum = sum + i; add $s1, $s1, $s0
} sll $s0, $s0, 1
sll is shift left logical. j loop
If you shift by 1 bit to done:
the left, it is equivalent
to multiplying the
number by two. $t1 = 1 if i < 101

Chapter 6 <58>
 Arrays
• Access large amounts of similar data
• Index: access each element
• Size: number of elements

Chapter 6 <59>
 Arrays
• 4-element array
• Base address = 0x5000 (address of first element,
array[0])
• First step in accessing an array: load base address into
a register

ZYBooks simulator (Sec 3.10)

Address content
5000 Array[0]
5004 Array[1]
5008 Array[2]
5012 Array[3]
… …

Chapter 6 <60>
 Arrays using For Loops
// C Code
int array[3];
int i;

for (i=0; i < 3; i = i + 1)

array[i] = i;

# MIPS assembly code

# $t0 = array base address, $t1 = i

Chapter 6 <61>
 Arrays Using For Loops
Goal:
Use MIPS assembly code to initialize the first three locations in data
memory to the values 1, 2 and 3. This is a 3-element array of integers.

Approach: Use a for loop to initialize these values.

Steps:

1) First draw a flowchart. Think about what variables you will use.
You will need the address of the first memory location (which is
5000). You also need to know how many elements are in the array
(which is 3).
2) Think about the decision box in the flowchart. What should you
check? (It is the number of elements you have stored. If that
number reaches 3, you are done).
3) As long as you do not reach the limit of 3, you should keep storing
the next required value into memory.
4) Make sure you increment your variables (which are the next
memory location you will use for storage, and the loop variable, i).
Chapter 6 <62>
 Solution
Your solution may be different based on what variables you used and how you
structure your loop. It does not matter as long as you produce the correct
result. You can verify your program by running it in the zyBooks simulator in
3.10

See the next slide. It is best that you do not copy and paste this code. Usually,
you learn very little through copy-and-paste. Write the code yourself. The
sample solution is provided only for reference.

Note that you should always use descriptive comments.

Also note the indentation in the code. It makes it much easier to read.

Chapter 6 <63>
# Simple Array program, written by Ravi Rao, 11/11/21

# Start address of array is 5000,

# stored in $t0.
#
# number of elements is 3, stored in $t1
# The loop variable i is $t2

addi $t0, $zero, 5000

# Number of elements is $t1

addi $t1, $zero, 3

#Initialize loop variable $t2 to 0

addi $t2, $zero, 0

loop:
# if i < 3, $t3 is set to 1
# if i >= 3, $t3 is set to 0
slt $t3, $t2, $t1

beq $t3, $zero, done

# we still have work to do

# store the value of i in memory
sw $t2, 0($t0)

# update i
addi $t2, $t2, 1

#update memory address

addi $t0, $t0, 4

j loop

done:
Common errors (observed by Prof. Rao in various
classes)

If you forget to update the loop variable i, you will keep going through the
loop forever. This is known as an infinite loop. You can check this by using
the single step mode and ensuring that the loop variable is properly
incremented.

If you forget to update the next memory location for storing your data, you
will keep over-writing the existing memory location. Again, you can check
this by using the single step mode.

If you do not check the condition properly in the slt instruction, you will not
get the desired result. This is why it is important to create a flowchart
carefully so you understand how your own program is solving the desired
problem.

Chapter 6 <65>
 ASCII Code
• American Standard Code for Information
Interchange
• Each text character has unique byte
value
– For example, S = 0x53, a = 0x61, A = 0x41
– Lower-case and upper-case differ by 0x20 (32)

Chapter 6 <66>
Cast of Characters

Chapter 6 <67>
 Machine Language
• Binary representation of instructions
• Computers only understand 1’s and 0’s
• 32-bit instructions
– Simplicity favors regularity: 32-bit data &
instructions
• 3 instruction formats:
– R-Type: register operands
– I-Type: immediate operand
– J-Type: for jumping (discuss later)

Chapter 6 <68>
 R-Type
• Register-type
• 3 register operands:
– rs, rt: source registers
– rd: destination register
• Other fields:
– op: the operation code or opcode (0 for R-type instructions)
– funct: the function
with opcode, tells computer what operation to perform
– shamt: the shift amount for shift instructions, otherwise it’s 0

R-Type
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Chapter 6 <69>
 R-Type Examples
Assembly Code Field Values
op rs rt rd shamt funct

add $s0, $s1, $s2 0 17 18 16 0 32

sub $t0, $t3, $t5 0 11 13 8 0 34

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Machine Code
op rs rt rd shamt funct

000000 10001 10010 10000 00000 100000 (0x02328020)

000000 01011 01101 01000 00000 100010 (0x016D4022)

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Note the order of registers in the assembly code:

add rd, rs, rt
Chapter 6 <70>
 I-Type
• Immediate-type
• 3 operands:
– rs, rt: register operands
– imm: 16-bit two’s complement immediate
• Other fields:
– op: the opcode
– Simplicity favors regularity: all instructions have opcode
– Operation is completely determined by opcode

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits

Chapter 6 <71>
 I-Type Examples
Assembly Code Field Values
op rs rt imm

addi $s0, $s1, 5 8 17 16 5

addi $t0, $s3, -12 8 19 8 -12

lw $t2, 32($0) 35 0 10 32

sw $s1, 4($t1) 43 9 17 4
6 bits 5 bits 5 bits 16 bits

Machine Code
Note the differing order of op rs rt imm
registers in assembly and
001000 10001 10000 0000 0000 0000 0101 (0x22300005)
machine codes:
001000 10011 01000 1111 1111 1111 0100 (0x2268FFF4)
addi rt, rs, imm
100011 00000 01010 0000 0000 0010 0000 (0x8C0A0020)
lw rt, imm(rs)
101011 01001 10001 0000 0000 0000 0100 (0xAD310004)
sw rt, imm(rs)
6 bits 5 bits 5 bits 16 bits

Chapter 6 <72>
 Machine Language: J-Type
• Jump-type
• 26-bit address operand (addr)
• Used for jump instructions (j)

J-Type
op addr
6 bits 26 bits

Chapter 6 <73>
Review: Instruction Formats
R-Type
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits

J-Type
op addr
6 bits 26 bits

Chapter 6 <74>
How to look for information: Appendix B, Table B.1, Page 620 of textbook
How to look for information: Appendix B, Table B.2, Page 621 of textbook
 Twos complement of 12 is FFF4
-12 in twos complement
zyBooks also has this in 3.5.
 Programming
• High-level languages:
– e.g., C, Java, Python
– Written at higher level of abstraction
• Common high-level software constructs:
– if/else statements
– for loops
– while loops
– arrays
– function calls

Chapter 6 <79>
 Ada Lovelace, 1815-1852

• Wrote the first computer

program
• Her program calculated
the Bernoulli numbers on
Charles Babbage’s
Analytical Engine
• She was the daughter of
the poet Lord Byron

Chapter 6 <80>
 Power of the Stored Program
• 32-bit instructions & data stored in memory
• Sequence of instructions: only difference
between two applications
• To run a new program:
– No rewiring required
– Simply store new program in memory
• Program Execution:
– Processor fetches (reads) instructions from memory
in sequence
– Processor performs the specified operation

Chapter 6 <81>
The Stored Program
Assembly Code Machine Code
lw $t2, 32($0) 0x8C0A0020
add $s0, $s1, $s2 0x02328020
addi $t0, $s3, -12 0x2268FFF4
sub $t0, $t3, $t5 0x016D4022

Stored Program
Program Counter
Instructions
(PC): keeps track of
Address
current instruction
Same Address sequence in MARS
0040000C 0 1 6 D 4 0 2 2 (see next slide)
00400008 2 2 6 8 F F F 4
00400004 0 2 3 2 8 0 2 0
00400000 8 C0 A0 0 2 0 PC

Main Memory
Chapter 6 <82>
Ravi added

Chapter 6 <83>
 Interpreting Machine Code
• Start with opcode: tells how to parse rest
• If opcode all 0’s
– R-type instruction
– Function bits tell operation
• Otherwise
– opcode tells operation
Machine Code Field Values Assembly Code
op rs rt imm op rs rt imm
(0x2237FFF1) 001000 10001 10111 1111 1111 1111 0001 8 17 23 -15 addi $s7, $s1, -15
2 2 3 7 F F F 1

op rs rt rd shamt funct op rs rt rd shamt funct

(0x02F34022) 000000 10111 10011 01000 00000 100010 0 23 19 8 0 34 sub $t0, $s7, $s3
0 2 F 3 4 0 2 2

Chapter 6 <84>
 Interpreting Machine Code

Machine Code Field Values Assembly Code

op rs rt imm op rs rt imm
(0x2237FFF1) 001000 10001 10111 1111 1111 1111 0001 8 17 23 -15 addi $s7, $s1, -15
2 2 3 7 F F F 1

op rs rt rd shamt funct op rs rt rd shamt funct

(0x02F34022) 000000 10111 10011 01000 00000 100010 0 23 19 8 0 34 sub $t0, $s7, $s3
0 2 F 3 4 0 2 2

Chapter 6 <85>
 Ravi inserted: Two types of conversions

This is hugely important.

This will be a Final Exam problem.
You will be given the table of Op codes and register values.
You will have to do both types of conversions.
You do not need to memorize any values. Just understand the steps involved.
Practice using the material on the next slide.
 Ravi inserted: Useful website

https://www.eg.bucknell.edu/~csci320/mips_web/

Hex machine code from previous slide

Recommended steps for practice:

1. Take the assembly code (instruction)
2. Convert the assembly code into Hex machine code by hand
3. Check your answer using this website
4. Compare the answer against the machine code calculated by MARS (optional)
 Ravi inserted: Useful website

https://www.eg.bucknell.edu/~csci320/mips_web/

Hex machine code from previous slide

Recommended steps for practice:

1. Take the Hex machine code for an instruction (e.g. the previous slide, or your
textbook, or MARS (optional)).
2. Convert the Hex machine code to assembly code (instruction) by hand
3. Check your answer using this website
4. Compare the answer against the instruction in your MARS .asm code (optional)
 Programming
• High-level languages:
– e.g., C, Java, Python
– Written at higher level of abstraction
• Common high-level software constructs:
– if/else statements
– for loops
– while loops
– arrays
– function calls

Chapter 6 <89>
How to Compile & Run a Program
High Level Code

Compiler

Assembly Code

Assembler

Object Files
Object File
Library Files

Linker

Executable

Loader

Memory
Chapter 6 <90>
 Example Program: C Code
int f, g, y; // global variables

int main(void)
{
f = 2;
g = 3;
y = sum(f, g);

return y;
}

int sum(int a, int b) {

return (a + b);
}

Chapter 6 <91>
 Example Program: MIPS Assembly
.data
int f, g, y; // global
f:
g:
y:
int main(void)
.text
{
main:
addi $sp, $sp, -4 # stack frame
sw $ra, 0($sp) # store $ra
f = 2;
addi $a0, $0, 2 # $a0 = 2
g = 3;
sw $a0, f # f = 2
y = sum(f, g); addi $a1, $0, 3 # $a1 = 3
return y; sw $a1, g # g = 3
} jal sum # call sum
sw $v0, y # y = sum()
int sum(int a, int b) { lw $ra, 0($sp) # restore $ra
return (a + b); addi $sp, $sp, 4 # restore $sp
} jr $ra # return to OS
sum:
add $v0, $a0, $a1 # $v0 = a + b
jr $ra # return
Chapter 6 <92>
 FLOWCHARTS
https://en.wikipedia.org/wiki/Flowchart
flowchart-symbols-international-organisation.jpg
 Where are flowcharts used?
• Very widely
• Description of business processes and workflows
• In patent filings
• Even in politics!
• https://www.nytimes.com/2019/03/29/world/europe/brexit-flowchart-
confusion.html
Here’s just a portion of his latest:
https://www.uspto.gov/patents-getting-started/general-information-concerning-patents

What is a Patent?
A patent for an invention is the grant of a property right to the inventor, issued by the United States
Patent and Trademark Office. Generally, the term of a new patent is 20 years from the date on which
the application for the patent was filed in the United States or, in special cases, from the date an earlier
related application was filed, subject to the payment of maintenance fees. U.S. patent grants are
effective only within the United States, U.S. territories, and U.S. possessions. Under certain
circumstances, patent term extensions or adjustments may be available.

This provides an interesting career path for STEM students: Intersection of technology & law

1. Get a STEM degree

2. Go to Law school
3. Pass the Patent Bar exam and Legal bar exam
4. Become a Patent Attorney and make $$$$$
5. Alternately:
1. Get a STEM degree
2. Pass the Patent Bar exam
3. Become a Patent examiner
6. You can always file a patent for your own invention
1. There are fees involved
2. The Patent office will review your application thoroughly
• History of Electricity – developments in the 19th century
• 1827 – Georg Ohm discovers Ohm’s Law, E=I x R, which describes the basic
relationship between Voltage (E), Current (I), and Resistance (R)
• 1831- Michael Faraday discovers electromagnetic induction
• 1888 – Nikola Tesla receives a patent for Alternating Current
transmission
• 1891 – 1895 – George Westinghouse builds world's first commercial AC
system

Georg Ohm Michael Faraday Nikola Tesla George Westinghouse

6
https://patents.google.com/?inventor=ravishankar+rao
https://patents.google.com/patent/US20050110637A1/en?q=alarm&assignee=ibm&inventor=ravishankar+rao

Flow charts
US20050110637A1 Flow charts
US Application
 US20070162505A1
US Application

Method for using

psychological states to
index databases

Inventor:
Guillermo Cecchi,
Ravishankar Rao
Current Assignee: International
Business Machines Corp
 Sample problem: Do this for practice.

Draw a flowchart that describes the different outcomes for a student going through a 4 year college.
You should consider what happens in each year, e.g. does the student pass all courses, fail in one or more
courses or drop out.

Consider this background statistic for the US:

“41% of students graduate from a 4-year college within 4 years”
(source https://educationdata.org/number-of-college-graduates/ and ipeds.gov).

To draw your flowchart

1. visit the website draw.io
2. Use rectangles, diamonds and arrows and text to create your chart
3. The diamond represents a decision. One end is connected to an input. The decision is based on a
question, e.g. “Is it raining?”. The other ends are connected to the answers, e.g. “Yes” or “No”.
4. Complete your flowchart
5. Take a screenshot (use the Snipping tool in Windows or Shift+Command+3 on the Mac)
6. Save it as “Firstname_lastname_flowchart.jpg”.
7. This is for your practice only. You do not need to upload anything to webcampus.
 Chapter 5

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 5 <1>
 Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Number Systems
• Sequential Building Blocks
• Memory Arrays
• Logic Arrays

Chapter 5 <2>
 Introduction
• Digital building blocks:
– Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays,
logic arrays
• Building blocks demonstrate hierarchy,
modularity, and regularity:
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
• Will use these building blocks in Chapter
7 to build a microprocessor
Chapter 5 <3>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
S = 1 0 1
Cout = 1 1 0
1 1 1

S =
Cout =

Chapter 5 <4>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S = 1 0 1 1 0
Cout = 1 1 0 1 0
1 1 1 1 1

S =
Cout =

Chapter 5 <5>
1-Bit Adders
Remember?
Half Full We did this in EENG2286
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1

S = A  B  Cin
Cout = AB + ACin + BCin

Chapter 5 <6>
 Ripple-Carry Adder
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow

A31 B31 A30 B30 A1 B1 A0 B0

Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0

Chapter 5 <7>
 Subtracter
(Inserted by Ravi)

Illustrated on the next slide

Chapter 5 <8>
Subtracter/Subtractor

Symbol Implementation
A B
N
A B
N N
N N This means “1”
-
N +
Carry in is 1.
Y N So you add 1
Y
/ N means “N bits”

Chapter 5 <9>
 Comparator: Review of XOR
(Inserted by Ravi)

Chapter 5 <10>
 Comparator: Review of XNOR
(Inserted by Ravi)

Chapter 5 <11>
Comparator: Equality

Symbol Implementation
A3
B3

A B A2
4 4 B2
Equal
= A1
B1
Equal
A0
B0

Ravi note: This circuit checks for (A0 == B0) AND (A1 == B1) …..

Chapter 5 <12>
 Comparator: Less Than

A B
N N

-
N
[N-1] [N-1] is the MSB.
The bits are numbered from

A<B Bit #0 at the LSB to

Bit #[N-1] at the MSB

Ravi note: see pg. 241

5-<13>
Copyright © 2007 Elsevier
Chapter 5 <13>
 Arithmetic Logic Unit (ALU)

F2:0 Function
A B 000 A&B
N N 001 A|B
010 A+B
ALU 3F 011 not used
N 100 A & ~B
Y 101 A | ~B
110 A-B
111 SLT

Ravi note: Let us assume we want to design

this ALU
Copyright © 2007so that when F2:0 is one of 8 choices, the correct function is implemented. 5-<14>
Elsevier
Chapter 5 <14>
 Multiplexer review
(Inserted Ravi: the next slide is from Chapter 2.
It is covered on pg. 83 of the book)

5-<15>
Copyright © 2007 Elsevier
Chapter 5 <15>
 Multiplexer (Mux)
slide is from Chapter 2.
It is covered on pg. 83 of the book
• Selects between one of N inputs to connect
to output
• log2N-bit select input – control input
• Example: 2:1 Mux
S

D0 0 This is the new symbol we will

Y use in this course for a Mux
D1 1

S D1 D0 Y S Y
0 0 0 0 0 D0
0 0 1 1 1 D1
When S = 0, select D0
0 1 0 0 When S = 1, select D1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1 These tables are equivalent
1 1 1 1

Chapter 5 <16>
 ALU Design
A B
N N F2:0 Function
000 A&B
N
001 A|B
1

0 F2
N 010 A+B
011 not used
Cout + 100 A & ~B
[N-1] S
101 A | ~B
Extend
Zero

110 A-B
N N N N
1

0
3

2 F1:0 111 SLT

N
Y 2-bit select, chooses from 4 options
5-<17>
Copyright © 2007 Elsevier
Chapter 5 <17>
 ALU Design: Ravi’s explanation
Take one path at a time: say F2 = 0: selects B (green path)
A B
N N F2:0 Function
000 A&B
N
001 A|B Logical OR
1

0
F2
N 010 A+B Addition

B 011 not used

Cout + 100 A & ~B
[N-1] S
A |B
A&B
101 A | ~B
Extend

A+B
Zero

110 A-B
N N N N
1

0
3

2 F1:0 111 SLT

N
Y 2-bit select, chooses from 4 options
Copyright © 2007 Elsevier
Say F1=1 and F2 =Chapter
0: we5 select
<18> input 2, ie A+B 5-<18>
 ALU Design: Ravi’s explanation
Take one path at a time and verify this table for homework. (SLT is on next slide)
A B
N N F2:0 Function
000 A&B
N 001 A|B
1

0
F2
N
010 A+B
011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N
2-bit select, chooses from 4 options
Y
Chapter 5 <19>
5-<19>
 Ravi’s explanation
(for two’s complement, see Subtracter slide)
SLT: When F2 =1, watch what happens: you compute A – B (two’s complement).
The adder receives a Carry-in of 1 (which is F2). The output has sign 0 if A >= B, 1 if A < B
A B
N N F2:0 Function
000 A&B

Note that the MSB is Bit #[N-1].

N
1 001 A|B
0
This unit just pads Bit #[N-1] F2
ie the sign bit (the MSB) with N
010 A+B
zeros to the left.
Because the output Y has N bits. 011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

Example on next slide

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N 2-bit select, chooses from 4 options
Y

So if F1 = 1 and F0 = 1, we have Y = 00000000(N bits) when A >= B

or Y = 00000001(N bits) when A < B. That is what this means:
Set Y (ie make Y = 1) when A < B
 Chapter 5

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 5 <1>
 Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Number Systems
• Sequential Building Blocks
• Memory Arrays
• Logic Arrays

Chapter 5 <2>
 Introduction
• Digital building blocks:
– Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays,
logic arrays
• Building blocks demonstrate hierarchy,
modularity, and regularity:
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
• Will use these building blocks in Chapter
7 to build a microprocessor
Chapter 5 <3>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
S = 1 0 1
Cout = 1 1 0
1 1 1

S =
Cout =

Chapter 5 <4>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S = 1 0 1 1 0
Cout = 1 1 0 1 0
1 1 1 1 1

S =
Cout =

Chapter 5 <5>
1-Bit Adders
Remember?
Half Full We did this in EENG2286
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1

S = A  B  Cin
Cout = AB + ACin + BCin

Chapter 5 <6>
 Ripple-Carry Adder
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow

A31 B31 A30 B30 A1 B1 A0 B0

Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0

Chapter 5 <7>
 Subtracter
(Inserted by Ravi)

Illustrated on the next slide

Chapter 5 <8>
Subtracter/Subtractor

Symbol Implementation
A B
N
A B
N N
N N This means “1”
-
N +
Carry in is 1.
Y N So you add 1
Y
/ N means “N bits”

Chapter 5 <9>
 Comparator: Review of XOR
(Inserted by Ravi)

Chapter 5 <10>
 Comparator: Review of XNOR
(Inserted by Ravi)

Chapter 5 <11>
Comparator: Equality

Symbol Implementation
A3
B3

A B A2
4 4 B2
Equal
= A1
B1
Equal
A0
B0

Ravi note: This circuit checks for (A0 == B0) AND (A1 == B1) …..

Chapter 5 <12>
 Comparator: Less Than

A B
N N

-
N
[N-1] [N-1] is the MSB.
The bits are numbered from

A<B Bit #0 at the LSB to

Bit #[N-1] at the MSB

Ravi note: see pg. 241

5-<13>
Copyright © 2007 Elsevier
Chapter 5 <13>
 Arithmetic Logic Unit (ALU)

F2:0 Function
A B 000 A&B
N N 001 A|B
010 A+B
ALU 3F 011 not used
N 100 A & ~B
Y 101 A | ~B
110 A-B
111 SLT

Ravi note: Let us assume we want to design

this ALU
Copyright © 2007so that when F2:0 is one of 8 choices, the correct function is implemented. 5-<14>
Elsevier
Chapter 5 <14>
 Multiplexer review
(Inserted Ravi: the next slide is from Chapter 2.
It is covered on pg. 83 of the book)

5-<15>
Copyright © 2007 Elsevier
Chapter 5 <15>
 Multiplexer (Mux)
slide is from Chapter 2.
It is covered on pg. 83 of the book
• Selects between one of N inputs to connect
to output
• log2N-bit select input – control input
• Example: 2:1 Mux
S

D0 0 This is the new symbol we will

Y use in this course for a Mux
D1 1

S D1 D0 Y S Y
0 0 0 0 0 D0
0 0 1 1 1 D1
When S = 0, select D0
0 1 0 0 When S = 1, select D1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1 These tables are equivalent
1 1 1 1

Chapter 5 <16>
 ALU Design
A B
N N F2:0 Function
000 A&B
N
001 A|B
1

0 F2
N 010 A+B
011 not used
Cout + 100 A & ~B
[N-1] S
101 A | ~B
Extend
Zero

110 A-B
N N N N
1

0
3

2 F1:0 111 SLT

N
Y 2-bit select, chooses from 4 options
5-<17>
Copyright © 2007 Elsevier
Chapter 5 <17>
 ALU Design: Ravi’s explanation
Take one path at a time: say F2 = 0: selects B (green path)
A B
N N F2:0 Function
000 A&B
N
001 A|B Logical OR
1

0
F2
N 010 A+B Addition

B 011 not used

Cout + 100 A & ~B
[N-1] S
A |B
A&B
101 A | ~B
Extend

A+B
Zero

110 A-B
N N N N
1

0
3

2 F1:0 111 SLT

N
Y 2-bit select, chooses from 4 options
Copyright © 2007 Elsevier
Say F1=1 and F2 =Chapter
0: we5 select
<18> input 2, ie A+B 5-<18>
 ALU Design: Ravi’s explanation
Take one path at a time and verify this table for homework. (SLT is on next slide)
A B
N N F2:0 Function
000 A&B
N 001 A|B
1

0
F2
N
010 A+B
011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N
2-bit select, chooses from 4 options
Y
Chapter 5 <19>
5-<19>
 Ravi’s explanation
(for two’s complement, see Subtracter slide)
SLT: When F2 =1, watch what happens: you compute A – B (two’s complement).
The adder receives a Carry-in of 1 (which is F2). The output has sign 0 if A >= B, 1 if A < B
A B
N N F2:0 Function
000 A&B

Note that the MSB is Bit #[N-1].

N
1 001 A|B
0
This unit just pads Bit #[N-1] F2
ie the sign bit (the MSB) with N
010 A+B
zeros to the left.
Because the output Y has N bits. 011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

Example on next slide

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N 2-bit select, chooses from 4 options
Y

So if F1 = 1 and F0 = 1, we have Y = 00000000(N bits) when A >= B

or Y = 00000001(N bits) when A < B. That is what this means:
Set Y (ie make Y = 1) when A < B
 Chapter 5

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 5 <1>
 Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Number Systems
• Sequential Building Blocks
• Memory Arrays
• Logic Arrays

Chapter 5 <2>
 Introduction
• Digital building blocks:
– Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays,
logic arrays
• Building blocks demonstrate hierarchy,
modularity, and regularity:
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
• Will use these building blocks in Chapter
7 to build microprocessor
Chapter 5 <3>
 ALU Design: Ravi’s explanation
Take one path at a time and verify this table for homework. (SLT is on next slide)
A B
N N F2:0 Function
000 A&B
N 001 A|B
1

0
F2
N
010 A+B
011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N
2-bit select, chooses from 4 options
Y
Chapter 5 <4>
5-<4>
 Ravi’s explanation SLT: Set less than
(for two’s complement, see Subtracter slide)
SLT: When F2 =1, watch what happens: you compute A – B (two’s complement).
The adder receives a Carry-in of 1 (which is F2). The output has sign 0 if A >= B, 1 if A < B
A B
N N F2:0 Function
000 A&B

Note that the MSB is Bit #[N-1].

N
1 001 A|B
0
This unit just pads Bit #[N-1] F2
ie the sign bit (the MSB) with N
010 A+B
zeros to the left.
Because the output Y has N bits. 011 not used
100 A & ~B
Cout +
[N-1] S
101 A | ~B
Extend

Example on next slide

110 A-B
Zero

N N N N
111 SLT
1

0
3

2 F1:0
N 2-bit select, chooses from 4 options
Y
So if F1 = 1 and F0 = 1, we have Y = 00000000(N bits) when A >= B
or Y = 00000001(N bits) when A < B. That is what this means:
Set Y (ie make Y = 1) when A < B
 Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1

0
F2
N

Cout +
[N-1] S
Extend
Zero

N N N N
1

0
3

2 F1:0
N
Y

5-<6>
Copyright © 2007 Elsevier
Chapter 5 <6>
 Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1 – A < B, so Y should be 32-bit
0
F2 representation of 1 (0x00000001)
N
– F2:0 = 111
– F2 = 1 (adder acts as
Cout + subtracter), so 25 - 32 = -7
[N-1] S
– -7 has 1 in the most
Extend

significant bit (S31 = 1)

Zero

N N N N
– F1:0 = 11 multiplexer selects
1

0
3

2 F1:0 Y = S31 (zero extended) =

N
Y
0x00000001.

5-<7>
Copyright © 2007 Elsevier
Chapter 5 <7>
 Shifters
• Logical shifter: shifts value to left or right and fills empty spaces with 0’s
– Ex: 11001 >> 2 =
– Ex: 11001 << 2 =

• Arithmetic shifter: same as logical shifter, but on right shift, fills empty
spaces with the old most significant bit (msb).
– Ex: 11001 >>> 2 =
– Ex: 11001 <<< 2 =

• Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
– Ex: 11001 ROR 2 =
– Ex: 11001 ROL 2 =

5-<8>
Copyright © 2007 Elsevier
Chapter 5 <8>
 Shifters
• Logical shifter:
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter:
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator:
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111

Chapter 5 <9>
Shifter Design
A 3 A 2 A1 A0 shamt1:0
2
00 S1:0
01

10
Y3

shamt1:0 11

2 00
S1:0
01
Y2
A3:0 4 >> 4 Y3:0
10

11

00
S1:0
01

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <10>
 Shifter Design: Ravi’s explanation
Note: connections do not have a “dot” A 3 A 2 A1 A0 shamt1:0
They are staggered. 2
00 S1:0
I prefer to have a “dot” 01
Y3 =0
10

shamt1:0 11

2 00
S1:0
01
Y2
A3:0 4 >> 4 Y3:0
10

11

00
S1:0
01
Y1
Say shamt=shift amount is 01 10

11
So we shift to the right by 1.
00
S1:0
A3 A2 A1 A0 → 0 A3 A2 A1 01

10
Y0 = A1
Y3 Y2 Y1 Y0 11

Similarly verify all the other combinations for shamt (homework)

Chapter 5 <11>
 Fairleigh Dickinson University
Gildart Haase School of Computer Sciences and Engineering
Metropolitan Campus, Teaneck, NJ
Course Syllabus

1. Course: EENG2287/EGTG2287 Microprocessors System Design l

Semester: Fall Year: 2024 Credits: 3 Contact Hours: 4
Section: 22
Class Hours: Tuesday 2:00 PM – 5:20PM Location: M-204

2: Instructor: Dr. Ravi Rao

Office hours: Mon. 4:30-5:30pm; Tues. 1:10pm-2pm; Fri: 1:30-2:30 pm
and other times by appointment
Phone: 201-692-2130
Email: [email protected] (Please state “EENG2287 Section 21” in the subject of your email)
3: TEXTBOOKS. BOTH ARE REQUIRED
1) PRINT TEXTBOOK
Digital Computer Design and Computer Architecture by Harris & Harris, 2nd edition. (Note:
the 1st edition is available via FDU e-brary (online). You may use this edition, though the 2 nd
edition is recommended).
Companion resources (e.g. powerpoint slides) are available at the following website
https://textbooks.elsevier.com/web/product_details.aspx?isbn=9780123944245

2) zyBooks “Microprocessor Design I”. Instructions to access this:

1. Sign in or create an account at learn.zybooks.com
2. Enter zyBook code “FDUEENG2287EGTE2287Section22Fall2024” and subscribe.
3. The cost is $64, and it is mandatory for you to purchase this online book. The
subscription will last for one semester.

OTHER RESOURCES
• FDU WebMail account
• FDU WebCampus account
4: COURSE DESCRIPTION:
Introduction to microprocessors and microcomputers. The MIPS reduced-
instruction-set (RISC) architecture is covered in detail including the memory
addressing, data types, and register organization. Assembly language instructions
are used to write, execute, and debug assembly language codes.

5: PREREQUISITES:ENGR 2286 Digital System Design

6: COURSE OBJECTIVES AND OUTCOMES:

Objective 1: To learn the fundamentals of microprocessors and microcomputers
Outcome 1.1: Understand the number systems binary, decimal and
hexadecimal. Understand signed number representation.
Outcome 1.2: Understand the general architecture of microcomputer
systems.
Outcome 1.3: Understanding of the evolution of microprocessor
architectures and performance criteria used to compare different
processor families
Objective 2: To understand the software architecture of microprocessors.
Outcome 2.1: Understand the memory address space, various data
types, registers and their applications.
Outcome 2.2: Understand the various registers, their applications, and
limitations
Outcome 2.3: Understand the various addressing modes, and be able to
generate the correct memory address.
Objective 3: To be able to interpret and write simple assembly language programs for
MIPS processors and execute them using the programming tool MARS
Outcome 3.1: Learn the instruction set; understand the syntax/format and its
intended use.
Outcome 3.2: Be able to use the tool MARS to write, load,
assemble, execute and debug assembly language programs
Outcome 3.3: Apply the software design process to develop a program
for a practical application.
Outcome 3.4: Understand the issues of high-level language program
structures on software performance through the analysis and design of
assembly language equivalents for the If-Else, Switch, Do, While, and
For loops
Objective 4: To learn about the latest trends in microcomputing including the
difference of the 32-bit architectures.

2
 Outcome 4.1: Gain an understanding of 80386, 80486 and Pentium
processor software architecture, programming, and microarchitecture
and their impact on microcomputer performance.

7: Course Requirements

Instructions and Formats for Homework Assignments and Lab Projects

All homework must be submitted electronically through Webcampus by the due date
and time. No credit will be given for late work except in unusual circumstances.

EMERGENCY NOTIFICATIONS AND SPECIAL ASSIGNMENTS:

All students enrolled in this course are required to login to their WebCampus for this
course on a daily basis to check for emergency notifications or special announcements
(if any). Students should regularly check their WebCampus e-mail accounts for
messages pertaining to this course. All e-mail correspondences with the professor
should directed to [email protected] with the subject starting with “EENG2287 Sec
22”.

Homework
All homework assignments must be turned in individually by their due date. Late
submissions will be penalized by taking off 50% of the marked points, and accepted
only up to the beginning of the subsequent class period.

8: Attendance and participation

As per the Academic Regulations section of the Student Handbook, “Students are required to
attend class, arrive on time and participate in all courses for which they are enrolled. Class
attendance and participation are essential to academic progress. See Attendance Section of
Academic Regulations in the Student Handbook.

If you cannot attend a specific class, you must notify the instructor ahead of time stating the
reason for missing the class. It will be your responsibility to make yourself aware of the course
material presented and submit homework due for the missed class.

9: GRADING POLICY:

3
 You will not be given any make-up tests and quizzes without justification. You must submit grade
disputes via email within one week after you receive the assessment item.

Attendance & Participation 5%

Homework 15 %
Quizzes 15 %
Labs & Projects 20 %
Midterm 20 %
Final 25 %
Total 100%

This is subject to change.

Grading Scale

90 – 100% A

86 – 89% A-

82 – 85% B+

78 – 81% B

74 – 77% B-

70 – 73% C+

66 – 69% C

62 – 65% C-

54 – 61% D

Less than 54% F

4
10: COURSE SCHEDULE: Subject to change
Topic(s)
1 Chapter 1 — Intro to Microprocessors and Microcomputers
2,3 Chapter 2 — Software Architecture; Quiz 1

4 Chapter 3 — Assembly Language Programming and

Addressing Modes
Chapter 4 — Machine Language Coding
5
6,7 Chapter 5 Microprocessor Programming 1

8 Midterm Exam
9 The Software Design Process
10,11 Chapter 6 — Microprocessor Programming 2; Quiz 2
12,13 Implementing I-ILL Program Structures and their Impact on
Performance
14 Chapter 15 — 386, 486, and Pentium Processor SW and
Microarchitecture
15 Final Exam
Experiments:
Lab 1: Using the MIPS Simulator
Lab 2: Assembling and Executing Instructions
Lab 3: Loading, Executing, and Debugging Programs
Project 1: Working with the Data Transfer, Arithmetic, Logic, Shift,
Compare, and Jump Instructions
Project 2: (Team Design)

11: GHSCSE Policy on Technology and Electronics in the Classroom

During quizzes and exams, you must not have cellphones, smart watches, and any other
communication devices in your possession. Instructor can specify any other restrictions on use

5
of technology. Instructor can also specify whether calculators can be used during exams, if
applicable. If calculators are allowed, they must not have any communication capabilities.

12: Resources for Student Success

For links providing access to all resources listed below, visit, “Syllabus Resources for
Student Success”.
o Academic Advising
o Academic Support Center
o Accommodations (Disability Support Services, Regional Center for Learning
Disabilities, Compass)
o Computer Labs (GHSCSE supports 4 additional Computer Labs in BEC 302, BEC
304, MUS 206, and MUS 207)
o Dean of Students Office
o Housing and Residence Life
o Student Counseling and Psychological Services
o Student Health and Wellness
o Technical Assistance (UTAC)
o Transforming College Campuses
o University Library
o UWILL Counseling Intervention Services (free 24/7)
In addition, any student with a concern who does not know where to turn may reach
out to the Chief Student Experience Officer on your campus.
Metro Campus: Rashard Mills, [email protected] , 201-692-2045

13: University Policies

Students in this course are advised to visit Relevant Academic Policies: NJ | Fairleigh
Dickinson University (fdu.edu) to see all the academic and other policies relevant to this
and every course offered at FDU.
These policies include:
• Academic Honesty and Integrity
• Attendance (Academic Regulations section of Student Handbook)
• Chosen Name Policy
• Diversity, Equity, Inclusion, and Accessibility (DEIA) Commitment Statement
• Grade Appeal Procedure
• Policy on Prohibited Discrimination, Harassment, and Related Misconduct /
FERPA
• Statement on Sexual and Gender Identity
• University Statement of Accommodation

6
14: Additional Information

Announcements will be posted in Webcampus on a regular basis. Please check them

regularly. You MUST be regular in keeping up with the lecture materials and
homeworks.

Instructor Profile: Ravi Rao, PhD. https://www.fdu.edu/profiles/alevoor476_rao/

7
 Chapter 1

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 1 <1>
 Increasing Bit Width
• Extend number from N to M bits (M > N) :
– Sign-extension
– Zero-extension

Copyright © 2012 Elsevier

Chapter 1 <2>
Ravi note:

From Harris, Pg. 17

Chapter 1 <3>
Example 1.14 in the book, pg 18

Chapter 1 <4>
 Sign-Extension
• Sign bit copied to msb’s
• Number value is same Ravi note:
5 == 0101
So twos complement of this is 1011
• Example 1: which is -5 (in twos complement)
– 4-bit representation of 3 = 0011
– 8-bit sign-extended value: 00000011
• Example 2:
– 4-bit representation of -5 = 1011
– 8-bit sign-extended value: 11111011

Chapter 1 <5>
 Zero-Extension
• Zeros copied to msb’s
• Value changes for negative numbers

• Example 1:
– 4-bit value = 00112 = 310
– 8-bit zero-extended value: 00000011 = 310
• Example 2:
– 4-bit value = 1011 = -510
– 8-bit zero-extended value: 00001011 = 1110

Chapter 1 <6>
 Zero-Extension
• Zeros copied to msb’s
• Value changes for negative numbers

• Example 1:
– 4-bit value = 00112 = 310
– 8-bit zero-extended value: 00000011 = 310
• Example 2: Zero padding
– 4-bit value = 1011 = -510 gives wrong
result.
– 8-bit zero-extended value: 00001011 = 1110 -5 = 11

Ravi note: If we just pad zeros to the left,

it doesn’t work for signed numbers. It works for unsigned numbers.

Chapter 1 <7>
 Inserted by Ravi Rao (not in original deck):
One-extension
Sign extending a negative number, ie one that has a “1” in the MSB for a two’s
complement number

Sign extend: 1101 from 4 bits to 8 bits: (note: 1101 is -3 in base 10. This is a signed
two’s complement number)

Just copy the leading 1 four times → 1111 1101

Check: this number is -2^7 + 111 1101 = -128 + 125 = -3

Alternately, take the two’s complement of 1111 1101, which is 3.
Do this by flipping the bits and adding 1 to the number.
This gives the magnitude of the number, and we know the sign is negative (MSB is 1).
So this number is -3. Chapter 1 <8>
 Number System Comparison
Number System Range
Unsigned [0, 2N-1]
Sign/Magnitude [-(2N-1-1), 2N-1-1]
Two’s Complement [-2N-1, 2N-1-1]

For example, 4-bit representation:

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Unsigned 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Two's Complement

0000
1111 1110 1101 1100 1011 1010 1001
1000
0001 0010 0011 0100 0101 0110 0111 Sign/Magnitude

Chapter 1 <9>